diff mbox series

[v2,3/8] common/cnxk: add API to check CPT IQ is full

Message ID 9f0c4db1de799f820c3a81376a5178b78fbbe01d.1630584303.git.sthotton@marvell.com (mailing list archive)
State Superseded, archived
Delegated to: akhil goyal
Headers show
Series Crypto adapter support for Marvell CNXK driver | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Shijith Thotton Sept. 2, 2021, 12:17 p.m. UTC
Added flow control based check to determine CPT IQ is full.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
---
 drivers/common/cnxk/roc_cpt.c      |  6 ++++--
 drivers/common/cnxk/roc_cpt.h      | 11 +++++++++++
 drivers/common/cnxk/roc_cpt_priv.h |  6 ------
 3 files changed, 15 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index c001497f74..5e35d1bdda 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -464,6 +464,8 @@  cpt_iq_init(struct roc_cpt_lf *lf)
 	plt_write64(lf_q_size.u, lf->rbase + CPT_LF_Q_SIZE);
 
 	lf->fc_addr = (uint64_t *)addr;
+	lf->fc_hyst_bits = plt_log2_u32(lf->nb_desc) / 2;
+	lf->fc_thresh = lf->nb_desc - (lf->nb_desc % (1 << lf->fc_hyst_bits));
 }
 
 int
@@ -809,8 +811,8 @@  roc_cpt_iq_enable(struct roc_cpt_lf *lf)
 	lf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL);
 	lf_ctl.s.ena = 1;
 	lf_ctl.s.fc_ena = 1;
-	lf_ctl.s.fc_up_crossing = 1;
-	lf_ctl.s.fc_hyst_bits = CPT_FC_NUM_HYST_BITS;
+	lf_ctl.s.fc_up_crossing = 0;
+	lf_ctl.s.fc_hyst_bits = lf->fc_hyst_bits;
 	plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
 
 	cpt_lf_dump(lf);
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 3a2f5b97e1..f0f505a8c2 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -94,6 +94,8 @@  struct roc_cpt_lf {
 	uint16_t msixoff;
 	uint16_t pf_func;
 	uint64_t *fc_addr;
+	uint32_t fc_hyst_bits;
+	uint64_t fc_thresh;
 	uint64_t io_addr;
 	uint8_t *iq_vaddr;
 	struct roc_nix *inl_outb_nix;
@@ -121,6 +123,15 @@  struct roc_cpt_rxc_time_cfg {
 	uint16_t zombie_thres;
 };
 
+static inline int
+roc_cpt_is_iq_full(struct roc_cpt_lf *lf)
+{
+	if (*lf->fc_addr < lf->fc_thresh)
+		return 0;
+
+	return 1;
+}
+
 int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt,
 				   struct roc_cpt_rxc_time_cfg *cfg);
 int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);
diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h
index 0880ec098d..21911e5d79 100644
--- a/drivers/common/cnxk/roc_cpt_priv.h
+++ b/drivers/common/cnxk/roc_cpt_priv.h
@@ -5,12 +5,6 @@ 
 #ifndef _ROC_CPT_PRIV_H_
 #define _ROC_CPT_PRIV_H_
 
-/* Set number of hystbits to 6.
- * This will trigger the FC writes whenever number of outstanding commands in
- * the queue becomes multiple of 32.
- */
-#define CPT_FC_NUM_HYST_BITS 6
-
 struct cpt {
 	struct plt_pci_device *pci_dev;
 	struct dev dev;