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[v2,2/2] event/octeontx2: configure crypto adapter xaq pool

Message ID 66a5cdfce8b20d07596c44c448029aefbbf7fe58.1619439044.git.sthotton@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Jerin Jacob
Headers show
Series event/octeontx2: fixes for crypto adapter | expand

Checks

Context Check Description
ci/iol-mellanox-Performance success Performance Testing PASS
ci/github-robot success github build: passed
ci/iol-testing success Testing PASS
ci/iol-abi-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/intel-Testing success Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/Intel-compilation success Compilation OK
ci/checkpatch success coding style OK

Commit Message

Shijith Thotton April 26, 2021, 12:21 p.m. UTC
Configure xaq pool based on number of in-use crypto queues to avoid CPT
add work failure due to xaq buffer run out. This patch configures
OTX2_CPT_DEFAULT_CMD_QLEN number of xae entries per queue pair.

Fixes: 29768f78d5a7 ("event/octeontx2: add crypto adapter framework")

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 drivers/event/octeontx2/otx2_evdev_adptr.c        | 2 +-
 drivers/event/octeontx2/otx2_evdev_crypto_adptr.c | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/event/octeontx2/otx2_evdev_adptr.c b/drivers/event/octeontx2/otx2_evdev_adptr.c
index d69f269df..d85c3665c 100644
--- a/drivers/event/octeontx2/otx2_evdev_adptr.c
+++ b/drivers/event/octeontx2/otx2_evdev_adptr.c
@@ -1,5 +1,5 @@ 
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
+ * Copyright(C) 2019-2021 Marvell.
  */
 
 #include "otx2_evdev.h"
diff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
index ed600a659..d9a002625 100644
--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
+++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
@@ -89,6 +89,14 @@  otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,
 	sso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F;
 	sso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev);
 
+	/* Update crypto adapter xae count */
+	if (queue_pair_id == -1)
+		sso_evdev->adptr_xae_cnt +=
+			vf->nb_queues * OTX2_CPT_DEFAULT_CMD_QLEN;
+	else
+		sso_evdev->adptr_xae_cnt += OTX2_CPT_DEFAULT_CMD_QLEN;
+	sso_xae_reconfigure((struct rte_eventdev *)(uintptr_t)dev);
+
 	return 0;
 }