diff mbox series

[v1,05/24] net/igc/base: reset loop variable

Message ID	6538bb0ae11e2ae5c9787f925a8cf63251638f6c.1738858026.git.anatoly.burakov@intel.com (mailing list archive)
State	Accepted
Delegated to:	Bruce Richardson
Headers	From: Anatoly Burakov <anatoly.burakov@intel.com> To: dev@dpdk.org, Alvin Zhang <alvinx.zhang@intel.com>, Ferruh Yigit <ferruh.yigit@intel.com> Subject: [PATCH v1 05/24] net/igc/base: reset loop variable Date: Thu, 6 Feb 2025 16:08:28 +0000 Message-ID: <6538bb0ae11e2ae5c9787f925a8cf63251638f6c.1738858026.git.anatoly.burakov@intel.com> In-Reply-To: <cover.1738858026.git.anatoly.burakov@intel.com> References: <cover.1738328106.git.anatoly.burakov@intel.com> <cover.1738858026.git.anatoly.burakov@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: dev-bounces@dpdk.org
Series	Fixes for igc and e1000 \| [v1,00/24] Fixes for igc and e1000 [v1,01/24] net/igc/base: fix deadlock in i225 [v1,02/24] net/igc/base: fix infinite loop [v1,03/24] net/igc/base: fix bitwise op type mismatch [v1,04/24] net/igc/base: increase PHY power up delay [v1,05/24] net/igc/base: reset loop variable [v1,06/24] net/igc/base: fix LTR for i225 [v1,07/24] net/igc/base: fix typo in LTR calculation [v1,08/24] net/igc/base: fix unused value [v1,09/24] net/igc/base: fix semaphore timeout value [v1,10/24] net/igc/base: fix iterator type [v1,11/24] net/igc/base: fix MAC addr hash bit shift [v1,12/24] net/igc/base: fix data type in MAC hash [v1,13/24] net/igc/base: fix static analysis warning [v1,14/24] net/e1000/base: fix semaphore timeout value [v1,15/24] net/e1000/base: correct mPHY access logic [v1,16/24] net/e1000/base: fix iterator type [v1,17/24] net/e1000/base: fix MAC addr hash bit shift [v1,18/24] net/e1000/base: fix data type in MAC hash [v1,19/24] net/e1000/base: fix uninitialized variable usage [v1,20/24] net/e1000/base: fix static analysis warning [v1,21/24] net/e1000/base: fix static analysis warning [v1,22/24] net/e1000/base: fix reset for 82580 [v1,23/24] net/e1000/base: fix unchecked return [v1,24/24] net/e1000/base: skip MANC check for 82575

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Burakov, Anatoly Feb. 6, 2025, 4:08 p.m. UTC

From: Sasha Neftin <sasha.neftin@intel.com>

When writing to Shadow RAM, we set rev_val on success, but since the value
is already set to success initially, it is possible for none of the writes
to be successful, yet ret_val will still be set to success. Fix it by
resetting the ret_val to failure before every loop iteration.

Fixes: 8cb7c57d9b3c ("net/igc: support device initialization")
Cc: stable@dpdk.org

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/intel/igc/base/igc_i225.c | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/drivers/net/intel/igc/base/igc_i225.c b/drivers/net/intel/igc/base/igc_i225.c
index 1277f59885..003c060215 100644
--- a/drivers/net/intel/igc/base/igc_i225.c
+++ b/drivers/net/intel/igc/base/igc_i225.c
@@ -565,6 +565,7 @@  static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,
 	}
 
 	for (i = 0; i < words; i++) {
+		ret_val = -IGC_ERR_NVM;
 		eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) |
 			(data[i] << IGC_NVM_RW_REG_DATA) |
 			IGC_NVM_RW_REG_START;