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DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1879; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 3IWF1FtEsQElrwY0voXujkUHMg3y6EPQXMDaEV0jRmtHm85Sq78vx6nPWFDodhQh+s7zXr5rxkOQ9UHZa7woIjbE2RW/Y7RMcOmoTyP6eJPdFIUgyL8HFijdCLrvO7DlpoaphGrOJRjy6PmkvQRbBbTrh6NFp3f/rVvcEjZWGOfJGbl/cqDVtf6x6PHY8/LJVlTDYtVPoQ3F3U/JB4KAX63NP1iJt4NdADmuxVrhAEeOchSzhukyLKaCkYNeYul+2y96OzyCeR+R0mjYf8tIcbS9wP56iRHcdTHqzx9RoxaMVdaBUVW/nhvQs/Voe7+e+EoA9UKgurTQ5iVf/YnVZfAfGWI7lX0t6poztoB+q1U= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 58263b69-cdc7-49bf-630f-08d630332169 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:08.7168 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1879 Subject: [dpdk-dev] [PATCH v6 03/22] net/atlantic: add hardware registers access routines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add implementation for hardware registers access routines. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 1 + drivers/net/atlantic/atl_hw_regs.c | 52 +++++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_hw_regs.h | 53 ++++++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_types.h | 4 +++ drivers/net/atlantic/meson.build | 1 + 5 files changed, 111 insertions(+) create mode 100644 drivers/net/atlantic/atl_hw_regs.c create mode 100644 drivers/net/atlantic/atl_hw_regs.h diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index e42ce5b178ab..8613ced71732 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -23,5 +23,6 @@ LDLIBS += -lrte_bus_pci # all source are stored in SRCS-y # SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/atl_hw_regs.c b/drivers/net/atlantic/atl_hw_regs.c new file mode 100644 index 000000000000..bd42c8341e2b --- /dev/null +++ b/drivers/net/atlantic/atl_hw_regs.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File aq_hw_utils.c: Definitions of helper functions used across + * hardware layer. + */ + +#include "atl_hw_regs.h" + +#include +#include + +void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, + u32 shift, u32 val) +{ + if (msk ^ ~0) { + u32 reg_old, reg_new; + + reg_old = aq_hw_read_reg(aq_hw, addr); + reg_new = (reg_old & (~msk)) | (val << shift); + + if (reg_old != reg_new) + aq_hw_write_reg(aq_hw, addr, reg_new); + } else { + aq_hw_write_reg(aq_hw, addr, val); + } +} + +u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift) +{ + return ((aq_hw_read_reg(aq_hw, addr) & msk) >> shift); +} + +u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg) +{ + return rte_le_to_cpu_32(rte_read32((u8 *)hw->mmio + reg)); +} + +void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value) +{ + rte_write32((rte_cpu_to_le_32(value)), (u8 *)hw->mmio + reg); +} + +int aq_hw_err_from_flags(struct aq_hw_s *hw) +{ + int err = 0; + + if (aq_hw_read_reg(hw, 0x10U) == ~0U) + return -ENXIO; + + return err; +} diff --git a/drivers/net/atlantic/atl_hw_regs.h b/drivers/net/atlantic/atl_hw_regs.h new file mode 100644 index 000000000000..a2d6ca804e5e --- /dev/null +++ b/drivers/net/atlantic/atl_hw_regs.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File aq_hw_utils.h: Declaration of helper functions used across hardware + * layer. + */ + +#ifndef AQ_HW_UTILS_H +#define AQ_HW_UTILS_H + +#include +#include +#include +#include +#include +#include "atl_common.h" +#include "atl_types.h" + + +#ifndef HIDWORD +#define LODWORD(_qw) ((u32)(_qw)) +#define HIDWORD(_qw) ((u32)(((_qw) >> 32) & 0xffffffff)) +#endif + +#define AQ_HW_SLEEP(_US_) rte_delay_ms(_US_) + +#define mdelay rte_delay_ms +#define udelay rte_delay_us +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#define BIT(x) (1UL << (x)) + +#define AQ_HW_WAIT_FOR(_B_, _US_, _N_) \ +do { \ + unsigned int AQ_HW_WAIT_FOR_i; \ + for (AQ_HW_WAIT_FOR_i = _N_; (!(_B_)) && (AQ_HW_WAIT_FOR_i);\ + --AQ_HW_WAIT_FOR_i) {\ + udelay(_US_); \ + } \ + if (!AQ_HW_WAIT_FOR_i) {\ + err = -ETIMEDOUT; \ + } \ +} while (0) + +#define ATL_WRITE_FLUSH(aq_hw) { (void)aq_hw_read_reg(aq_hw, 0x10); } + +void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, + u32 shift, u32 val); +u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift); +u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg); +void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value); +int aq_hw_err_from_flags(struct aq_hw_s *hw); + +#endif /* AQ_HW_UTILS_H */ diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index d8c2560807d3..725b0c4dc670 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -22,4 +22,8 @@ typedef uint64_t u64; #define min(a, b) RTE_MIN(a, b) #define max(a, b) RTE_MAX(a, b) +struct aq_hw_s { + void *mmio; +}; + #endif diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index c5a2546ef657..cd6a0f637a7d 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -3,4 +3,5 @@ sources = files( 'atl_ethdev.c', + 'atl_hw_regs.c', )