From patchwork Wed Aug 7 15:09:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57542 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 932D74C91; Wed, 7 Aug 2019 17:09:56 +0200 (CEST) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by dpdk.org (Postfix) with ESMTP id E62EB2BAF for ; Wed, 7 Aug 2019 17:09:42 +0200 (CEST) Received: by mail-wr1-f67.google.com with SMTP id p13so17167393wru.10 for ; Wed, 07 Aug 2019 08:09:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=8O5D8oaKajRKAycKCWBOPr1JPd+AjkcPPBYy+pLUd5Q=; b=J5argAjrsqxIF10vQ+trawcTTbSnBUkGJ2Ubz6jjrfR5kd9kjppkUkI5a8J+6V4Dbm 3ypvd7LGhbenHwPp1/vBk9hDPiXpC6uUrFsiAJFnZPPQ9fX0sKySE9753yiaj3JZELc8 tEWldKySL9uiESkdrv+tuk0NZU/OsTK93EW0ao7A5ictY4iE/In5hxCzJsFwxC2GgXxr nQg93VkTpTdQ7S0B5ArlUi4P8sNBK4IqFaqAWFJnQN3T7xN00+Jca/p9PH+MuSvGlH/d orjwsjlQYge8IYOf8Zvr33iEBDsRYQUVVVmNJ8QXy5WoALKwC+NKcVVg+6Nx2B+VR5Br Jm5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=8O5D8oaKajRKAycKCWBOPr1JPd+AjkcPPBYy+pLUd5Q=; b=YTTi9djvsHtEnVerwxbxSYKhb2HnbXlJ14MaYnqbYzoDiNfLh6HWtdLcjsMZ75Gpqv 1F4lIKdpzu9B1kqUCnTL0dcK18jUHKCc8N7u9lJc+DrJAY9tYUyeYJ+6U/MhwWkCPWkV rZxieuV9zLPR+gdKgVP2qTrRjpZ2ZBhoxqlyBhbqLmdaYNzn8SdjBHSTPea3/35EIk5g 9SC80/RWKnSPW7h6wimK21Bh5mgjXASOZf4V7Y9dXJ5zZTYarwVLZnYnYmdrQhWwW7no R2Zd9w0iq++uIym+Ys5pwyug7W6MqovVmhOHpHOhNptNZ1Bk+t4gTHwoH4jx577Xnvj6 jUrg== X-Gm-Message-State: APjAAAUOqb4RIzm8dDR+WJOY9LeJwpSYYJFLOew+YtrD26yh+ug34MTw b+lL9h/G4dGys7ZKGvSwjOzj7yJVkQ== X-Google-Smtp-Source: APXvYqwic2rt5JFw5Ykd0Hwc7PXK+NjT2JnicUPhi+BrLYuBg6np0fHA7GoxsmWLvm0Hkc1pXn8OIQ== X-Received: by 2002:a5d:50d1:: with SMTP id f17mr10744367wrt.124.1565190582406; Wed, 07 Aug 2019 08:09:42 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:41 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:14 +0200 Message-Id: <5411f97091b9d7806b88f847d138bd0ebb4024d3.1565190405.git.thierry.herbelot@6wind.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 05/12] net/ixgbe: fix Tx descriptor status api X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The Tx descriptor status api was not behaving as expected. This API is used to inspect the content of the descriptors in the Tx ring to determine the length of the Tx queue. Since the software advances the tail pointer and the hardware advances the head pointer, the Tx queue is located before txq->tx_tail in the ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20) should inspect the 20th descriptor before the tail, not after. As before, we still need to take care about only checking descriptors that have the RS bit. Additionally, we can avoid an access to the ring if offset is greater or equal to nb_tx_desc - nb_tx_free. Fixes: 5da8b8814178 ("net/ixgbe: implement descriptor status API") Cc: stable@dpdk.org Signed-off-by: Olivier Matz --- drivers/net/ixgbe/ixgbe_rxtx.c | 45 +++++++++++++++++++++++++++++++----------- drivers/net/ixgbe/ixgbe_rxtx.h | 1 + 2 files changed, 34 insertions(+), 12 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index edcfa60cec98..4abc2fe37488 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -2627,10 +2627,15 @@ ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, hw->mac.type == ixgbe_mac_X540_vf || hw->mac.type == ixgbe_mac_X550_vf || hw->mac.type == ixgbe_mac_X550EM_x_vf || - hw->mac.type == ixgbe_mac_X550EM_a_vf) + hw->mac.type == ixgbe_mac_X550EM_a_vf) { txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx)); - else + txq->tdh_reg_addr = IXGBE_PCI_REG_ADDR(hw, + IXGBE_VFTDH(queue_idx)); + } else { txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx)); + txq->tdh_reg_addr = IXGBE_PCI_REG_ADDR(hw, + IXGBE_TDH(txq->reg_idx)); + } txq->tx_ring_phys_addr = tz->iova; txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr; @@ -3163,22 +3168,38 @@ ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) { struct ixgbe_tx_queue *txq = tx_queue; volatile uint32_t *status; - uint32_t desc; + int32_t desc, dd; if (unlikely(offset >= txq->nb_tx_desc)) return -EINVAL; + if (offset >= txq->nb_tx_desc - txq->nb_tx_free) + return RTE_ETH_TX_DESC_DONE; + + desc = txq->tx_tail - offset - 1; + if (desc < 0) + desc += txq->nb_tx_desc; - desc = txq->tx_tail + offset; - /* go to next desc that has the RS bit */ - desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * - txq->tx_rs_thresh; - if (desc >= txq->nb_tx_desc) { - desc -= txq->nb_tx_desc; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; + /* offset is too small, no other way than reading PCI reg */ + if (unlikely(offset < txq->tx_rs_thresh)) { + int16_t tx_head, queue_size; + tx_head = ixgbe_read_addr(txq->tdh_reg_addr); + queue_size = txq->tx_tail - tx_head; + if (queue_size < 0) + queue_size += txq->nb_tx_desc; + return queue_size > offset ? RTE_ETH_TX_DESC_FULL : + RTE_ETH_TX_DESC_DONE; } - status = &txq->tx_ring[desc].wb.status; + /* index of the dd bit to look at */ + dd = (desc / txq->tx_rs_thresh + 1) * txq->tx_rs_thresh - 1; + + /* In full featured mode, RS bit is only set in the last descriptor */ + /* of a multisegments packet */ + if (!(txq->offloads == 0 && + txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) + dd = txq->sw_ring[dd].last_id; + + status = &txq->tx_ring[dd].wb.status; if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)) return RTE_ETH_TX_DESC_DONE; diff --git a/drivers/net/ixgbe/ixgbe_rxtx.h b/drivers/net/ixgbe/ixgbe_rxtx.h index 505d344b9cee..05fd4167576c 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.h +++ b/drivers/net/ixgbe/ixgbe_rxtx.h @@ -201,6 +201,7 @@ struct ixgbe_tx_queue { struct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for vector PMD */ }; volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */ + volatile uint32_t *tdh_reg_addr; /**< Address of TDH register. */ uint16_t nb_tx_desc; /**< number of TX descriptors. */ uint16_t tx_tail; /**< current value of TDT reg. */ /**< Start freeing TX buffers if there are less free descriptors than