diff mbox series

cycles: add isb before read cntvct_el0

Message ID 4099DE2E54AFAD489356C6C9161D53339729EC8E@DGGEML502-MBX.china.huawei.com (mailing list archive)
State Superseded, archived
Delegated to: David Marchand
Headers show
Series cycles: add isb before read cntvct_el0 | expand

Checks

Context Check Description
ci/Intel-compilation success Compilation OK
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-testing success Testing PASS
ci/travis-robot warning Travis build: failed
ci/checkpatch warning coding style issues

Commit Message

Linhaifeng March 9, 2020, 10:58 a.m. UTC
We should use isb rather than dsb to sync system counter to cntvct_el0.

Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
---
 lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++
 lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++
 2 files changed, 5 insertions(+)
diff mbox series

Patch

diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index 859ae129d..2587f98a2 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -21,6 +21,7 @@  extern "C" {
 
 #define dsb(opt) asm volatile("dsb " #opt : : : "memory")
 #define dmb(opt) asm volatile("dmb " #opt : : : "memory")
+#define isb()    (asm volatile("isb" : : : "memory"))
 
 #define rte_mb() dsb(sy)
 
@@ -44,6 +45,8 @@  extern "C" {
 
 #define rte_cio_rmb() dmb(oshld)
 
+#define rte_isb() isb()
+
 /*------------------------ 128 bit atomic operations -------------------------*/
 
 #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
index 68e7c7338..29f524901 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
@@ -18,6 +18,7 @@  extern "C" {
  *   The time base for this lcore.
  */
 #ifndef RTE_ARM_EAL_RDTSC_USE_PMU
+
 /**
  * This call is portable to any ARMv8 architecture, however, typically
  * cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
@@ -27,6 +28,7 @@  rte_rdtsc(void)
 {
 	uint64_t tsc;
 
+	rte_isb();
 	asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
 	return tsc;
 }