From patchwork Fri Jan 20 15:27:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?N=C3=A9lio_Laranjeiro?= X-Patchwork-Id: 19844 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 6C45CF947; Fri, 20 Jan 2017 16:28:07 +0100 (CET) Received: from mail-wm0-f48.google.com (mail-wm0-f48.google.com [74.125.82.48]) by dpdk.org (Postfix) with ESMTP id 329DBAB08 for ; Fri, 20 Jan 2017 16:27:52 +0100 (CET) Received: by mail-wm0-f48.google.com with SMTP id r126so41928555wmr.0 for ; Fri, 20 Jan 2017 07:27:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=2aF27esbUm9uLDZrO26xfgoJ05DuK7izNx49lKqcLPc=; b=oejaZ03Xxz63GmjwHBaP3L4IaOUJKbxw+L0IeVBpUcgvtI2LTEWdsDeG2gZvmhZvGH 41jxjzvPckkTehaHsGes9UsaLYTUaCzqaW5poZINsjvTEL/ufTgGN2BzqL67SjZQuhKf yyusXeat5V92w8dYXHaNqKQOXmNQAP+hhfH4M6KQojtRFo7wyWMLzfHlZcNNotQuq5IS Q3aQL7+yAb59gwxL3jf8Gk3sx93OKUTyuzIIDHOHguwfLIJ+wC/1ifspcRoJK3c8mz+h fPXU9xNdK2nkvlzTme0RefI2uTatO7F+UHcGpVa5qIwLLnDHSeaqCGowlJiVgBN/uD8+ upxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=2aF27esbUm9uLDZrO26xfgoJ05DuK7izNx49lKqcLPc=; b=YP7e29IC2nI3lGLKwqnTD9AK7DBBFkI3LFS1twiJ4g9hU9HtU/hgaturIbSVFYlDst saCjbBfPmumHzE5M+2nm5U38/BbPkWTfqLm0CtALyZ/FqJq2O8l1Vz2MRJoemOYVuSzb FGpBZxlkK3BsKOXUaNza8JvD6fkFl7XQLvCFGzr/sypi0hgC2zr9CsYfBwNEfFCDO170 zGIngcAVJKQ6Q3qZNwmuS50yP/Bs8soA0DYdDp5u/QeyGPAhtE2n2SXqT+sfZyYKW0HI k1QsGM2eRweezO3q69Y5sTj+srhI7tZrOTF1EqW2ajRwkfDh35ZzDEL0Tg7dzAAZs4Uz QyLg== X-Gm-Message-State: AIkVDXI9aq/C9B8vvRJrQUhUlFbO3raRCCj43vITNWZ7SdNAEDuUZ2m78/ID0Km06IgWdsEh X-Received: by 10.223.147.7 with SMTP id 7mr2712820wro.165.1484926071498; Fri, 20 Jan 2017 07:27:51 -0800 (PST) Received: from ping.vm.6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id y127sm6649462wmg.12.2017.01.20.07.27.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Jan 2017 07:27:51 -0800 (PST) From: Nelio Laranjeiro To: dev@dpdk.org Cc: Adrien Mazarguil , stable@dpdk.org Date: Fri, 20 Jan 2017 16:27:29 +0100 Message-Id: <3ca6440e12f5c7489673be37ad0bd164938cdf4d.1484925981.git.nelio.laranjeiro@6wind.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <582098dca09b3d3bb70ec24e6c44426a63348392.1484925981.git.nelio.laranjeiro@6wind.com> References: <582098dca09b3d3bb70ec24e6c44426a63348392.1484925981.git.nelio.laranjeiro@6wind.com> In-Reply-To: <582098dca09b3d3bb70ec24e6c44426a63348392.1484925981.git.nelio.laranjeiro@6wind.com> References: <582098dca09b3d3bb70ec24e6c44426a63348392.1484925981.git.nelio.laranjeiro@6wind.com> Subject: [dpdk-dev] [PATCH 2/2] net/mlx5: fix Rx packet validation and type X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Rx checksum validation and packet type offloads are read from the wrong location. Fixes: 501505c5608a ("net/mlx: fix IPv4 and IPv6 packet type") Fixes: 350f4c482e46 ("net/mlx5: fix Rx checksum macros") Fixes: 6218063b39a6 ("net/mlx5: refactor Rx data path") Cc: stable@dpdk.org Signed-off-by: Nelio Laranjeiro Acked-by: Adrien Mazarguil --- drivers/net/mlx5/mlx5_prm.h | 47 +++++++++++++++++++++++++---------------- drivers/net/mlx5/mlx5_rxtx.c | 50 +++++++++++++++++++------------------------- 2 files changed, 50 insertions(+), 47 deletions(-) diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h index d9bb332..755b5d7 100644 --- a/drivers/net/mlx5/mlx5_prm.h +++ b/drivers/net/mlx5/mlx5_prm.h @@ -64,9 +64,6 @@ /* Invalidate a CQE. */ #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4) -/* CQE value to inform that VLAN is stripped. */ -#define MLX5_CQE_VLAN_STRIPPED 0x1 - /* Maximum number of packets a multi-packet WQE can handle. */ #define MLX5_MPW_DSEG_MAX 5 @@ -87,26 +84,41 @@ #define MLX5_OPCODE_TSO MLX5_OPCODE_LSO_MPW /* Compat with OFED 3.3. */ #endif -/* IPv4 packet. */ -#define MLX5_CQE_RX_IPV4_PACKET (1u << 2) +/* CQE value to inform that VLAN is stripped. */ +#define MLX5_CQE_VLAN_STRIPPED (1u << 0) + +/* IPv4 options. */ +#define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1) /* IPv6 packet. */ -#define MLX5_CQE_RX_IPV6_PACKET (1u << 3) +#define MLX5_CQE_RX_IPV6_PACKET (1u << 2) + +/* IPv4 packet. */ +#define MLX5_CQE_RX_IPV4_PACKET (1u << 3) -/* Outer IPv4 packet. */ -#define MLX5_CQE_RX_OUTER_IPV4_PACKET (1u << 7) +/* TCP packet. */ +#define MLX5_CQE_RX_TCP_PACKET (1u << 4) -/* Outer IPv6 packet. */ -#define MLX5_CQE_RX_OUTER_IPV6_PACKET (1u << 8) +/* UDP packet. */ +#define MLX5_CQE_RX_UDP_PACKET (1u << 5) -/* Tunnel packet bit in the CQE. */ -#define MLX5_CQE_RX_TUNNEL_PACKET (1u << 4) +/* IP is fragmented. */ +#define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7) + +/* L2 header is valid. */ +#define MLX5_CQE_RX_L2_HDR_VALID (1u << 8) -/* Outer IP checksum OK. */ -#define MLX5_CQE_RX_OUTER_IP_CSUM_OK (1u << 5) +/* L3 header is valid. */ +#define MLX5_CQE_RX_L3_HDR_VALID (1u << 9) -/* Outer UDP header and checksum OK. */ -#define MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK (1u << 6) +/* L4 header is valid. */ +#define MLX5_CQE_RX_L4_HDR_VALID (1u << 10) + +/* Outer packet, 0 IPv4, 1 IPv6. */ +#define MLX5_CQE_RX_OUTER_PACKET (1u << 1) + +/* Tunnel packet bit in the CQE. */ +#define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0) /* INVALID is used by packets matching no flow rules. */ #define MLX5_FLOW_MARK_INVALID 0 @@ -188,8 +200,7 @@ struct mlx5_cqe { uint32_t rx_hash_res; uint8_t rx_hash_type; uint8_t rsvd1[11]; - uint8_t hds_ip_ext; - uint8_t l4_hdr_type_etc; + uint16_t hdr_type_etc; uint16_t vlan_info; uint8_t rsvd2[12]; uint32_t byte_cnt; diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c index 56c7f78..f88b3eb 100644 --- a/drivers/net/mlx5/mlx5_rxtx.c +++ b/drivers/net/mlx5/mlx5_rxtx.c @@ -1107,23 +1107,20 @@ static inline uint32_t rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe) { uint32_t pkt_type; - uint8_t flags = cqe->l4_hdr_type_etc; + uint16_t flags = ntohs(cqe->hdr_type_etc); - if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) + if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) { pkt_type = TRANSPOSE(flags, - MLX5_CQE_RX_OUTER_IPV4_PACKET, - RTE_PTYPE_L3_IPV4_EXT_UNKNOWN) | - TRANSPOSE(flags, - MLX5_CQE_RX_OUTER_IPV6_PACKET, - RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) | - TRANSPOSE(flags, MLX5_CQE_RX_IPV4_PACKET, RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) | TRANSPOSE(flags, MLX5_CQE_RX_IPV6_PACKET, RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN); - else + pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ? + RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : + RTE_PTYPE_L3_IPV4_EXT_UNKNOWN); + } else { pkt_type = TRANSPOSE(flags, MLX5_CQE_L3_HDR_TYPE_IPV6, @@ -1131,6 +1128,7 @@ rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe) TRANSPOSE(flags, MLX5_CQE_L3_HDR_TYPE_IPV4, RTE_PTYPE_L3_IPV4_EXT_UNKNOWN); + } return pkt_type; } @@ -1248,28 +1246,22 @@ static inline uint32_t rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe) { uint32_t ol_flags = 0; - uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK; - uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK; - - if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) || - (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6)) - ol_flags |= TRANSPOSE(cqe->hds_ip_ext, - MLX5_CQE_L3_OK, - PKT_RX_IP_CKSUM_GOOD); - if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) || - (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) || - (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) || - (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP)) - ol_flags |= TRANSPOSE(cqe->hds_ip_ext, - MLX5_CQE_L4_OK, - PKT_RX_L4_CKSUM_GOOD); + uint16_t flags = ntohs(cqe->hdr_type_etc); + + ol_flags = + TRANSPOSE(flags, + MLX5_CQE_RX_L3_HDR_VALID, + PKT_RX_IP_CKSUM_GOOD) | + TRANSPOSE(flags, + MLX5_CQE_RX_L4_HDR_VALID, + PKT_RX_L4_CKSUM_GOOD); if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun)) ol_flags |= - TRANSPOSE(cqe->l4_hdr_type_etc, - MLX5_CQE_RX_OUTER_IP_CSUM_OK, + TRANSPOSE(flags, + MLX5_CQE_RX_L3_HDR_VALID, PKT_RX_IP_CKSUM_GOOD) | - TRANSPOSE(cqe->l4_hdr_type_etc, - MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK, + TRANSPOSE(flags, + MLX5_CQE_RX_L4_HDR_VALID, PKT_RX_L4_CKSUM_GOOD); return ol_flags; } @@ -1376,7 +1368,7 @@ mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n) pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe); } - if (cqe->l4_hdr_type_etc & + if (cqe->hdr_type_etc & MLX5_CQE_VLAN_STRIPPED) { pkt->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;