@@ -685,21 +685,13 @@ static int nim_ready_100_gb(adapter_info_t *p_info, int port)
return 1;
}
- if (port == 0) {
- /* setTxEqualization(uint8_t intf_no, uint8_t lane, uint32_t pre_tap2,
- * uint32_t main_tap, uint32_t pre_tap1, uint32_t post_tap1)
- */
- nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 0, 0, 44, 2, 9);
- nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 1, 0, 44, 2, 9);
- nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 2, 0, 44, 2, 9);
- nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 3, 0, 44, 2, 9);
-
- } else {
- nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 0, 0, 44, 2, 9);
- nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 1, 0, 44, 2, 9);
- nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 2, 0, 44, 2, 9);
- nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 3, 0, 44, 2, 9);
- }
+ /* setTxEqualization(uint8_t intf_no, uint8_t lane, uint32_t pre_tap2,
+ * uint32_t main_tap, uint32_t pre_tap1, uint32_t post_tap1)
+ */
+ nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 0, 0, 44, 2, 9);
+ nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 1, 0, 44, 2, 9);
+ nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 2, 0, 44, 2, 9);
+ nthw_phy_tile_set_tx_equalization(p_phy_tile, port, 3, 0, 44, 2, 9);
/*
* Perform a full reset. If the RX is in reset from the start this sequence will
@@ -59,7 +59,6 @@ static int nthw_fpga_rst9563_setup(nthw_fpga_t *p_fpga, struct nthw_fpga_rst_nt2
p->mp_fld_rst_mac_rx = nthw_register_get_field(p_curr_reg, RST9563_RST_MAC_RX);
p->mp_fld_rst_mac_tx = NULL;
p->mp_fld_rst_ptp = nthw_register_get_field(p_curr_reg, RST9563_RST_PTP);
- p->mp_fld_rst_ptp = nthw_register_get_field(p_curr_reg, RST9563_RST_PTP);
p->mp_fld_rst_ts = nthw_register_get_field(p_curr_reg, RST9563_RST_TS);
p->mp_fld_rst_ptp_mmcm = nthw_register_get_field(p_curr_reg, RST9563_RST_PTP_MMCM);
p->mp_fld_rst_ts_mmcm = nthw_register_get_field(p_curr_reg, RST9563_RST_TS_MMCM);
@@ -93,9 +93,6 @@ int nthw_rac_init(nthw_rac_t *p, nthw_fpga_t *p_fpga, struct fpga_info_s *p_fpga
if (p->mp_reg_dbg_data)
p->mp_fld_dbg_data = nthw_register_query_field(p->mp_reg_dbg_data, RAC_DBG_DATA_D);
- else
- p->mp_reg_dbg_data = NULL;
-
p->mp_reg_rab_ib_data = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_IB_DATA);
p->mp_fld_rab_ib_data = nthw_register_get_field(p->mp_reg_rab_ib_data, RAC_RAB_IB_DATA_D);
@@ -254,7 +254,6 @@ int nthw_stat_init(nthw_stat_t *p, nthw_fpga_t *p_fpga, int n_instance)
p->mn_stat_layout_version = 1;
} else {
- p->mn_stat_layout_version = 0;
NT_LOG(ERR, NTHW, "%s: unknown module_version 0x%08lX layout=%d",
p_adapter_id_str, n_module_version_packed64, p->mn_stat_layout_version);
}