diff mbox series

net/mlx5: support ESP in non-template RSS expansion

Message ID 20250217071316.37195-1-getelson@nvidia.com (mailing list archive)
State Awaiting Upstream
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: support ESP in non-template RSS expansion |

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ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
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Commit Message

Gregory Etelson Feb. 17, 2025, 7:13 a.m. UTC 
Add support for the ESP protocol in non-template RSS expansion.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
---
 drivers/net/mlx5/mlx5_nta_rss.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Dariusz Sosnowski Feb. 26, 2025, 8:36 a.m. UTC | #1 
> -----Original Message-----
> From: Gregory Etelson <getelson@nvidia.com>
> Sent: Monday, February 17, 2025 8:13 AM
> To: dev@dpdk.org
> Cc: Gregory Etelson <getelson@nvidia.com>; Maayan Kashani
> <mkashani@nvidia.com>; Raslan Darawsheh <rasland@nvidia.com>
> Subject: [PATCH] net/mlx5: support ESP in non-template RSS expansion
> 
> External email: Use caution opening links or attachments
> 
> 
> Add support for the ESP protocol in non-template RSS expansion.
> 
> Signed-off-by: Gregory Etelson <getelson@nvidia.com>

Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

Best regards,
Dariusz Sosnowski
Raslan Darawsheh Feb. 26, 2025, 1:55 p.m. UTC | #2 
Hi,

From: Gregory Etelson <getelson@nvidia.com>
Sent: Monday, February 17, 2025 9:13 AM
To: dev@dpdk.org
Cc: Gregory Etelson; Maayan Kashani; Raslan Darawsheh
Subject: [PATCH] net/mlx5: support ESP in non-template RSS expansion

Add support for the ESP protocol in non-template RSS expansion.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>


Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_nta_rss.c b/drivers/net/mlx5/mlx5_nta_rss.c
index 602df301ac..8f00510445 100644
--- a/drivers/net/mlx5/mlx5_nta_rss.c
+++ b/drivers/net/mlx5/mlx5_nta_rss.c
@@ -123,7 +123,7 @@  mlx5_nta_rss_expand_l3_l4(struct mlx5_nta_rss_ctx *rss_ctx,
 			  uint64_t rss_types, uint64_t rss_l3_types)
 {
 	int ret;
-	int ptype_l3, ptype_l4_udp, ptype_l4_tcp, ptype_l4_esp = 0;
+	int ptype_l3, ptype_l4_esp, ptype_l4_udp, ptype_l4_tcp;
 	uint64_t rss = rss_types &
 		 ~(rss_l3_types == MLX5_IPV4_LAYER_TYPES ?
 		  MLX5_IPV6_LAYER_TYPES : MLX5_IPV4_LAYER_TYPES);
@@ -132,12 +132,13 @@  mlx5_nta_rss_expand_l3_l4(struct mlx5_nta_rss_ctx *rss_ctx,
 	if (rss_ctx->rss_conf->level < 2) {
 		ptype_l3 = rss_l3_types == MLX5_IPV4_LAYER_TYPES ?
 			   RTE_PTYPE_L3_IPV4 : RTE_PTYPE_L3_IPV6;
-		ptype_l4_esp = RTE_PTYPE_TUNNEL_ESP;
+		ptype_l4_esp = RTE_PTYPE_L4_ESP;
 		ptype_l4_udp = RTE_PTYPE_L4_UDP;
 		ptype_l4_tcp = RTE_PTYPE_L4_TCP;
 	} else {
 		ptype_l3 = rss_l3_types == MLX5_IPV4_LAYER_TYPES ?
 			   RTE_PTYPE_INNER_L3_IPV4 : RTE_PTYPE_INNER_L3_IPV6;
+		ptype_l4_esp = RTE_PTYPE_INNER_L4_ESP;
 		ptype_l4_udp = RTE_PTYPE_INNER_L4_UDP;
 		ptype_l4_tcp = RTE_PTYPE_INNER_L4_TCP;
 	}
@@ -469,7 +470,7 @@  flow_nta_create_single(struct rte_eth_dev *dev,
  */
 #define MLX5_PTYPE_RSS_OUTER_MASK (RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L3_IPV6 | \
 				  RTE_PTYPE_L4_UDP | RTE_PTYPE_L4_TCP | \
-				  RTE_PTYPE_TUNNEL_ESP)
+				  RTE_PTYPE_L4_ESP)
 #define MLX5_PTYPE_RSS_INNER_MASK (RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L3_IPV6 | \
 				  RTE_PTYPE_INNER_L4_TCP | RTE_PTYPE_INNER_L4_UDP)
 
@@ -630,4 +631,3 @@  flow_nta_handle_rss(struct rte_eth_dev *dev,
 }
 
 #endif
-