From patchwork Mon Oct 7 19:33:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 145334 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BBB6345AD8; Mon, 7 Oct 2024 21:38:00 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EE93B40674; Mon, 7 Oct 2024 21:35:36 +0200 (CEST) Received: from egress-ip42b.ess.de.barracuda.com (egress-ip42b.ess.de.barracuda.com [18.185.115.246]) by mails.dpdk.org (Postfix) with ESMTP id 36EB540A4B for ; Mon, 7 Oct 2024 21:35:24 +0200 (CEST) Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03lp2233.outbound.protection.outlook.com [104.47.51.233]) by mx-outbound43-193.eu-central-1c.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Mon, 07 Oct 2024 19:35:22 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=oRYT1Ky/n+cqFNZR7ll2aPjQd8MdDtYKPcEbiWWAM7yCWC+H0ezOfYGfR8h3z4gLTeLW6i8LRZAxMi5FZXs1m4KEdWyfgZKX6Zq+bN656y8vqIf6F2NSra8HE8UnC623mtchtlGG8mCXhxpjpyAFI/5izTuHmx/zqJPYIjeWYIXX02L5TED0z/0bZ9W1XaksK8PXEZ+v75mpdX+GB54s2zC5DKdV/fZjFRUl025PBfQuot77XzBXj5/W+bMUVCfHyU/ezW78tlksiG1Y/+BEc/ySDZK1ocRdq1l4uXIZOGZ+R4Uy9Ipfs5KRZtj74uwzwI2ydqP5Ju7kKs0TvSL9YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MgqqTEDvbxf5p0XpsaqXF430vmRHUeWGS7OoPanx0HU=; b=L85TdEF2H5/lifWYVjtGJTmWFJtZBF0BE/qH2ZX8K28ymxIEWWv88plwLIGLioDVmXSvWKKCeCXGelttZHLrXxClJe+g/0kPZlVXtCZSolWq6YPapGZL339C5HHceJf03KhrmmAuYYH4bymn3pQuj0Fxyb42Q7850P47WmYclGWnMgNwnuxK4YqCaYqbYyHgbpWhFL4Sc2YAlvv+XbRd5IYhM93kePvnfMa3HnZ4oQeaHpzDZLPZOzu57O0g7FsReShidOGSew6475NOEUBj/7n+nzxU986JHTeCA91DrKugjy7yJEhm366Onq7j9T4JIMEHVr363zPz8qsY1dfG7A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 178.72.21.4) smtp.rcpttodomain=dpdk.org smtp.mailfrom=napatech.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=napatech.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=napatech.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MgqqTEDvbxf5p0XpsaqXF430vmRHUeWGS7OoPanx0HU=; b=IT3xFPKaMROuFu3SiaMlC3i3wr7J/EXNa7Rc1VHgp9+VkRU5QoctdfyzJR3f23yXkrACXq6NGoScA/btq1dQxrtL3iK8MEncFWbbyGJMlTvyw+SgqobCEPl3k97yrNj1hPlq4AfyZzmjQmUK55z+AuTQae3+WGVkjMVcH0VvTWQ= Received: from DB9PR05CA0016.eurprd05.prod.outlook.com (2603:10a6:10:1da::21) by AM0P190MB0625.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:199::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.22; Mon, 7 Oct 2024 19:35:20 +0000 Received: from DB1PEPF000509EC.eurprd03.prod.outlook.com (2603:10a6:10:1da:cafe::b6) by DB9PR05CA0016.outlook.office365.com (2603:10a6:10:1da::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7982.34 via Frontend Transport; Mon, 7 Oct 2024 19:35:20 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 178.72.21.4) smtp.mailfrom=napatech.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=napatech.com; Received-SPF: Fail (protection.outlook.com: domain of napatech.com does not designate 178.72.21.4 as permitted sender) receiver=protection.outlook.com; client-ip=178.72.21.4; helo=localhost.localdomain; Received: from localhost.localdomain (178.72.21.4) by DB1PEPF000509EC.mail.protection.outlook.com (10.167.242.70) with Microsoft SMTP Server id 15.20.8048.13 via Frontend Transport; Mon, 7 Oct 2024 19:35:20 +0000 From: Serhii Iliushyk To: dev@dpdk.org Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com, andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com, Oleksandr Kolomeiets Subject: [PATCH v2 21/50] net/ntnic: add copier (Tx CPY) flow module Date: Mon, 7 Oct 2024 21:33:57 +0200 Message-ID: <20241007193436.675785-22-sil-plv@napatech.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241007193436.675785-1-sil-plv@napatech.com> References: <20241006203728.330792-2-sil-plv@napatech.com> <20241007193436.675785-1-sil-plv@napatech.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB1PEPF000509EC:EE_|AM0P190MB0625:EE_ X-MS-Office365-Filtering-Correlation-Id: 1720004d-af2a-48ae-997d-08dce7072e33 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: Qir6HJwyKFj7yic0hMznIdrflszkgSfmmCkrs6l1VbVsq0U41AZIgJlgcBpD5/kNIgkNXBg94Ui0Dp6Ms4GCeGC4RpxfiEU3wVFpur6FfWc4LnOvw8mhN1sHHFha13ieSAXbcZvFiyuoekfbtVlEUE0NmbVdwfNQ31JsT4oWMXboS2OGgbAyaVub+ZPzTgIWWk5AMAW831S4ElNlSaQmat+wC1xvEb7vCPxvD8jy048OYsfmO9QemhDNX58dA7HdBIPrOYO7I5P5LXZqAMguWEeAiPhlQOxg7vHMRwhNaDbe0sG5pTdZUYbK+Y7ZHEXaMeLzI5X6n7nuCM4O9XZQBJKKOaxuAUDTNMqcoWyOMereHI1bi5OhwIFNEZJCY9O69J/6hMm0cS87c8OM13s3KeVaW+yb4wMDB3wFP7dU+TSZZOB/lSQ3TS1fVia/pOrkrefH9igrHpkIYeF6QA6VOKx4d+dph3F9xeztoVPDK35ETfmuibqNUeudhS/bjGr6OuWqKSETXgFh4nUpxzgO95Pp9jUGvH6lOZuhEaDPC09tZxmvYYMPhrIol2jQ/IHo6XhRCZsAbARHNZyPGBn+t3Pa/isvtfx6DfWhCgaWcWTQLGRtyiZvbZpPEAkbHjmko+37EDWlk3Jn43kJyBwldqTR+TfWuSosVWSYFZCzTU1Tqd370sUpC/z1KXjrxy1GOI4kJVj3PsrxEcXoI0XOTM4RnCopqveCabB7Yp3jF+hwD68epWVTV+XFjmFEETdU1YGxIxvZP49Dub8ax8jiTv4jN6nY0T2k+L9vCUJ8ZFFB+HUejgQRLXB5qhGOSgjggWsUfNaX13Vp0MUUjGxeJFtyBEsJ+F4q9vhVye5XlU9OqZQ1UaAS0A5UvTTK1EgmLOD/Cw4EZQo9FHXcySd0Rg6+E75FBDq1HhpJ5jT+nt8Wwh031xkvlFXBhFWeSpBF9EgA1FIkvPV5ZPVv4VGDRuGJuRyQz7wk+OR6xAJ8ko51Ir9KqIrqugcW+S99iwAEhgKYT+dVUzq5ggLbzCRBZOcoPI66Z3/EG22VQT7Wv8NxZFIRZLTxmnZz5tc01YIMe82ho9HzDt1GnG1Eg/PY9ThsdhHGXrOsmBs5JhIXlCvy3mIS2Nvy3zcwRyEPJlHL0lYJ4X7ri8WTmwYdlqNc+ztIx1TfKix6KbTt1+9Yj1tvTdKEySedNDNH8r2aravJOM45L87s15sbOytNAVzA3kr3bRhrYQnJGjbTnvqNdFcRzS5caaRGXUVRTFoDgaJuTGZIdmdlsDml8E/wll7hMRfo9kMhAes4qQS6kiX0kp+IFtNavDzY4NP3qfoqCvldNxtiO47GRkFfVgc59jRQ1lUa2sKjETPfA5n4202EZVfw5VgJMCp5rKLcEJdM7uK+ X-Forefront-Antispam-Report: CIP:178.72.21.4; CTRY:DK; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:localhost.localdomain; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: Wu9vBxL4TdHuvw1DYG3rcb+wtbYoMCh4ba0uwO2IrdtSGETRcrKDi0FWSXpwnpSXBOylbNFkCCJuVz+0Q3S8w0ECf4rGmpHds0QkDfrGXZMGodzCYOAoegoY7HYeZvOfVzcA5l4EkRnXLwFECft+FS/xGYevEjk68bI+9oGsTfe/lv6Ab/PnNaKbTNcDwbQrXUyaPdb5w43JpuaohdJKo6Dr3cUs4RLiUlYWl7f/FRXxeZ+zVK9f3UBhSElX3qPzQxk87s5qJm3eqWlNxNsSPqBsV4CaylAgllulS8l5AUMmOU9pghhYIFs1qltBFXOPrYt7hjTfsLrXxcEpOoqyjSL3LXpoF2s18an6JZwgWfAmWTzl5rs8Et8Eyc5aZpIBh7p3QP4bP01104bF7kcLoLbuhlRE7+dc7bn6RNWSzzsKrLk0KWpFEu6GYl5gp8/PoE8bmEqVb+Zu8yJpgfmcITQ4dQR341e3VbgcYsCwY8d90eF+9S5iKmeGO0Ork/zGvXtkIbezuUKeUS2ZOb3Yu9HZzTY/9kC0iiU4Lh6WHoOeyXeQlEAKzpJHc/VoDyYJ7Yz0/7oTFwIYb9Z93xwNrnCDygqroo+bODecxFNHiyUbHJdjHJn1YdGOS9XIqUzoC+NQ+XjgvAnemrR/o9+R0Q== X-OriginatorOrg: napatech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 19:35:20.2876 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1720004d-af2a-48ae-997d-08dce7072e33 X-MS-Exchange-CrossTenant-Id: c4540d0b-728a-4233-9da5-9ea30c7ec3ed X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=c4540d0b-728a-4233-9da5-9ea30c7ec3ed; Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509EC.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P190MB0625 X-BESS-ID: 1728329722-311201-2748-3516-1 X-BESS-VER: 2019.1_20241004.2057 X-BESS-Apparent-Source-IP: 104.47.51.233 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVkYmFmZGQGYGUNTS0jTRMCXZzC Qp2TTN2NDEzMjMyNQwzTgtKSnNwNzAUKk2FgAGmOD6QgAAAA== X-BESS-Outbound-Spam-Score: 1.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.259566 [from cloudscan14-168.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.50 BSF_RULE_7582B META: Custom Rule 7582B 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=1.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_RULE_7582B, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Oleksandr Kolomeiets The TX Copy module writes data to packet fields based on the lookup performed by the FLM module. This is used for NAT and can support other actions based on the RTE action MODIFY_FIELD. Signed-off-by: Oleksandr Kolomeiets --- drivers/net/ntnic/meson.build | 1 + .../nthw/flow_api/flow_backend/flow_backend.c | 13 + .../ntnic/nthw/flow_filter/flow_nthw_tx_cpy.c | 339 ++++++++++++++++++ .../ntnic/nthw/flow_filter/flow_nthw_tx_cpy.h | 49 +++ .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 + .../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 2 + .../nthw/supported/nthw_fpga_reg_defs_cpy.h | 113 ++++++ .../supported/nthw_fpga_reg_defs_tx_cpy.h | 23 ++ 8 files changed, 541 insertions(+) create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_cpy.c create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_cpy.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 2dfb0d0627..3c00203e34 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -57,6 +57,7 @@ sources = files( 'nthw/flow_filter/flow_nthw_qsl.c', 'nthw/flow_filter/flow_nthw_rpp_lr.c', 'nthw/flow_filter/flow_nthw_slc_lr.c', + 'nthw/flow_filter/flow_nthw_tx_cpy.c', 'nthw/model/nthw_fpga_model.c', 'nthw/nthw_platform.c', 'nthw/nthw_rac.c', diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c index e2abbf0368..af1e8ce3a4 100644 --- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c +++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c @@ -16,6 +16,7 @@ #include "flow_nthw_slc_lr.h" #include "flow_nthw_pdb.h" #include "flow_nthw_rpp_lr.h" +#include "flow_nthw_tx_cpy.h" #include "ntnic_mod_reg.h" #include "nthw_fpga_model.h" #include "hw_mod_backend.h" @@ -40,6 +41,7 @@ static struct backend_dev_s { struct pdb_nthw *p_pdb_nthw; struct hfu_nthw *p_hfu_nthw; /* TPE module */ struct rpp_lr_nthw *p_rpp_lr_nthw; /* TPE module */ + struct tx_cpy_nthw *p_tx_cpy_nthw; /* TPE module */ struct ifr_nthw *p_ifr_nthw; /* TPE module */ } be_devs[MAX_PHYS_ADAPTERS]; @@ -1807,6 +1809,16 @@ const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, vo be_devs[physical_adapter_no].p_rpp_lr_nthw = NULL; } + /* Init nthw TX_CPY */ + if (tx_cpy_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) { + struct tx_cpy_nthw *ptr = tx_cpy_nthw_new(); + tx_cpy_nthw_init(ptr, p_fpga, physical_adapter_no); + be_devs[physical_adapter_no].p_tx_cpy_nthw = ptr; + + } else { + be_devs[physical_adapter_no].p_tx_cpy_nthw = NULL; + } + be_devs[physical_adapter_no].adapter_no = physical_adapter_no; *dev = (void *)&be_devs[physical_adapter_no]; @@ -1826,6 +1838,7 @@ static void bin_flow_backend_done(void *dev) pdb_nthw_delete(be_dev->p_pdb_nthw); hfu_nthw_delete(be_dev->p_hfu_nthw); rpp_lr_nthw_delete(be_dev->p_rpp_lr_nthw); + tx_cpy_nthw_delete(be_dev->p_tx_cpy_nthw); } static const struct flow_backend_ops ops = { diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_cpy.c b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_cpy.c new file mode 100644 index 0000000000..197baae334 --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_cpy.c @@ -0,0 +1,339 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include + +#include "ntlog.h" +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "flow_nthw_tx_cpy.h" + +struct tx_cpy_nthw *tx_cpy_nthw_new(void) +{ + struct tx_cpy_nthw *p = malloc(sizeof(struct tx_cpy_nthw)); + + if (p) + (void)memset(p, 0, sizeof(*p)); + + return p; +} + +void tx_cpy_nthw_delete(struct tx_cpy_nthw *p) +{ + if (p) { + free(p->m_writers); + (void)memset(p, 0, sizeof(*p)); + free(p); + } +} + +int tx_cpy_nthw_init(struct tx_cpy_nthw *p, nthw_fpga_t *p_fpga, int n_instance) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_TX_CPY, n_instance); + + assert(n_instance >= 0 && n_instance < 256); + + if (p == NULL) + return p_mod == NULL ? -1 : 0; + + if (p_mod == NULL) { + NT_LOG(ERR, NTHW, "%s: TxCpy %d: no such instance\n", p_adapter_id_str, + n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->m_physical_adapter_no = (uint8_t)n_instance; + p->m_tx_cpy = nthw_fpga_query_module(p_fpga, MOD_TX_CPY, n_instance); + + const int writers_cnt = nthw_fpga_get_product_param(p->mp_fpga, NT_TX_CPY_WRITERS, 0); + + if (writers_cnt < 1) + return -1; + + p->m_writers_cnt = (unsigned int)writers_cnt; + p->m_writers = calloc(p->m_writers_cnt, sizeof(struct tx_cpy_writers_s)); + + if (p->m_writers == NULL) + return -1; + + const int variant = nthw_fpga_get_product_param(p->mp_fpga, NT_TX_CPY_VARIANT, 0); + + switch (p->m_writers_cnt) { + default: + case 6: + p->m_writers[5].mp_writer_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER5_CTRL); + p->m_writers[5].mp_writer_ctrl_addr = + nthw_register_get_field(p->m_writers[5].mp_writer_ctrl, + CPY_WRITER5_CTRL_ADR); + p->m_writers[5].mp_writer_ctrl_cnt = + nthw_register_get_field(p->m_writers[5].mp_writer_ctrl, + CPY_WRITER5_CTRL_CNT); + p->m_writers[5].mp_writer_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER5_DATA); + p->m_writers[5].mp_writer_data_reader_select = + nthw_register_get_field(p->m_writers[5].mp_writer_data, + CPY_WRITER5_DATA_READER_SELECT); + p->m_writers[5].mp_writer_data_dyn = + nthw_register_get_field(p->m_writers[5].mp_writer_data, + CPY_WRITER5_DATA_DYN); + p->m_writers[5].mp_writer_data_ofs = + nthw_register_get_field(p->m_writers[5].mp_writer_data, + CPY_WRITER5_DATA_OFS); + p->m_writers[5].mp_writer_data_len = + nthw_register_get_field(p->m_writers[5].mp_writer_data, + CPY_WRITER5_DATA_LEN); + + if (variant != 0) { + p->m_writers[5].mp_writer_data_mask_pointer = + nthw_register_get_field(p->m_writers[5].mp_writer_data, + CPY_WRITER5_DATA_MASK_POINTER); + p->m_writers[5].mp_writer_mask_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER5_MASK_CTRL); + p->m_writers[5].mp_writer_mask_ctrl_addr = + nthw_register_get_field(p->m_writers[5].mp_writer_mask_ctrl, + CPY_WRITER5_MASK_CTRL_ADR); + p->m_writers[5].mp_writer_mask_ctrl_cnt = + nthw_register_get_field(p->m_writers[5].mp_writer_mask_ctrl, + CPY_WRITER5_MASK_CTRL_CNT); + p->m_writers[5].mp_writer_mask_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER5_MASK_DATA); + p->m_writers[5].mp_writer_mask_data_byte_mask = + nthw_register_get_field(p->m_writers[5].mp_writer_mask_data, + CPY_WRITER5_MASK_DATA_BYTE_MASK); + } + + /* Fallthrough */ + case 5: + p->m_writers[4].mp_writer_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER4_CTRL); + p->m_writers[4].mp_writer_ctrl_addr = + nthw_register_get_field(p->m_writers[4].mp_writer_ctrl, + CPY_WRITER4_CTRL_ADR); + p->m_writers[4].mp_writer_ctrl_cnt = + nthw_register_get_field(p->m_writers[4].mp_writer_ctrl, + CPY_WRITER4_CTRL_CNT); + p->m_writers[4].mp_writer_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER4_DATA); + p->m_writers[4].mp_writer_data_reader_select = + nthw_register_get_field(p->m_writers[4].mp_writer_data, + CPY_WRITER4_DATA_READER_SELECT); + p->m_writers[4].mp_writer_data_dyn = + nthw_register_get_field(p->m_writers[4].mp_writer_data, + CPY_WRITER4_DATA_DYN); + p->m_writers[4].mp_writer_data_ofs = + nthw_register_get_field(p->m_writers[4].mp_writer_data, + CPY_WRITER4_DATA_OFS); + p->m_writers[4].mp_writer_data_len = + nthw_register_get_field(p->m_writers[4].mp_writer_data, + CPY_WRITER4_DATA_LEN); + + if (variant != 0) { + p->m_writers[4].mp_writer_data_mask_pointer = + nthw_register_get_field(p->m_writers[4].mp_writer_data, + CPY_WRITER4_DATA_MASK_POINTER); + p->m_writers[4].mp_writer_mask_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER4_MASK_CTRL); + p->m_writers[4].mp_writer_mask_ctrl_addr = + nthw_register_get_field(p->m_writers[4].mp_writer_mask_ctrl, + CPY_WRITER4_MASK_CTRL_ADR); + p->m_writers[4].mp_writer_mask_ctrl_cnt = + nthw_register_get_field(p->m_writers[4].mp_writer_mask_ctrl, + CPY_WRITER4_MASK_CTRL_CNT); + p->m_writers[4].mp_writer_mask_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER4_MASK_DATA); + p->m_writers[4].mp_writer_mask_data_byte_mask = + nthw_register_get_field(p->m_writers[4].mp_writer_mask_data, + CPY_WRITER4_MASK_DATA_BYTE_MASK); + } + + /* Fallthrough */ + case 4: + p->m_writers[3].mp_writer_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER3_CTRL); + p->m_writers[3].mp_writer_ctrl_addr = + nthw_register_get_field(p->m_writers[3].mp_writer_ctrl, + CPY_WRITER3_CTRL_ADR); + p->m_writers[3].mp_writer_ctrl_cnt = + nthw_register_get_field(p->m_writers[3].mp_writer_ctrl, + CPY_WRITER3_CTRL_CNT); + p->m_writers[3].mp_writer_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER3_DATA); + p->m_writers[3].mp_writer_data_reader_select = + nthw_register_get_field(p->m_writers[3].mp_writer_data, + CPY_WRITER3_DATA_READER_SELECT); + p->m_writers[3].mp_writer_data_dyn = + nthw_register_get_field(p->m_writers[3].mp_writer_data, + CPY_WRITER3_DATA_DYN); + p->m_writers[3].mp_writer_data_ofs = + nthw_register_get_field(p->m_writers[3].mp_writer_data, + CPY_WRITER3_DATA_OFS); + p->m_writers[3].mp_writer_data_len = + nthw_register_get_field(p->m_writers[3].mp_writer_data, + CPY_WRITER3_DATA_LEN); + + if (variant != 0) { + p->m_writers[3].mp_writer_data_mask_pointer = + nthw_register_get_field(p->m_writers[3].mp_writer_data, + CPY_WRITER3_DATA_MASK_POINTER); + p->m_writers[3].mp_writer_mask_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER3_MASK_CTRL); + p->m_writers[3].mp_writer_mask_ctrl_addr = + nthw_register_get_field(p->m_writers[3].mp_writer_mask_ctrl, + CPY_WRITER3_MASK_CTRL_ADR); + p->m_writers[3].mp_writer_mask_ctrl_cnt = + nthw_register_get_field(p->m_writers[3].mp_writer_mask_ctrl, + CPY_WRITER3_MASK_CTRL_CNT); + p->m_writers[3].mp_writer_mask_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER3_MASK_DATA); + p->m_writers[3].mp_writer_mask_data_byte_mask = + nthw_register_get_field(p->m_writers[3].mp_writer_mask_data, + CPY_WRITER3_MASK_DATA_BYTE_MASK); + } + + /* Fallthrough */ + case 3: + p->m_writers[2].mp_writer_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER2_CTRL); + p->m_writers[2].mp_writer_ctrl_addr = + nthw_register_get_field(p->m_writers[2].mp_writer_ctrl, + CPY_WRITER2_CTRL_ADR); + p->m_writers[2].mp_writer_ctrl_cnt = + nthw_register_get_field(p->m_writers[2].mp_writer_ctrl, + CPY_WRITER2_CTRL_CNT); + p->m_writers[2].mp_writer_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER2_DATA); + p->m_writers[2].mp_writer_data_reader_select = + nthw_register_get_field(p->m_writers[2].mp_writer_data, + CPY_WRITER2_DATA_READER_SELECT); + p->m_writers[2].mp_writer_data_dyn = + nthw_register_get_field(p->m_writers[2].mp_writer_data, + CPY_WRITER2_DATA_DYN); + p->m_writers[2].mp_writer_data_ofs = + nthw_register_get_field(p->m_writers[2].mp_writer_data, + CPY_WRITER2_DATA_OFS); + p->m_writers[2].mp_writer_data_len = + nthw_register_get_field(p->m_writers[2].mp_writer_data, + CPY_WRITER2_DATA_LEN); + + if (variant != 0) { + p->m_writers[2].mp_writer_data_mask_pointer = + nthw_register_get_field(p->m_writers[2].mp_writer_data, + CPY_WRITER2_DATA_MASK_POINTER); + p->m_writers[2].mp_writer_mask_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER2_MASK_CTRL); + p->m_writers[2].mp_writer_mask_ctrl_addr = + nthw_register_get_field(p->m_writers[2].mp_writer_mask_ctrl, + CPY_WRITER2_MASK_CTRL_ADR); + p->m_writers[2].mp_writer_mask_ctrl_cnt = + nthw_register_get_field(p->m_writers[2].mp_writer_mask_ctrl, + CPY_WRITER2_MASK_CTRL_CNT); + p->m_writers[2].mp_writer_mask_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER2_MASK_DATA); + p->m_writers[2].mp_writer_mask_data_byte_mask = + nthw_register_get_field(p->m_writers[2].mp_writer_mask_data, + CPY_WRITER2_MASK_DATA_BYTE_MASK); + } + + /* Fallthrough */ + case 2: + p->m_writers[1].mp_writer_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER1_CTRL); + p->m_writers[1].mp_writer_ctrl_addr = + nthw_register_get_field(p->m_writers[1].mp_writer_ctrl, + CPY_WRITER1_CTRL_ADR); + p->m_writers[1].mp_writer_ctrl_cnt = + nthw_register_get_field(p->m_writers[1].mp_writer_ctrl, + CPY_WRITER1_CTRL_CNT); + p->m_writers[1].mp_writer_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER1_DATA); + p->m_writers[1].mp_writer_data_reader_select = + nthw_register_get_field(p->m_writers[1].mp_writer_data, + CPY_WRITER1_DATA_READER_SELECT); + p->m_writers[1].mp_writer_data_dyn = + nthw_register_get_field(p->m_writers[1].mp_writer_data, + CPY_WRITER1_DATA_DYN); + p->m_writers[1].mp_writer_data_ofs = + nthw_register_get_field(p->m_writers[1].mp_writer_data, + CPY_WRITER1_DATA_OFS); + p->m_writers[1].mp_writer_data_len = + nthw_register_get_field(p->m_writers[1].mp_writer_data, + CPY_WRITER1_DATA_LEN); + + if (variant != 0) { + p->m_writers[1].mp_writer_data_mask_pointer = + nthw_register_get_field(p->m_writers[1].mp_writer_data, + CPY_WRITER1_DATA_MASK_POINTER); + p->m_writers[1].mp_writer_mask_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER1_MASK_CTRL); + p->m_writers[1].mp_writer_mask_ctrl_addr = + nthw_register_get_field(p->m_writers[1].mp_writer_mask_ctrl, + CPY_WRITER1_MASK_CTRL_ADR); + p->m_writers[1].mp_writer_mask_ctrl_cnt = + nthw_register_get_field(p->m_writers[1].mp_writer_mask_ctrl, + CPY_WRITER1_MASK_CTRL_CNT); + p->m_writers[1].mp_writer_mask_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER1_MASK_DATA); + p->m_writers[1].mp_writer_mask_data_byte_mask = + nthw_register_get_field(p->m_writers[1].mp_writer_mask_data, + CPY_WRITER1_MASK_DATA_BYTE_MASK); + } + + /* Fallthrough */ + case 1: + p->m_writers[0].mp_writer_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER0_CTRL); + p->m_writers[0].mp_writer_ctrl_addr = + nthw_register_get_field(p->m_writers[0].mp_writer_ctrl, + CPY_WRITER0_CTRL_ADR); + p->m_writers[0].mp_writer_ctrl_cnt = + nthw_register_get_field(p->m_writers[0].mp_writer_ctrl, + CPY_WRITER0_CTRL_CNT); + p->m_writers[0].mp_writer_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER0_DATA); + p->m_writers[0].mp_writer_data_reader_select = + nthw_register_get_field(p->m_writers[0].mp_writer_data, + CPY_WRITER0_DATA_READER_SELECT); + p->m_writers[0].mp_writer_data_dyn = + nthw_register_get_field(p->m_writers[0].mp_writer_data, + CPY_WRITER0_DATA_DYN); + p->m_writers[0].mp_writer_data_ofs = + nthw_register_get_field(p->m_writers[0].mp_writer_data, + CPY_WRITER0_DATA_OFS); + p->m_writers[0].mp_writer_data_len = + nthw_register_get_field(p->m_writers[0].mp_writer_data, + CPY_WRITER0_DATA_LEN); + + if (variant != 0) { + p->m_writers[0].mp_writer_data_mask_pointer = + nthw_register_get_field(p->m_writers[0].mp_writer_data, + CPY_WRITER0_DATA_MASK_POINTER); + p->m_writers[0].mp_writer_mask_ctrl = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER0_MASK_CTRL); + p->m_writers[0].mp_writer_mask_ctrl_addr = + nthw_register_get_field(p->m_writers[0].mp_writer_mask_ctrl, + CPY_WRITER0_MASK_CTRL_ADR); + p->m_writers[0].mp_writer_mask_ctrl_cnt = + nthw_register_get_field(p->m_writers[0].mp_writer_mask_ctrl, + CPY_WRITER0_MASK_CTRL_CNT); + p->m_writers[0].mp_writer_mask_data = + nthw_module_get_register(p->m_tx_cpy, CPY_WRITER0_MASK_DATA); + p->m_writers[0].mp_writer_mask_data_byte_mask = + nthw_register_get_field(p->m_writers[0].mp_writer_mask_data, + CPY_WRITER0_MASK_DATA_BYTE_MASK); + } + + break; + + case 0: + return -1; + } + + return 0; +} diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_cpy.h b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_cpy.h new file mode 100644 index 0000000000..801b47b0bb --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_cpy.h @@ -0,0 +1,49 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __FLOW_NTHW_TX_CPY_H__ +#define __FLOW_NTHW_TX_CPY_H__ + +#include + +#include "nthw_fpga_model.h" + +struct tx_cpy_writers_s { + nthw_register_t *mp_writer_ctrl; + nthw_field_t *mp_writer_ctrl_addr; + nthw_field_t *mp_writer_ctrl_cnt; + + nthw_register_t *mp_writer_data; + nthw_field_t *mp_writer_data_reader_select; + nthw_field_t *mp_writer_data_dyn; + nthw_field_t *mp_writer_data_ofs; + nthw_field_t *mp_writer_data_len; + nthw_field_t *mp_writer_data_mask_pointer; + + nthw_register_t *mp_writer_mask_ctrl; + nthw_field_t *mp_writer_mask_ctrl_addr; + nthw_field_t *mp_writer_mask_ctrl_cnt; + + nthw_register_t *mp_writer_mask_data; + nthw_field_t *mp_writer_mask_data_byte_mask; +}; + +struct tx_cpy_nthw { + uint8_t m_physical_adapter_no; + nthw_fpga_t *mp_fpga; + + nthw_module_t *m_tx_cpy; + + unsigned int m_writers_cnt; + struct tx_cpy_writers_s *m_writers; +}; + +struct tx_cpy_nthw *tx_cpy_nthw_new(void); +void tx_cpy_nthw_delete(struct tx_cpy_nthw *p); +int tx_cpy_nthw_init(struct tx_cpy_nthw *p, nthw_fpga_t *p_fpga, int n_instance); + +int tx_cpy_nthw_setup(struct tx_cpy_nthw *p, int n_idx, int n_idx_cnt); + +#endif /* __FLOW_NTHW_TX_CPY_H__ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h index f1d055a36e..d93d9d3816 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h @@ -37,6 +37,7 @@ #define MOD_RST9563 (0x385d6d1dUL) #define MOD_SDC (0xd2369530UL) #define MOD_SLC_LR (0x969fc50bUL) +#define MOD_TX_CPY (0x60acf217UL) #define MOD_IDX_COUNT (14) /* aliases - only aliases go below this point */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h index c39901ce39..d58d10c438 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h @@ -14,6 +14,7 @@ #define _NTHW_FPGA_REG_DEFS_ #include "nthw_fpga_reg_defs_cat.h" +#include "nthw_fpga_reg_defs_cpy.h" #include "nthw_fpga_reg_defs_flm.h" #include "nthw_fpga_reg_defs_gfg.h" #include "nthw_fpga_reg_defs_gmf.h" @@ -37,6 +38,7 @@ #include "nthw_fpga_reg_defs_sdc.h" #include "nthw_fpga_reg_defs_slc.h" #include "nthw_fpga_reg_defs_slc_lr.h" +#include "nthw_fpga_reg_defs_tx_cpy.h" /* aliases */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h new file mode 100644 index 0000000000..55fd5704b9 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h @@ -0,0 +1,113 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Napatech A/S + */ + +/* + * nthw_fpga_reg_defs_cpy.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_CPY_ +#define _NTHW_FPGA_REG_DEFS_CPY_ + +/* CPY */ +#define NTHW_MOD_CPY (0x1ddc186fUL) +#define CPY_PACKET_READER0_CTRL (0x59359b7UL) +#define CPY_PACKET_READER0_CTRL_ADR (0xc84f1475UL) +#define CPY_PACKET_READER0_CTRL_CNT (0xd8478da4UL) +#define CPY_PACKET_READER0_DATA (0xaa42dbaeUL) +#define CPY_PACKET_READER0_DATA_DYN (0x34037b11UL) +#define CPY_PACKET_READER0_DATA_OFS (0x960af6b7UL) +#define CPY_WRITER0_CTRL (0xe9b3268eUL) +#define CPY_WRITER0_CTRL_ADR (0x26f906c2UL) +#define CPY_WRITER0_CTRL_CNT (0x36f19f13UL) +#define CPY_WRITER0_DATA (0x4662a497UL) +#define CPY_WRITER0_DATA_DYN (0xdab569a6UL) +#define CPY_WRITER0_DATA_LEN (0x32d16543UL) +#define CPY_WRITER0_DATA_MASK_POINTER (0x64db2b2dUL) +#define CPY_WRITER0_DATA_OFS (0x78bce400UL) +#define CPY_WRITER0_DATA_READER_SELECT (0x63a38cf9UL) +#define CPY_WRITER0_MASK_CTRL (0xed52c5f9UL) +#define CPY_WRITER0_MASK_CTRL_ADR (0x3bbdf6aaUL) +#define CPY_WRITER0_MASK_CTRL_CNT (0x2bb56f7bUL) +#define CPY_WRITER0_MASK_DATA (0x428347e0UL) +#define CPY_WRITER0_MASK_DATA_BYTE_MASK (0xd1d0e256UL) +#define CPY_WRITER1_CTRL (0x22eff52bUL) +#define CPY_WRITER1_CTRL_ADR (0xc93b6dfcUL) +#define CPY_WRITER1_CTRL_CNT (0xd933f42dUL) +#define CPY_WRITER1_DATA (0x8d3e7732UL) +#define CPY_WRITER1_DATA_DYN (0x35770298UL) +#define CPY_WRITER1_DATA_LEN (0xdd130e7dUL) +#define CPY_WRITER1_DATA_MASK_POINTER (0xb339ab75UL) +#define CPY_WRITER1_DATA_OFS (0x977e8f3eUL) +#define CPY_WRITER1_DATA_READER_SELECT (0x6c4b7bfUL) +#define CPY_WRITER1_MASK_CTRL (0x2cdc1a39UL) +#define CPY_WRITER1_MASK_CTRL_ADR (0x82462d42UL) +#define CPY_WRITER1_MASK_CTRL_CNT (0x924eb493UL) +#define CPY_WRITER1_MASK_DATA (0x830d9820UL) +#define CPY_WRITER1_MASK_DATA_BYTE_MASK (0x4e0a61c8UL) +#define CPY_WRITER2_CTRL (0xa47b8785UL) +#define CPY_WRITER2_CTRL_ADR (0x220cd6ffUL) +#define CPY_WRITER2_CTRL_CNT (0x32044f2eUL) +#define CPY_WRITER2_DATA (0xbaa059cUL) +#define CPY_WRITER2_DATA_DYN (0xde40b99bUL) +#define CPY_WRITER2_DATA_LEN (0x3624b57eUL) +#define CPY_WRITER2_DATA_MASK_POINTER (0x106f2ddcUL) +#define CPY_WRITER2_DATA_OFS (0x7c49343dUL) +#define CPY_WRITER2_DATA_READER_SELECT (0xa96dfa75UL) +#define CPY_WRITER2_MASK_CTRL (0xb53e7c38UL) +#define CPY_WRITER2_MASK_CTRL_ADR (0x933b473bUL) +#define CPY_WRITER2_MASK_CTRL_CNT (0x8333deeaUL) +#define CPY_WRITER2_MASK_DATA (0x1aeffe21UL) +#define CPY_WRITER2_MASK_DATA_BYTE_MASK (0x3514e32bUL) +#define CPY_WRITER3_CTRL (0x6f275420UL) +#define CPY_WRITER3_CTRL_ADR (0xcdcebdc1UL) +#define CPY_WRITER3_CTRL_CNT (0xddc62410UL) +#define CPY_WRITER3_DATA (0xc0f6d639UL) +#define CPY_WRITER3_DATA_DYN (0x3182d2a5UL) +#define CPY_WRITER3_DATA_LEN (0xd9e6de40UL) +#define CPY_WRITER3_DATA_MASK_POINTER (0xc78dad84UL) +#define CPY_WRITER3_DATA_OFS (0x938b5f03UL) +#define CPY_WRITER3_DATA_READER_SELECT (0xcc0ac133UL) +#define CPY_WRITER3_MASK_CTRL (0x74b0a3f8UL) +#define CPY_WRITER3_MASK_CTRL_ADR (0x2ac09cd3UL) +#define CPY_WRITER3_MASK_CTRL_CNT (0x3ac80502UL) +#define CPY_WRITER3_MASK_DATA (0xdb6121e1UL) +#define CPY_WRITER3_MASK_DATA_BYTE_MASK (0xaace60b5UL) +#define CPY_WRITER4_CTRL (0x72226498UL) +#define CPY_WRITER4_CTRL_ADR (0x2f12a6b8UL) +#define CPY_WRITER4_CTRL_CNT (0x3f1a3f69UL) +#define CPY_WRITER4_DATA (0xddf3e681UL) +#define CPY_WRITER4_DATA_DYN (0xd35ec9dcUL) +#define CPY_WRITER4_DATA_LEN (0x3b3ac539UL) +#define CPY_WRITER4_DATA_MASK_POINTER (0x8db326cfUL) +#define CPY_WRITER4_DATA_OFS (0x7157447aUL) +#define CPY_WRITER4_DATA_READER_SELECT (0x2d4e67a0UL) +#define CPY_WRITER4_MASK_CTRL (0x5d8bb67bUL) +#define CPY_WRITER4_MASK_CTRL_ADR (0xb1c193c9UL) +#define CPY_WRITER4_MASK_CTRL_CNT (0xa1c90a18UL) +#define CPY_WRITER4_MASK_DATA (0xf25a3462UL) +#define CPY_WRITER4_MASK_DATA_BYTE_MASK (0xc329e6edUL) +#define CPY_WRITER5_CTRL (0xb97eb73dUL) +#define CPY_WRITER5_CTRL_ADR (0xc0d0cd86UL) +#define CPY_WRITER5_CTRL_CNT (0xd0d85457UL) +#define CPY_WRITER5_DATA (0x16af3524UL) +#define CPY_WRITER5_DATA_DYN (0x3c9ca2e2UL) +#define CPY_WRITER5_DATA_LEN (0xd4f8ae07UL) +#define CPY_WRITER5_DATA_MASK_POINTER (0x5a51a697UL) +#define CPY_WRITER5_DATA_OFS (0x9e952f44UL) +#define CPY_WRITER5_DATA_READER_SELECT (0x48295ce6UL) +#define CPY_WRITER5_MASK_CTRL (0x9c0569bbUL) +#define CPY_WRITER5_MASK_CTRL_ADR (0x83a4821UL) +#define CPY_WRITER5_MASK_CTRL_CNT (0x1832d1f0UL) +#define CPY_WRITER5_MASK_DATA (0x33d4eba2UL) +#define CPY_WRITER5_MASK_DATA_BYTE_MASK (0x5cf36573UL) + +#endif /* _NTHW_FPGA_REG_DEFS_CPY_ */ + +/* + * Auto-generated file - do *NOT* edit + */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h new file mode 100644 index 0000000000..1fb71bf483 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h @@ -0,0 +1,23 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Napatech A/S + */ + +/* + * nthw_fpga_reg_defs_tx_cpy.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_TX_CPY_ +#define _NTHW_FPGA_REG_DEFS_TX_CPY_ + +/* TX_CPY */ +#define NTHW_MOD_TX_CPY (0x60acf217UL) + +#endif /* _NTHW_FPGA_REG_DEFS_TX_CPY_ */ + +/* + * Auto-generated file - do *NOT* edit + */