diff mbox series

[v2,19/50] net/ntnic: add header field update (HFU) flow module

Message ID 20241007193436.675785-20-sil-plv@napatech.com (mailing list archive)
State Superseded, archived
Delegated to: Ferruh Yigit
Headers
Series Provide: flow filter init API, Enable virtual queues, fix ntnic issues for release 24.07 |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Serhii Iliushyk Oct. 7, 2024, 7:33 p.m. UTC 
From: Oleksandr Kolomeiets <okl-plv@napatech.com>

The Header Field Update module updates protocol fields
if the packets have been changed,
for example length fields and next protocol fields.

Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
 drivers/net/ntnic/meson.build                 |  1 +
 .../nthw/flow_api/flow_backend/flow_backend.c | 13 +++
 .../ntnic/nthw/flow_filter/flow_nthw_hfu.c    | 99 +++++++++++++++++++
 .../ntnic/nthw/flow_filter/flow_nthw_hfu.h    | 54 ++++++++++
 .../ntnic/nthw/supported/nthw_fpga_mod_defs.h |  1 +
 .../ntnic/nthw/supported/nthw_fpga_reg_defs.h |  1 +
 .../nthw/supported/nthw_fpga_reg_defs_hfu.h   | 49 +++++++++
 7 files changed, 218 insertions(+)
 create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_hfu.c
 create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_hfu.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h
diff mbox series

Patch

diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 35f7feb7be..552cbc30bf 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -48,6 +48,7 @@  sources = files(
         'nthw/flow_api/flow_filter.c',
         'nthw/flow_filter/flow_nthw_cat.c',
         'nthw/flow_filter/flow_nthw_flm.c',
+        'nthw/flow_filter/flow_nthw_hfu.c',
         'nthw/flow_filter/flow_nthw_hsh.c',
         'nthw/flow_filter/flow_nthw_ifr.c',
         'nthw/flow_filter/flow_nthw_info.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
index e3c4c5b7cb..feb3355de3 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
@@ -10,6 +10,7 @@ 
 #include "flow_nthw_cat.h"
 #include "flow_nthw_km.h"
 #include "flow_nthw_flm.h"
+#include "flow_nthw_hfu.h"
 #include "flow_nthw_hsh.h"
 #include "flow_nthw_qsl.h"
 #include "flow_nthw_slc_lr.h"
@@ -36,6 +37,7 @@  static struct backend_dev_s {
 	struct qsl_nthw *p_qsl_nthw;
 	struct slc_lr_nthw *p_slc_lr_nthw;
 	struct pdb_nthw *p_pdb_nthw;
+	struct hfu_nthw *p_hfu_nthw;    /* TPE module */
 	struct ifr_nthw *p_ifr_nthw;    /* TPE module */
 } be_devs[MAX_PHYS_ADAPTERS];
 
@@ -1783,6 +1785,16 @@  const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, vo
 		be_devs[physical_adapter_no].p_pdb_nthw = NULL;
 	}
 
+	/* Init nthw HFU */
+	if (hfu_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) {
+		struct hfu_nthw *ptr = hfu_nthw_new();
+		hfu_nthw_init(ptr, p_fpga, physical_adapter_no);
+		be_devs[physical_adapter_no].p_hfu_nthw = ptr;
+
+	} else {
+		be_devs[physical_adapter_no].p_hfu_nthw = NULL;
+	}
+
 	be_devs[physical_adapter_no].adapter_no = physical_adapter_no;
 	*dev = (void *)&be_devs[physical_adapter_no];
 
@@ -1800,6 +1812,7 @@  static void bin_flow_backend_done(void *dev)
 	qsl_nthw_delete(be_dev->p_qsl_nthw);
 	slc_lr_nthw_delete(be_dev->p_slc_lr_nthw);
 	pdb_nthw_delete(be_dev->p_pdb_nthw);
+	hfu_nthw_delete(be_dev->p_hfu_nthw);
 }
 
 static const struct flow_backend_ops ops = {
diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hfu.c b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hfu.c
new file mode 100644
index 0000000000..36d181df02
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hfu.c
@@ -0,0 +1,99 @@ 
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+#include "ntlog.h"
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "flow_nthw_hfu.h"
+
+struct hfu_nthw *hfu_nthw_new(void)
+{
+	struct hfu_nthw *p = malloc(sizeof(struct hfu_nthw));
+
+	if (p)
+		(void)memset(p, 0, sizeof(*p));
+
+	return p;
+}
+
+void hfu_nthw_delete(struct hfu_nthw *p)
+{
+	if (p) {
+		(void)memset(p, 0, sizeof(*p));
+		free(p);
+	}
+}
+
+int hfu_nthw_init(struct hfu_nthw *p, nthw_fpga_t *p_fpga, int n_instance)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_HFU, n_instance);
+
+	assert(n_instance >= 0 && n_instance < 256);
+
+	if (p == NULL)
+		return p_mod == NULL ? -1 : 0;
+
+	if (p_mod == NULL) {
+		NT_LOG(ERR, NTHW, "%s: Hfu %d: no such instance\n", p_adapter_id_str, n_instance);
+		return -1;
+	}
+
+	p->mp_fpga = p_fpga;
+	p->m_physical_adapter_no = (uint8_t)n_instance;
+	p->m_hfu = nthw_fpga_query_module(p_fpga, MOD_HFU, n_instance);
+
+	p->mp_rcp_ctrl = nthw_module_get_register(p->m_hfu, HFU_RCP_CTRL);
+	p->mp_rcp_addr = nthw_register_get_field(p->mp_rcp_ctrl, HFU_RCP_CTRL_ADR);
+	p->mp_rcp_cnt = nthw_register_get_field(p->mp_rcp_ctrl, HFU_RCP_CTRL_CNT);
+
+	p->mp_rcp_data = nthw_module_get_register(p->m_hfu, HFU_RCP_DATA);
+	p->mp_rcp_data_len_a_wr = nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_A_WR);
+	p->mp_rcp_data_len_a_ol4len =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_A_OL4LEN);
+	p->mp_rcp_data_len_a_pos_dyn =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_A_POS_DYN);
+	p->mp_rcp_data_len_a_pos_ofs =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_A_POS_OFS);
+	p->mp_rcp_data_len_a_add_dyn =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_A_ADD_DYN);
+	p->mp_rcp_data_len_a_add_ofs =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_A_ADD_OFS);
+	p->mp_rcp_data_len_a_sub_dyn =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_A_SUB_DYN);
+	p->mp_rcp_data_len_b_wr = nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_B_WR);
+	p->mp_rcp_data_len_b_pos_dyn =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_B_POS_DYN);
+	p->mp_rcp_data_len_b_pos_ofs =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_B_POS_OFS);
+	p->mp_rcp_data_len_b_add_dyn =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_B_ADD_DYN);
+	p->mp_rcp_data_len_b_add_ofs =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_B_ADD_OFS);
+	p->mp_rcp_data_len_b_sub_dyn =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_B_SUB_DYN);
+	p->mp_rcp_data_len_c_wr = nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_C_WR);
+	p->mp_rcp_data_len_c_pos_dyn =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_C_POS_DYN);
+	p->mp_rcp_data_len_c_pos_ofs =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_C_POS_OFS);
+	p->mp_rcp_data_len_c_add_dyn =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_C_ADD_DYN);
+	p->mp_rcp_data_len_c_add_ofs =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_C_ADD_OFS);
+	p->mp_rcp_data_len_c_sub_dyn =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_LEN_C_SUB_DYN);
+	p->mp_rcp_data_ttl_wr = nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_TTL_WR);
+	p->mp_rcp_data_ttl_pos_dyn =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_TTL_POS_DYN);
+	p->mp_rcp_data_ttl_pos_ofs =
+		nthw_register_get_field(p->mp_rcp_data, HFU_RCP_DATA_TTL_POS_OFS);
+
+	return 0;
+}
diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hfu.h b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hfu.h
new file mode 100644
index 0000000000..7a59066b92
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hfu.h
@@ -0,0 +1,54 @@ 
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __FLOW_NTHW_HFU_H__
+#define __FLOW_NTHW_HFU_H__
+
+#include <stdint.h>
+
+#include "nthw_fpga_model.h"
+
+struct hfu_nthw {
+	uint8_t m_physical_adapter_no;
+	nthw_fpga_t *mp_fpga;
+
+	nthw_module_t *m_hfu;
+
+	nthw_register_t *mp_rcp_ctrl;
+	nthw_field_t *mp_rcp_addr;
+	nthw_field_t *mp_rcp_cnt;
+
+	nthw_register_t *mp_rcp_data;
+	nthw_field_t *mp_rcp_data_len_a_wr;
+	nthw_field_t *mp_rcp_data_len_a_ol4len;
+	nthw_field_t *mp_rcp_data_len_a_pos_dyn;
+	nthw_field_t *mp_rcp_data_len_a_pos_ofs;
+	nthw_field_t *mp_rcp_data_len_a_add_dyn;
+	nthw_field_t *mp_rcp_data_len_a_add_ofs;
+	nthw_field_t *mp_rcp_data_len_a_sub_dyn;
+	nthw_field_t *mp_rcp_data_len_b_wr;
+	nthw_field_t *mp_rcp_data_len_b_pos_dyn;
+	nthw_field_t *mp_rcp_data_len_b_pos_ofs;
+	nthw_field_t *mp_rcp_data_len_b_add_dyn;
+	nthw_field_t *mp_rcp_data_len_b_add_ofs;
+	nthw_field_t *mp_rcp_data_len_b_sub_dyn;
+	nthw_field_t *mp_rcp_data_len_c_wr;
+	nthw_field_t *mp_rcp_data_len_c_pos_dyn;
+	nthw_field_t *mp_rcp_data_len_c_pos_ofs;
+	nthw_field_t *mp_rcp_data_len_c_add_dyn;
+	nthw_field_t *mp_rcp_data_len_c_add_ofs;
+	nthw_field_t *mp_rcp_data_len_c_sub_dyn;
+	nthw_field_t *mp_rcp_data_ttl_wr;
+	nthw_field_t *mp_rcp_data_ttl_pos_dyn;
+	nthw_field_t *mp_rcp_data_ttl_pos_ofs;
+};
+
+struct hfu_nthw *hfu_nthw_new(void);
+void hfu_nthw_delete(struct hfu_nthw *p);
+int hfu_nthw_init(struct hfu_nthw *p, nthw_fpga_t *p_fpga, int n_instance);
+
+int hfu_nthw_setup(struct hfu_nthw *p, int n_idx, int n_idx_cnt);
+
+#endif	/* __FLOW_NTHW_HFU_H__ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
index 65c482f7c8..2d53dfdf98 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
@@ -19,6 +19,7 @@ 
 #define MOD_GFG (0xfc423807UL)
 #define MOD_GMF (0x68b1d15aUL)
 #define MOD_GPIO_PHY (0xbbe81659UL)
+#define MOD_HFU (0x4a70e72UL)
 #define MOD_HIF (0x7815363UL)
 #define MOD_HSH (0x501484bfUL)
 #define MOD_I2CM (0x93bc7780UL)
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
index ccb57fdd47..c49913036e 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
@@ -18,6 +18,7 @@ 
 #include "nthw_fpga_reg_defs_gfg.h"
 #include "nthw_fpga_reg_defs_gmf.h"
 #include "nthw_fpga_reg_defs_gpio_phy.h"
+#include "nthw_fpga_reg_defs_hfu.h"
 #include "nthw_fpga_reg_defs_hif.h"
 #include "nthw_fpga_reg_defs_hsh.h"
 #include "nthw_fpga_reg_defs_i2cm.h"
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h
new file mode 100644
index 0000000000..1334e55ef3
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h
@@ -0,0 +1,49 @@ 
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+/*
+ * nthw_fpga_reg_defs_hfu.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_HFU_
+#define _NTHW_FPGA_REG_DEFS_HFU_
+
+/* HFU */
+#define NTHW_MOD_HFU (0x4a70e72UL)
+#define HFU_RCP_CTRL (0xbfa69368UL)
+#define HFU_RCP_CTRL_ADR (0xa3c53608UL)
+#define HFU_RCP_CTRL_CNT (0xb3cdafd9UL)
+#define HFU_RCP_DATA (0x10771171UL)
+#define HFU_RCP_DATA_LEN_A_ADD_DYN (0xf48e5cadUL)
+#define HFU_RCP_DATA_LEN_A_ADD_OFS (0x5687d10bUL)
+#define HFU_RCP_DATA_LEN_A_OL4LEN (0xb06eaffcUL)
+#define HFU_RCP_DATA_LEN_A_POS_DYN (0x8d207086UL)
+#define HFU_RCP_DATA_LEN_A_POS_OFS (0x2f29fd20UL)
+#define HFU_RCP_DATA_LEN_A_SUB_DYN (0x4305f5d4UL)
+#define HFU_RCP_DATA_LEN_A_WR (0x22d5466UL)
+#define HFU_RCP_DATA_LEN_B_ADD_DYN (0xcd036068UL)
+#define HFU_RCP_DATA_LEN_B_ADD_OFS (0x6f0aedceUL)
+#define HFU_RCP_DATA_LEN_B_POS_DYN (0xb4ad4c43UL)
+#define HFU_RCP_DATA_LEN_B_POS_OFS (0x16a4c1e5UL)
+#define HFU_RCP_DATA_LEN_B_SUB_DYN (0x7a88c911UL)
+#define HFU_RCP_DATA_LEN_B_WR (0x1098fb88UL)
+#define HFU_RCP_DATA_LEN_C_ADD_DYN (0xda78742bUL)
+#define HFU_RCP_DATA_LEN_C_ADD_OFS (0x7871f98dUL)
+#define HFU_RCP_DATA_LEN_C_POS_DYN (0xa3d65800UL)
+#define HFU_RCP_DATA_LEN_C_POS_OFS (0x1dfd5a6UL)
+#define HFU_RCP_DATA_LEN_C_SUB_DYN (0x6df3dd52UL)
+#define HFU_RCP_DATA_LEN_C_WR (0xa8249cedUL)
+#define HFU_RCP_DATA_TTL_POS_DYN (0x92a70913UL)
+#define HFU_RCP_DATA_TTL_POS_OFS (0x30ae84b5UL)
+#define HFU_RCP_DATA_TTL_WR (0x7a1aaf7UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_HFU_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */