From patchwork Mon Oct 7 19:33:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 145329 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7D1645AD8; Mon, 7 Oct 2024 21:37:07 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B699540A87; Mon, 7 Oct 2024 21:35:26 +0200 (CEST) Received: from egress-ip42b.ess.de.barracuda.com (egress-ip42b.ess.de.barracuda.com [18.185.115.246]) by mails.dpdk.org (Postfix) with ESMTP id AB0DB40693 for ; Mon, 7 Oct 2024 21:35:20 +0200 (CEST) Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05lp2104.outbound.protection.outlook.com [104.47.18.104]) by mx-outbound43-193.eu-central-1c.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Mon, 07 Oct 2024 19:35:19 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=KKofmVHAiXBCWy/2IRuAZV8DsG0IRaT6eT+55Bm5JppWE4f5DcFc6fnmjANXXiH0ihnHyXHxx8/WPolEbwX5LX8j1HcTe+OfxTP20MFbgorjKyYBcN137NPSRIs+fYm/d29YLppHFzzBtkA2dU2IBkpQtfdyIfraFPBO6tK7j5U1TEoEMTvjgIpVXZ3gi7qxwDTwLpyMIaJGqxiWBJfEgJwA3N6I9KZyT+AjV8BOKqIV765l35LlxQfcmxARPmhnvAbNzISHDgNcVazMNMzNjSJX/oKZlWUmb9EnOY8f3/JqdFe06fzdoZiQvsshR63nC/4POaKi3RWyUaEFCkjkOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cav6N+foajbxzdVDCH6QQw+SLRiVTV/zPS93/jujSaM=; b=i9tH8qBj8xUyN56dtP/xgqaIpFegp5FX3wldIRKybtnz/q3bHvOqlggJkx8++ggRPPizV56o+Ruk4vCinOi7nEjqa5H3bZMQ4MLU7YMKMbYi1SM6BKLCaGn75UhokLyOlIpRHz0r9ofUt5uPVqsWZrHuTHIiHiTtc/xx7SV3EnlVajPEaSF/uUzdtn2D3tw+C1oce4jpS4Xkj7a8tqyKdZp3Vd7YzcZNLQH69uvTsHHEtW7BDIIjx3CYFOTj4bs6UkHcA9/VDIKPloquXs/KcvO2slDbOuyrA3VNFAMCLgkcpeqBbSiflyG2tl/07sPkxEgqcmuOpTNWMEGUm2NI7w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 178.72.21.4) smtp.rcpttodomain=dpdk.org smtp.mailfrom=napatech.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=napatech.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=napatech.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cav6N+foajbxzdVDCH6QQw+SLRiVTV/zPS93/jujSaM=; b=GMqjGZV3afCa1UE0PV7VNeEIpZhd2SSFcSEa8fEL/dB4h8CC8Hd7S0CW+ZV34+D7Q9B/3Bt5ghMtsz2aXJCW7FoZ+NoVkrF4vQ28jyL+QSkyyDcCnlAnPsOeRgi59c64/yk7pKDtCHwbn5Ntsjd7u3bHUfCxHUuw+g8/0Z+RzZo= Received: from DB9PR05CA0020.eurprd05.prod.outlook.com (2603:10a6:10:1da::25) by AM8P190MB1012.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:1c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.23; Mon, 7 Oct 2024 19:35:17 +0000 Received: from DB1PEPF000509EC.eurprd03.prod.outlook.com (2603:10a6:10:1da:cafe::e0) by DB9PR05CA0020.outlook.office365.com (2603:10a6:10:1da::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7982.34 via Frontend Transport; Mon, 7 Oct 2024 19:35:16 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 178.72.21.4) smtp.mailfrom=napatech.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=napatech.com; Received-SPF: Fail (protection.outlook.com: domain of napatech.com does not designate 178.72.21.4 as permitted sender) receiver=protection.outlook.com; client-ip=178.72.21.4; helo=localhost.localdomain; Received: from localhost.localdomain (178.72.21.4) by DB1PEPF000509EC.mail.protection.outlook.com (10.167.242.70) with Microsoft SMTP Server id 15.20.8048.13 via Frontend Transport; Mon, 7 Oct 2024 19:35:16 +0000 From: Serhii Iliushyk To: dev@dpdk.org Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com, andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com, Oleksandr Kolomeiets Subject: [PATCH v2 17/50] net/ntnic: add slicer (SLC LR) flow module Date: Mon, 7 Oct 2024 21:33:53 +0200 Message-ID: <20241007193436.675785-18-sil-plv@napatech.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241007193436.675785-1-sil-plv@napatech.com> References: <20241006203728.330792-2-sil-plv@napatech.com> <20241007193436.675785-1-sil-plv@napatech.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB1PEPF000509EC:EE_|AM8P190MB1012:EE_ X-MS-Office365-Filtering-Correlation-Id: 50bfa6a8-1281-45c0-b6ea-08dce7072bc7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: VYRj8Pxc84UGBIycsRZvg4QQ48RfG3ma0Y+ptUgD7i/fzh3DI4wmosDdz8kEV7MMdKQzfsK95m6imveqMCMKy+UyavOvMRQ2HqcTFtzIvST/KNKA62UjXvxKElFmnHDDs5T4rEahW/zhyz2M63HS7nOQyB2Y11bi/D3v/CDQUi3wylNsEpOmV7qlT6NRt5PnESH3JnzLRNaeGJlBpa7d5R3vmV6B/U3gRKgM3L4HiEST/mI1kLixtPykLF3wjVjRML6kP9mtEQnmFlPc6m386tr6eMJDC3vJPf5rLZHU4oleTH1M4t8Htqp2aHRhDnDwqsN7mydJrjRrq5I6yF5MJXzQhlUkdXta5ni83EoVbA1Lr3/Mx14HdCG1Y9P2JK89cNImdcIgqPxnXijuuNoXmM4n41+7fmMV20+2l4e1NQ95IMsKmfjSEEIqpbDlz2XlMKLW5ItLa2fdTqICSiGBU6B4i3n1g0A5HMuFn1mSZCkRfek7eZXjR4l7xyVltwq5JGI7WmgqW+kOMtKzz6ixFQiJ4WNJT066VbhrxktEoOYqwQon4lW6RROB3sB8dDrfo9HkEcxquyIo98WWv/Mqw5LgO67/2fQ0HW4MBDl2wJ2ri7kxHw/YcvOosftJditfAvjFnJIamFJ7FO6ng/Pcmm8ceUPhudq7anh6otphIf12UTBuu7TTBlqWhTboK3pfay1e5XLT7oFCTLNMTWMaQMkUroJ3hZFBqKORD3IAAEoMfEIsH1Sj8W0a+SXW3DQhroSZKorM6i8OGcYWvXstsPw8Vl9ulj+WdyGqSayBYXhv9tgdpJEROSIl1oisUCH64/p+G+I0Ufk7zqfH9K3dLUpp30tMubPU3yp9hUKAIQVFWIdvmVJNw2U8VtMMRZzPMogDMmyLlEpdKbPQVVhACsv3y5ZO7uCiqQ/b5ZS8hNd9dMoglh6VsClqA+Se9niHNNHof0qfNkyLoQh1qldm9P4AZ98SxJPUAXYhS3F2kLac4G3UzGuWh6Dc9P2+GSLNWA4bM+nq9qdAtT91jQPgY0sIOZp8+aSVmW+1YFiUPNRc6V9z1VP1yuGql/KcQS3C3lQw1R+njB7+xWldMpzwokMFG6h61W9xFyY6YE6p89OqAl8BVqCSfKqk2/Jn3jFVRIQf6W9PNsMq/reRb1dsGFum0uTh8wIV/CxvnM3DGFd4FSKUfvHQdGDpDURWFSPnX50X+eOVok2BDPoaP1UqM9fzHPCiawGeAlvCRc9gr+dZT3SDRf1CjZBV1dSz2Xn94ZJMusY8wUWvij0pOpi33WaygFPyo7Qe7kSN28dvj4WbHcfQcGav+7md1JBe/2m38k8GWvMdtYD7gQsV9rwEv2Ikgg08fdyC71p+9c0JwSomyr1Ct7Ubyv9LE7FpX9HT X-Forefront-Antispam-Report: CIP:178.72.21.4; CTRY:DK; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:localhost.localdomain; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: GanfxjF5wqmzk9Yzb3Z6zYqG24KOkZTx04XKV76ObjUG/T7Iqw6haA2VCvLbPOJyLIfbj8UJqkvJvRY52Gpa1Tijq/WFKbmTSOvHDAMDWOe7O/KrFGO0L/dfKyfKwMHxdslaowzA2eSLxQ93EshG+/5pPlWefBUWYgkOH/oMfKj524Io3/qzTNdouYDKpbxO6+T3XHuWZ1Yc3IPHWhRFuCEM+GBiE8FCPtY2tCWMwg7LKBd1UXII+JrbHeGq8sZI2908fikNTiAjh2+0j6aCy+HdYecaslwsqdXFYgaHLWEO3ugl7R3dW+BaJrVG08mNAC0NtjuFFs+s8ImDGh0YbZ+OrKIqmv6hUuIxmjeuxlb1l0ThQkI7d3A1HKM8emDzh0vJc2QWlJFmclloOWwZY1nSVh3KIGJtvLRQjPFMjgyYBbKwsjQeXxwhoFxMS9jptvAHiq+kjaSf+mkNafusiQvXBTTy4HhV5QKy/4cujNilUZBV2GFRm57WynjG/cPD3yaGIX1Hsshctp/nu7Qb+OuhnnSdTfVCVUYRDh99f41ZWYl96HPoUf5uz1hD6NpvnICSwiyY4a2csK2L0axy3o/tRXArRv2RX1NWRwqXxU+Dvhs8DkcOHs8B6aWiZKIefqi2PrrnLpJXhx4+iWJ4/w== X-OriginatorOrg: napatech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 19:35:16.2251 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50bfa6a8-1281-45c0-b6ea-08dce7072bc7 X-MS-Exchange-CrossTenant-Id: c4540d0b-728a-4233-9da5-9ea30c7ec3ed X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=c4540d0b-728a-4233-9da5-9ea30c7ec3ed; Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509EC.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8P190MB1012 X-BESS-ID: 1728329719-311201-2747-3512-1 X-BESS-VER: 2019.1_20241004.2057 X-BESS-Apparent-Source-IP: 104.47.18.104 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVoZmxmZmQGYGUDTFzCIt2czcyN wwOS0l1cjAxNIiLdE80SQx0cDQONUwSak2FgB4sfibQgAAAA== X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.259566 [from cloudscan17-231.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Oleksandr Kolomeiets The Slicer for Local Retransmit module can cut of the head a packet before the packet leaves the FPGA RX pipeline. This is used when the TX pipeline is configured to add a new head in the packet. Signed-off-by: Oleksandr Kolomeiets --- drivers/net/ntnic/include/hw_mod_backend.h | 14 ++ drivers/net/ntnic/include/hw_mod_slc_lr_v2.h | 25 ++++ drivers/net/ntnic/meson.build | 1 + .../nthw/flow_api/flow_backend/flow_backend.c | 66 +++++++++ .../ntnic/nthw/flow_filter/flow_nthw_slc_lr.c | 126 ++++++++++++++++++ .../ntnic/nthw/flow_filter/flow_nthw_slc_lr.h | 54 ++++++++ .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 + .../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 2 + .../nthw/supported/nthw_fpga_reg_defs_slc.h | 34 +++++ .../supported/nthw_fpga_reg_defs_slc_lr.h | 23 ++++ 10 files changed, 346 insertions(+) create mode 100644 drivers/net/ntnic/include/hw_mod_slc_lr_v2.h create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.c create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h diff --git a/drivers/net/ntnic/include/hw_mod_backend.h b/drivers/net/ntnic/include/hw_mod_backend.h index 84f2ed6c6a..309365f30d 100644 --- a/drivers/net/ntnic/include/hw_mod_backend.h +++ b/drivers/net/ntnic/include/hw_mod_backend.h @@ -13,6 +13,7 @@ #include "hw_mod_flm_v25.h" #include "hw_mod_km_v7.h" #include "hw_mod_qsl_v7.h" +#include "hw_mod_slc_lr_v2.h" #include "hw_mod_hsh_v5.h" #define MAX_PHYS_ADAPTERS 8 @@ -96,6 +97,13 @@ struct qsl_func_s { }; }; +struct slc_lr_func_s { + COMMON_FUNC_INFO_S; + union { + struct hw_mod_slc_lr_v2_s v2; + }; +}; + enum debug_mode_e { FLOW_BACKEND_DEBUG_MODE_NONE = 0x0000, FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001 @@ -214,6 +222,12 @@ struct flow_api_backend_ops { int (*qsl_qst_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); int (*qsl_qen_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); int (*qsl_unmq_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); + + /* SLC LR */ + bool (*get_slc_lr_present)(void *dev); + uint32_t (*get_slc_lr_version)(void *dev); + int (*slc_lr_rcp_flush)(void *dev, const struct slc_lr_func_s *slc_lr, int category, + int cnt); }; struct flow_api_backend_s { diff --git a/drivers/net/ntnic/include/hw_mod_slc_lr_v2.h b/drivers/net/ntnic/include/hw_mod_slc_lr_v2.h new file mode 100644 index 0000000000..718a3cff27 --- /dev/null +++ b/drivers/net/ntnic/include/hw_mod_slc_lr_v2.h @@ -0,0 +1,25 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _HW_MOD_SLC_LR_V2_H_ +#define _HW_MOD_SLC_LR_V2_H_ + +#include + +struct slc_lr_v2_rcp_s { + uint32_t head_slc_en; + uint32_t head_dyn; + int32_t head_ofs; + uint32_t tail_slc_en; + uint32_t tail_dyn; + int32_t tail_ofs; + uint32_t pcap; +}; + +struct hw_mod_slc_lr_v2_s { + struct slc_lr_v2_rcp_s *rcp; +}; + +#endif /* _HW_MOD_SLC_V2_H_ */ diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index c7c5cd997f..2c303f6980 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -53,6 +53,7 @@ sources = files( 'nthw/flow_filter/flow_nthw_info.c', 'nthw/flow_filter/flow_nthw_km.c', 'nthw/flow_filter/flow_nthw_qsl.c', + 'nthw/flow_filter/flow_nthw_slc_lr.c', 'nthw/model/nthw_fpga_model.c', 'nthw/nthw_platform.c', 'nthw/nthw_rac.c', diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c index a2422f8b31..6188d900bb 100644 --- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c +++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c @@ -12,6 +12,7 @@ #include "flow_nthw_flm.h" #include "flow_nthw_hsh.h" #include "flow_nthw_qsl.h" +#include "flow_nthw_slc_lr.h" #include "ntnic_mod_reg.h" #include "nthw_fpga_model.h" #include "hw_mod_backend.h" @@ -32,6 +33,7 @@ static struct backend_dev_s { struct flm_nthw *p_flm_nthw; struct hsh_nthw *p_hsh_nthw; struct qsl_nthw *p_qsl_nthw; + struct slc_lr_nthw *p_slc_lr_nthw; struct ifr_nthw *p_ifr_nthw; /* TPE module */ } be_devs[MAX_PHYS_ADAPTERS]; @@ -1436,6 +1438,55 @@ static int qsl_unmq_flush(void *be_dev, const struct qsl_func_s *qsl, int entry, return 0; } +/* + * SLC LR + */ + +static bool slc_lr_get_present(void *be_dev) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + return be->p_slc_lr_nthw != NULL; +} + +static uint32_t slc_lr_get_version(void *be_dev) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + return (uint32_t)((nthw_module_get_major_version(be->p_slc_lr_nthw->m_slc_lr) << 16) | + (nthw_module_get_minor_version(be->p_slc_lr_nthw->m_slc_lr) & 0xffff)); +} + +static int slc_lr_rcp_flush(void *be_dev, const struct slc_lr_func_s *slc_lr, int category, + int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, slc_lr, be->p_slc_lr_nthw); + + if (slc_lr->ver == 2) { + slc_lr_nthw_rcp_cnt(be->p_slc_lr_nthw, 1); + + for (int i = 0; i < cnt; i++) { + slc_lr_nthw_rcp_select(be->p_slc_lr_nthw, category + i); + slc_lr_nthw_rcp_head_slc_en(be->p_slc_lr_nthw, + slc_lr->v2.rcp[category + i].head_slc_en); + slc_lr_nthw_rcp_head_dyn(be->p_slc_lr_nthw, + slc_lr->v2.rcp[category + i].head_dyn); + slc_lr_nthw_rcp_head_ofs(be->p_slc_lr_nthw, + slc_lr->v2.rcp[category + i].head_ofs); + slc_lr_nthw_rcp_tail_slc_en(be->p_slc_lr_nthw, + slc_lr->v2.rcp[category + i].tail_slc_en); + slc_lr_nthw_rcp_tail_dyn(be->p_slc_lr_nthw, + slc_lr->v2.rcp[category + i].tail_dyn); + slc_lr_nthw_rcp_tail_ofs(be->p_slc_lr_nthw, + slc_lr->v2.rcp[category + i].tail_ofs); + slc_lr_nthw_rcp_pcap(be->p_slc_lr_nthw, slc_lr->v2.rcp[category + i].pcap); + slc_lr_nthw_rcp_flush(be->p_slc_lr_nthw); + } + } + + CHECK_DEBUG_OFF(slc_lr, be->p_slc_lr_nthw); + return 0; +} + /* * DBS */ @@ -1556,6 +1607,10 @@ const struct flow_api_backend_ops flow_be_iface = { qsl_qst_flush, qsl_qen_flush, qsl_unmq_flush, + + slc_lr_get_present, + slc_lr_get_version, + slc_lr_rcp_flush, }; const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, void **dev) @@ -1626,6 +1681,16 @@ const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, vo be_devs[physical_adapter_no].p_qsl_nthw = NULL; } + /* Init nthw SLC LR */ + if (slc_lr_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) { + struct slc_lr_nthw *pslclrnthw = slc_lr_nthw_new(); + slc_lr_nthw_init(pslclrnthw, p_fpga, physical_adapter_no); + be_devs[physical_adapter_no].p_slc_lr_nthw = pslclrnthw; + + } else { + be_devs[physical_adapter_no].p_slc_lr_nthw = NULL; + } + be_devs[physical_adapter_no].adapter_no = physical_adapter_no; *dev = (void *)&be_devs[physical_adapter_no]; @@ -1641,6 +1706,7 @@ static void bin_flow_backend_done(void *dev) flm_nthw_delete(be_dev->p_flm_nthw); hsh_nthw_delete(be_dev->p_hsh_nthw); qsl_nthw_delete(be_dev->p_qsl_nthw); + slc_lr_nthw_delete(be_dev->p_slc_lr_nthw); } static const struct flow_backend_ops ops = { diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.c b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.c new file mode 100644 index 0000000000..5961df7735 --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.c @@ -0,0 +1,126 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "flow_nthw_slc_lr.h" + +void slc_lr_nthw_set_debug_mode(struct slc_lr_nthw *p, unsigned int n_debug_mode) +{ + nthw_module_set_debug_mode(p->m_slc_lr, n_debug_mode); +} + +struct slc_lr_nthw *slc_lr_nthw_new(void) +{ + struct slc_lr_nthw *p = malloc(sizeof(struct slc_lr_nthw)); + + if (p) + (void)memset(p, 0, sizeof(*p)); + + return p; +} + +void slc_lr_nthw_delete(struct slc_lr_nthw *p) +{ + if (p) { + (void)memset(p, 0, sizeof(*p)); + free(p); + } +} + +int slc_lr_nthw_init(struct slc_lr_nthw *p, nthw_fpga_t *p_fpga, int n_instance) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_SLC_LR, n_instance); + + assert(n_instance >= 0 && n_instance < 256); + + if (p == NULL) + return p_mod == NULL ? -1 : 0; + + if (p_mod == NULL) { + NT_LOG(ERR, NTHW, "%s: Slc %d: no such instance\n", p_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->m_physical_adapter_no = (uint8_t)n_instance; + p->m_slc_lr = nthw_fpga_query_module(p_fpga, MOD_SLC_LR, n_instance); + + /* RCP */ + p->mp_rcp_ctrl = nthw_module_get_register(p->m_slc_lr, SLC_RCP_CTRL); + p->mp_rcp_addr = nthw_register_get_field(p->mp_rcp_ctrl, SLC_RCP_CTRL_ADR); + p->mp_rcp_cnt = nthw_register_get_field(p->mp_rcp_ctrl, SLC_RCP_CTRL_CNT); + p->mp_rcp_data = nthw_module_get_register(p->m_slc_lr, SLC_RCP_DATA); + p->mp_rcp_data_head_slc_en = + nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_HEAD_SLC_EN); + p->mp_rcp_data_head_dyn = nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_HEAD_DYN); + p->mp_rcp_data_head_ofs = nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_HEAD_OFS); + p->mp_rcp_data_tail_slc_en = + nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_TAIL_SLC_EN); + p->mp_rcp_data_tail_dyn = nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_TAIL_DYN); + p->mp_rcp_data_tail_ofs = nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_TAIL_OFS); + p->mp_rcp_data_pcap = nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_PCAP); + + return 0; +} + +/* RCP */ +void slc_lr_nthw_rcp_select(const struct slc_lr_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_addr, val); +} + +void slc_lr_nthw_rcp_cnt(const struct slc_lr_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_cnt, val); +} + +void slc_lr_nthw_rcp_head_slc_en(const struct slc_lr_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_head_slc_en, val); +} + +void slc_lr_nthw_rcp_head_dyn(const struct slc_lr_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_head_dyn, val); +} + +void slc_lr_nthw_rcp_head_ofs(const struct slc_lr_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_head_ofs, val); +} + +void slc_lr_nthw_rcp_tail_slc_en(const struct slc_lr_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_tail_slc_en, val); +} + +void slc_lr_nthw_rcp_tail_dyn(const struct slc_lr_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_tail_dyn, val); +} + +void slc_lr_nthw_rcp_tail_ofs(const struct slc_lr_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_tail_ofs, val); +} + +void slc_lr_nthw_rcp_pcap(const struct slc_lr_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_pcap, val); +} + +void slc_lr_nthw_rcp_flush(const struct slc_lr_nthw *p) +{ + nthw_register_flush(p->mp_rcp_ctrl, 1); + nthw_register_flush(p->mp_rcp_data, 1); +} diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.h b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.h new file mode 100644 index 0000000000..2eed32c022 --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.h @@ -0,0 +1,54 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __FLOW_NTHW_SLC_LR_H__ +#define __FLOW_NTHW_SLC_LR_H__ + +#include + +#include "nthw_fpga_model.h" + +struct slc_lr_nthw { + uint8_t m_physical_adapter_no; + nthw_fpga_t *mp_fpga; + + nthw_module_t *m_slc_lr; + + nthw_register_t *mp_rcp_ctrl; + nthw_field_t *mp_rcp_addr; + nthw_field_t *mp_rcp_cnt; + nthw_register_t *mp_rcp_data; + + nthw_field_t *mp_rcp_data_head_slc_en; + nthw_field_t *mp_rcp_data_head_dyn; + nthw_field_t *mp_rcp_data_head_ofs; + nthw_field_t *mp_rcp_data_tail_slc_en; + nthw_field_t *mp_rcp_data_tail_dyn; + nthw_field_t *mp_rcp_data_tail_ofs; + nthw_field_t *mp_rcp_data_pcap; +}; + +typedef struct slc_lr_nthw slc_lr_nthw_t; + +struct slc_lr_nthw *slc_lr_nthw_new(void); +void slc_lr_nthw_delete(struct slc_lr_nthw *p); +int slc_lr_nthw_init(struct slc_lr_nthw *p, nthw_fpga_t *p_fpga, int n_instance); + +int slc_lr_nthw_setup(struct slc_lr_nthw *p, int n_idx, int n_idx_cnt); +void slc_lr_nthw_set_debug_mode(struct slc_lr_nthw *p, unsigned int n_debug_mode); + +/* RCP */ +void slc_lr_nthw_rcp_select(const struct slc_lr_nthw *p, uint32_t val); +void slc_lr_nthw_rcp_cnt(const struct slc_lr_nthw *p, uint32_t val); +void slc_lr_nthw_rcp_head_slc_en(const struct slc_lr_nthw *p, uint32_t val); +void slc_lr_nthw_rcp_head_dyn(const struct slc_lr_nthw *p, uint32_t val); +void slc_lr_nthw_rcp_head_ofs(const struct slc_lr_nthw *p, int32_t val); +void slc_lr_nthw_rcp_tail_slc_en(const struct slc_lr_nthw *p, uint32_t val); +void slc_lr_nthw_rcp_tail_dyn(const struct slc_lr_nthw *p, uint32_t val); +void slc_lr_nthw_rcp_tail_ofs(const struct slc_lr_nthw *p, int32_t val); +void slc_lr_nthw_rcp_pcap(const struct slc_lr_nthw *p, uint32_t val); +void slc_lr_nthw_rcp_flush(const struct slc_lr_nthw *p); + +#endif /* __FLOW_NTHW_SLC_LR_H__ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h index b159da7597..22682b6a5f 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h @@ -33,6 +33,7 @@ #define MOD_RAC (0xae830b42UL) #define MOD_RST9563 (0x385d6d1dUL) #define MOD_SDC (0xd2369530UL) +#define MOD_SLC_LR (0x969fc50bUL) #define MOD_IDX_COUNT (14) /* aliases - only aliases go below this point */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h index 7b99a7fbdb..f775a4b33a 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h @@ -32,6 +32,8 @@ #include "nthw_fpga_reg_defs_rac.h" #include "nthw_fpga_reg_defs_rst9563.h" #include "nthw_fpga_reg_defs_sdc.h" +#include "nthw_fpga_reg_defs_slc.h" +#include "nthw_fpga_reg_defs_slc_lr.h" /* aliases */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h new file mode 100644 index 0000000000..11a8ef79a1 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h @@ -0,0 +1,34 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Napatech A/S + */ + +/* + * nthw_fpga_reg_defs_slc.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_SLC_ +#define _NTHW_FPGA_REG_DEFS_SLC_ + +/* SLC */ +#define NTHW_MOD_SLC (0x1aef1f38UL) +#define SLC_RCP_CTRL (0xa3373b1UL) +#define SLC_RCP_CTRL_ADR (0xe64629e7UL) +#define SLC_RCP_CTRL_CNT (0xf64eb036UL) +#define SLC_RCP_DATA (0xa5e2f1a8UL) +#define SLC_RCP_DATA_HEAD_DYN (0x86b55a78UL) +#define SLC_RCP_DATA_HEAD_OFS (0x24bcd7deUL) +#define SLC_RCP_DATA_HEAD_SLC_EN (0x61cf5ef7UL) +#define SLC_RCP_DATA_PCAP (0x84909c04UL) +#define SLC_RCP_DATA_TAIL_DYN (0x85cd93a3UL) +#define SLC_RCP_DATA_TAIL_OFS (0x27c41e05UL) +#define SLC_RCP_DATA_TAIL_SLC_EN (0xa4f5112cUL) + +#endif /* _NTHW_FPGA_REG_DEFS_SLC_ */ + +/* + * Auto-generated file - do *NOT* edit + */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h new file mode 100644 index 0000000000..ef1f358cb3 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h @@ -0,0 +1,23 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Napatech A/S + */ + +/* + * nthw_fpga_reg_defs_slc_lr.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_SLC_LR_ +#define _NTHW_FPGA_REG_DEFS_SLC_LR_ + +/* SLC_LR */ +#define NTHW_MOD_SLC_LR (0x969fc50bUL) + +#endif /* _NTHW_FPGA_REG_DEFS_SLC_LR_ */ + +/* + * Auto-generated file - do *NOT* edit + */