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It supports both exact match which is implemented with a CAM, and wildcards which is implemented with a TCAM. Signed-off-by: Oleksandr Kolomeiets --- drivers/net/ntnic/include/hw_mod_backend.h | 28 + drivers/net/ntnic/include/hw_mod_km_v7.h | 96 +++ drivers/net/ntnic/meson.build | 1 + .../nthw/flow_api/flow_backend/flow_backend.c | 206 ++++++ .../net/ntnic/nthw/flow_filter/flow_nthw_km.c | 610 ++++++++++++++++++ .../net/ntnic/nthw/flow_filter/flow_nthw_km.h | 214 ++++++ .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 + .../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 + .../nthw/supported/nthw_fpga_reg_defs_km.h | 126 ++++ 9 files changed, 1283 insertions(+) create mode 100644 drivers/net/ntnic/include/hw_mod_km_v7.h create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_km.c create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_km.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h diff --git a/drivers/net/ntnic/include/hw_mod_backend.h b/drivers/net/ntnic/include/hw_mod_backend.h index ce2c0cf7cf..b921c06643 100644 --- a/drivers/net/ntnic/include/hw_mod_backend.h +++ b/drivers/net/ntnic/include/hw_mod_backend.h @@ -10,6 +10,7 @@ #include "hw_mod_cat_v18.h" #include "hw_mod_cat_v21.h" +#include "hw_mod_km_v7.h" #define MAX_PHYS_ADAPTERS 8 @@ -40,6 +41,23 @@ struct cat_func_s { }; }; +struct km_func_s { + COMMON_FUNC_INFO_S; + uint32_t nb_categories; + uint32_t nb_cam_banks; + uint32_t nb_cam_record_words; + uint32_t nb_cam_records; + uint32_t nb_tcam_banks; + uint32_t nb_tcam_bank_width; + /* not read from backend, but rather set using version */ + uint32_t nb_km_rcp_mask_a_word_size; + /* --- || --- */ + uint32_t nb_km_rcp_mask_b_word_size; + union { + struct hw_mod_km_v7_s v7; + }; +}; + enum debug_mode_e { FLOW_BACKEND_DEBUG_MODE_NONE = 0x0000, FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001 @@ -112,6 +130,16 @@ struct flow_api_backend_ops { int (*cat_rck_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); int (*cat_len_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); int (*cat_kcc_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); + + /* KM */ + bool (*get_km_present)(void *dev); + uint32_t (*get_km_version)(void *dev); + int (*km_rcp_flush)(void *dev, const struct km_func_s *km, int category, int cnt); + int (*km_cam_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); + int (*km_tcam_flush)(void *dev, const struct km_func_s *km, int bank, int byte, int value, + int cnt); + int (*km_tci_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); + int (*km_tcq_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); }; struct flow_api_backend_s { diff --git a/drivers/net/ntnic/include/hw_mod_km_v7.h b/drivers/net/ntnic/include/hw_mod_km_v7.h new file mode 100644 index 0000000000..dcc28c1812 --- /dev/null +++ b/drivers/net/ntnic/include/hw_mod_km_v7.h @@ -0,0 +1,96 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _HW_MOD_KM_V7_H_ +#define _HW_MOD_KM_V7_H_ + +#include + +struct km_v7_rcp_s { + uint32_t qw0_dyn; + int32_t qw0_ofs; + uint32_t qw0_sel_a; + uint32_t qw0_sel_b; + uint32_t qw4_dyn; + int32_t qw4_ofs; + uint32_t qw4_sel_a; + uint32_t qw4_sel_b; + uint32_t dw8_dyn; + int32_t dw8_ofs; + uint32_t dw8_sel_a; + uint32_t dw8_sel_b; + uint32_t dw10_dyn; + int32_t dw10_ofs; + uint32_t dw10_sel_a; + uint32_t dw10_sel_b; + uint32_t swx_cch; + uint32_t swx_sel_a; + uint32_t swx_sel_b; + uint32_t mask_d_a[12]; + uint32_t mask_b[6]; + uint32_t dual; + uint32_t paired; + uint32_t el_a; + uint32_t el_b; + uint32_t info_a; + uint32_t info_b; + uint32_t ftm_a; + uint32_t ftm_b; + uint32_t bank_a; + uint32_t bank_b; + uint32_t kl_a; + uint32_t kl_b; + uint32_t keyway_a; + uint32_t keyway_b; + uint32_t synergy_mode; + uint32_t dw0_b_dyn; + int32_t dw0_b_ofs; + uint32_t dw2_b_dyn; + int32_t dw2_b_ofs; + uint32_t sw4_b_dyn; + int32_t sw4_b_ofs; + uint32_t sw5_b_dyn; + int32_t sw5_b_ofs; +}; + +struct km_v7_cam_s { + uint32_t w0; + uint32_t w1; + uint32_t w2; + uint32_t w3; + uint32_t w4; + uint32_t w5; + uint32_t ft0; + uint32_t ft1; + uint32_t ft2; + uint32_t ft3; + uint32_t ft4; + uint32_t ft5; +}; + +struct km_v7_tcam_s { + uint32_t t[3]; + uint32_t dirty; +}; + +struct km_v7_tci_s { + uint32_t color; + uint32_t ft; +}; + +struct km_v7_tcq_s { + uint32_t bank_mask; + uint32_t qual; +}; + +struct hw_mod_km_v7_s { + struct km_v7_rcp_s *rcp; + struct km_v7_cam_s *cam; + struct km_v7_tcam_s *tcam; + struct km_v7_tci_s *tci; + struct km_v7_tcq_s *tcq; +}; + +#endif /* _HW_MOD_KM_V7_H_ */ diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 09631fb84b..8d297cbb61 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -48,6 +48,7 @@ sources = files( 'nthw/flow_api/flow_filter.c', 'nthw/flow_filter/flow_nthw_cat.c', 'nthw/flow_filter/flow_nthw_info.c', + 'nthw/flow_filter/flow_nthw_km.c', 'nthw/model/nthw_fpga_model.c', 'nthw/nthw_platform.c', 'nthw/nthw_rac.c', diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c index 16cc24ec72..c004000cc0 100644 --- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c +++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c @@ -7,6 +7,7 @@ #include "flow_nthw_info.h" #include "flow_nthw_cat.h" +#include "flow_nthw_km.h" #include "ntnic_mod_reg.h" #include "nthw_fpga_model.h" #include "hw_mod_backend.h" @@ -23,6 +24,7 @@ static struct backend_dev_s { enum debug_mode_e dmode; struct info_nthw *p_info_nthw; struct cat_nthw *p_cat_nthw; + struct km_nthw *p_km_nthw; } be_devs[MAX_PHYS_ADAPTERS]; #define CHECK_DEBUG_ON(be, mod, inst) \ @@ -720,6 +722,191 @@ static int cat_kcc_flush(void *be_dev, const struct cat_func_s *cat, int len_ind return 0; } +/* + * KM + */ + +static bool km_get_present(void *be_dev) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + return be->p_km_nthw != NULL; +} + +static uint32_t km_get_version(void *be_dev) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + return (uint32_t)((nthw_module_get_major_version(be->p_km_nthw->m_km) << 16) | + (nthw_module_get_minor_version(be->p_km_nthw->m_km) & 0xffff)); +} + +static int km_rcp_flush(void *be_dev, const struct km_func_s *km, int category, int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + + CHECK_DEBUG_ON(be, km, be->p_km_nthw); + + if (km->ver == 7) { + km_nthw_rcp_cnt(be->p_km_nthw, 1); + + for (int i = 0; i < cnt; i++) { + km_nthw_rcp_select(be->p_km_nthw, category + i); + km_nthw_rcp_qw0_dyn(be->p_km_nthw, km->v7.rcp[category + i].qw0_dyn); + km_nthw_rcp_qw0_ofs(be->p_km_nthw, km->v7.rcp[category + i].qw0_ofs); + km_nthw_rcp_qw0_sel_a(be->p_km_nthw, km->v7.rcp[category + i].qw0_sel_a); + km_nthw_rcp_qw0_sel_b(be->p_km_nthw, km->v7.rcp[category + i].qw0_sel_b); + km_nthw_rcp_qw4_dyn(be->p_km_nthw, km->v7.rcp[category + i].qw4_dyn); + km_nthw_rcp_qw4_ofs(be->p_km_nthw, km->v7.rcp[category + i].qw4_ofs); + km_nthw_rcp_qw4_sel_a(be->p_km_nthw, km->v7.rcp[category + i].qw4_sel_a); + km_nthw_rcp_qw4_sel_b(be->p_km_nthw, km->v7.rcp[category + i].qw4_sel_b); + km_nthw_rcp_dw8_dyn(be->p_km_nthw, km->v7.rcp[category + i].dw8_dyn); + km_nthw_rcp_dw8_ofs(be->p_km_nthw, km->v7.rcp[category + i].dw8_ofs); + km_nthw_rcp_dw8_sel_a(be->p_km_nthw, km->v7.rcp[category + i].dw8_sel_a); + km_nthw_rcp_dw8_sel_b(be->p_km_nthw, km->v7.rcp[category + i].dw8_sel_b); + km_nthw_rcp_dw10_dyn(be->p_km_nthw, km->v7.rcp[category + i].dw10_dyn); + km_nthw_rcp_dw10_ofs(be->p_km_nthw, km->v7.rcp[category + i].dw10_ofs); + km_nthw_rcp_dw10_sel_a(be->p_km_nthw, km->v7.rcp[category + i].dw10_sel_a); + km_nthw_rcp_dw10_sel_b(be->p_km_nthw, km->v7.rcp[category + i].dw10_sel_b); + km_nthw_rcp_swx_cch(be->p_km_nthw, km->v7.rcp[category + i].swx_cch); + km_nthw_rcp_swx_sel_a(be->p_km_nthw, km->v7.rcp[category + i].swx_sel_a); + km_nthw_rcp_swx_sel_b(be->p_km_nthw, km->v7.rcp[category + i].swx_sel_b); + km_nthw_rcp_mask_da(be->p_km_nthw, km->v7.rcp[category + i].mask_d_a); + km_nthw_rcp_mask_b(be->p_km_nthw, km->v7.rcp[category + i].mask_b); + km_nthw_rcp_dual(be->p_km_nthw, km->v7.rcp[category + i].dual); + km_nthw_rcp_paired(be->p_km_nthw, km->v7.rcp[category + i].paired); + km_nthw_rcp_el_a(be->p_km_nthw, km->v7.rcp[category + i].el_a); + km_nthw_rcp_el_b(be->p_km_nthw, km->v7.rcp[category + i].el_b); + km_nthw_rcp_info_a(be->p_km_nthw, km->v7.rcp[category + i].info_a); + km_nthw_rcp_info_b(be->p_km_nthw, km->v7.rcp[category + i].info_b); + km_nthw_rcp_ftm_a(be->p_km_nthw, km->v7.rcp[category + i].ftm_a); + km_nthw_rcp_ftm_b(be->p_km_nthw, km->v7.rcp[category + i].ftm_b); + km_nthw_rcp_bank_a(be->p_km_nthw, km->v7.rcp[category + i].bank_a); + km_nthw_rcp_bank_b(be->p_km_nthw, km->v7.rcp[category + i].bank_b); + km_nthw_rcp_kl_a(be->p_km_nthw, km->v7.rcp[category + i].kl_a); + km_nthw_rcp_kl_b(be->p_km_nthw, km->v7.rcp[category + i].kl_b); + km_nthw_rcp_keyway_a(be->p_km_nthw, km->v7.rcp[category + i].keyway_a); + km_nthw_rcp_keyway_b(be->p_km_nthw, km->v7.rcp[category + i].keyway_b); + km_nthw_rcp_synergy_mode(be->p_km_nthw, + km->v7.rcp[category + i].synergy_mode); + km_nthw_rcp_dw0_b_dyn(be->p_km_nthw, km->v7.rcp[category + i].dw0_b_dyn); + km_nthw_rcp_dw0_b_ofs(be->p_km_nthw, km->v7.rcp[category + i].dw0_b_ofs); + km_nthw_rcp_dw2_b_dyn(be->p_km_nthw, km->v7.rcp[category + i].dw2_b_dyn); + km_nthw_rcp_dw2_b_ofs(be->p_km_nthw, km->v7.rcp[category + i].dw2_b_ofs); + km_nthw_rcp_sw4_b_dyn(be->p_km_nthw, km->v7.rcp[category + i].sw4_b_dyn); + km_nthw_rcp_sw4_b_ofs(be->p_km_nthw, km->v7.rcp[category + i].sw4_b_ofs); + km_nthw_rcp_sw5_b_dyn(be->p_km_nthw, km->v7.rcp[category + i].sw5_b_dyn); + km_nthw_rcp_sw5_b_ofs(be->p_km_nthw, km->v7.rcp[category + i].sw5_b_ofs); + km_nthw_rcp_flush(be->p_km_nthw); + } + } + + CHECK_DEBUG_OFF(km, be->p_km_nthw); + return 0; +} + +static int km_cam_flush(void *be_dev, const struct km_func_s *km, int bank, int record, int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, km, be->p_km_nthw); + + if (km->ver == 7) { + km_nthw_cam_cnt(be->p_km_nthw, 1); + + for (int i = 0; i < cnt; i++) { + km_nthw_cam_select(be->p_km_nthw, (bank << 11) + record + i); + km_nthw_cam_w0(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].w0); + km_nthw_cam_w1(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].w1); + km_nthw_cam_w2(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].w2); + km_nthw_cam_w3(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].w3); + km_nthw_cam_w4(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].w4); + km_nthw_cam_w5(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].w5); + km_nthw_cam_ft0(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].ft0); + km_nthw_cam_ft1(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].ft1); + km_nthw_cam_ft2(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].ft2); + km_nthw_cam_ft3(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].ft3); + km_nthw_cam_ft4(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].ft4); + km_nthw_cam_ft5(be->p_km_nthw, km->v7.cam[(bank << 11) + record + i].ft5); + km_nthw_cam_flush(be->p_km_nthw); + } + } + + CHECK_DEBUG_OFF(km, be->p_km_nthw); + return 0; +} + +static int km_tcam_flush(void *be_dev, const struct km_func_s *km, int bank, int byte, int value, + int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, km, be->p_km_nthw); + + if (km->ver == 7) { + int start_idx = bank * 4 * 256 + byte * 256 + value; + km_nthw_tcam_cnt(be->p_km_nthw, 1); + + for (int i = 0; i < cnt; i++) { + if (km->v7.tcam[start_idx + i].dirty) { + km_nthw_tcam_select(be->p_km_nthw, start_idx + i); + km_nthw_tcam_t(be->p_km_nthw, km->v7.tcam[start_idx + i].t); + km_nthw_tcam_flush(be->p_km_nthw); + km->v7.tcam[start_idx + i].dirty = 0; + } + } + } + + CHECK_DEBUG_OFF(km, be->p_km_nthw); + return 0; +} + +/* + * bank is the TCAM bank, index is the index within the bank (0..71) + */ +static int km_tci_flush(void *be_dev, const struct km_func_s *km, int bank, int index, int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, km, be->p_km_nthw); + + if (km->ver == 7) { + /* TCAM bank width in version 3 = 72 */ + km_nthw_tci_cnt(be->p_km_nthw, 1); + + for (int i = 0; i < cnt; i++) { + km_nthw_tci_select(be->p_km_nthw, bank * 72 + index + i); + km_nthw_tci_color(be->p_km_nthw, km->v7.tci[bank * 72 + index + i].color); + km_nthw_tci_ft(be->p_km_nthw, km->v7.tci[bank * 72 + index + i].ft); + km_nthw_tci_flush(be->p_km_nthw); + } + } + + CHECK_DEBUG_OFF(km, be->p_km_nthw); + return 0; +} + +/* + * bank is the TCAM bank, index is the index within the bank (0..71) + */ +static int km_tcq_flush(void *be_dev, const struct km_func_s *km, int bank, int index, int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, km, be->p_km_nthw); + + if (km->ver == 7) { + /* TCAM bank width in version 3 = 72 */ + km_nthw_tcq_cnt(be->p_km_nthw, 1); + + for (int i = 0; i < cnt; i++) { + /* adr = lover 4 bits = bank, upper 7 bits = index */ + km_nthw_tcq_select(be->p_km_nthw, bank + (index << 4) + i); + km_nthw_tcq_bank_mask(be->p_km_nthw, + km->v7.tcq[bank + (index << 4) + i].bank_mask); + km_nthw_tcq_qual(be->p_km_nthw, km->v7.tcq[bank + (index << 4) + i].qual); + km_nthw_tcq_flush(be->p_km_nthw); + } + } + + CHECK_DEBUG_OFF(km, be->p_km_nthw); + return 0; +} + /* * DBS */ @@ -805,6 +992,14 @@ const struct flow_api_backend_ops flow_be_iface = { cat_rck_flush, cat_len_flush, cat_kcc_flush, + + km_get_present, + km_get_version, + km_rcp_flush, + km_cam_flush, + km_tcam_flush, + km_tci_flush, + km_tcq_flush, }; const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, void **dev) @@ -825,6 +1020,16 @@ const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, vo be_devs[physical_adapter_no].p_cat_nthw = NULL; } + /* Init nthw KM */ + if (km_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) { + struct km_nthw *pkmnthw = km_nthw_new(); + km_nthw_init(pkmnthw, p_fpga, physical_adapter_no); + be_devs[physical_adapter_no].p_km_nthw = pkmnthw; + + } else { + be_devs[physical_adapter_no].p_km_nthw = NULL; + } + be_devs[physical_adapter_no].adapter_no = physical_adapter_no; *dev = (void *)&be_devs[physical_adapter_no]; @@ -836,6 +1041,7 @@ static void bin_flow_backend_done(void *dev) struct backend_dev_s *be_dev = (struct backend_dev_s *)dev; info_nthw_delete(be_dev->p_info_nthw); cat_nthw_delete(be_dev->p_cat_nthw); + km_nthw_delete(be_dev->p_km_nthw); } static const struct flow_backend_ops ops = { diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_km.c b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_km.c new file mode 100644 index 0000000000..db720bd6f8 --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_km.c @@ -0,0 +1,610 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include +#include + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "flow_nthw_km.h" + +#define CHECK_AND_SET_VALUE(a, val) \ + do { \ + nthw_field_t *temp_a = (a); \ + if (temp_a) { \ + nthw_field_set_val32(temp_a, val); \ + } \ + } while (0) + +void km_nthw_set_debug_mode(struct km_nthw *p, unsigned int n_debug_mode) +{ + nthw_module_set_debug_mode(p->m_km, n_debug_mode); +} + +struct km_nthw *km_nthw_new(void) +{ + struct km_nthw *p = malloc(sizeof(struct km_nthw)); + + if (p) + (void)memset(p, 0, sizeof(*p)); + + return p; +} + +void km_nthw_delete(struct km_nthw *p) +{ + if (p) { + (void)memset(p, 0, sizeof(*p)); + free(p); + } +} + +int km_nthw_init(struct km_nthw *p, nthw_fpga_t *p_fpga, int n_instance) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_KM, n_instance); + + assert(n_instance >= 0 && n_instance < 256); + + if (p == NULL) + return p_mod == NULL ? -1 : 0; + + if (p_mod == NULL) { + NT_LOG(ERR, NTHW, "%s: Km %d: no such instance\n", p_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->m_physical_adapter_no = (uint8_t)n_instance; + p->m_km = p_mod; + + /* RCP */ + p->mp_rcp_ctrl = nthw_module_get_register(p->m_km, KM_RCP_CTRL); + p->mp_rcp_addr = nthw_register_get_field(p->mp_rcp_ctrl, KM_RCP_CTRL_ADR); + p->mp_rcp_cnt = nthw_register_get_field(p->mp_rcp_ctrl, KM_RCP_CTRL_CNT); + p->mp_rcp_data = nthw_module_get_register(p->m_km, KM_RCP_DATA); + p->mp_rcp_data_qw0_dyn = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_QW0_DYN); + p->mp_rcp_data_qw0_ofs = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_QW0_OFS); + p->mp_rcp_data_qw0_sel_a = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_QW0_SEL_A); + p->mp_rcp_data_qw0_sel_b = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_QW0_SEL_B); + p->mp_rcp_data_qw4_dyn = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_QW4_DYN); + p->mp_rcp_data_qw4_ofs = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_QW4_OFS); + p->mp_rcp_data_qw4_sel_a = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_QW4_SEL_A); + p->mp_rcp_data_qw4_sel_b = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_QW4_SEL_B); + + p->mp_rcp_data_sw8_dyn = nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW8_DYN); + p->mp_rcp_data_dw8_dyn = nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW8_DYN); + + p->mp_rcp_data_swx_ovs_sb = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SWX_OVS_SB); + p->mp_rcp_data_swx_cch = nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SWX_CCH); + p->mp_rcp_data_swx_sel_a = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_SWX_SEL_A); + p->mp_rcp_data_swx_sel_b = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_SWX_SEL_B); + p->mp_rcp_data_mask_a = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_MASK_A); + p->mp_rcp_data_mask_b = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_MASK_B); + p->mp_rcp_data_dual = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_DUAL); + p->mp_rcp_data_paired = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_PAIRED); + p->mp_rcp_data_el_a = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_EL_A); + p->mp_rcp_data_el_b = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_EL_B); + p->mp_rcp_data_info_a = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_INFO_A); + p->mp_rcp_data_info_b = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_INFO_B); + p->mp_rcp_data_ftm_a = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_FTM_A); + p->mp_rcp_data_ftm_b = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_FTM_B); + p->mp_rcp_data_bank_a = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_BANK_A); + p->mp_rcp_data_bank_b = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_BANK_B); + p->mp_rcp_data_kl_a = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_KL_A); + p->mp_rcp_data_kl_b = nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_KL_B); + p->mp_rcp_data_flow_set = nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_FLOW_SET); + p->mp_rcp_data_keyway_a = nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_KEYWAY_A); + p->mp_rcp_data_keyway_b = nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_KEYWAY_B); + p->mp_rcp_data_synergy_mode = + nthw_register_get_field(p->mp_rcp_data, KM_RCP_DATA_SYNERGY_MODE); + + /* CAM */ + p->mp_cam_ctrl = nthw_module_get_register(p->m_km, KM_CAM_CTRL); + p->mp_cam_addr = nthw_register_get_field(p->mp_cam_ctrl, KM_CAM_CTRL_ADR); + p->mp_cam_cnt = nthw_register_get_field(p->mp_cam_ctrl, KM_CAM_CTRL_CNT); + p->mp_cam_data = nthw_module_get_register(p->m_km, KM_CAM_DATA); + p->mp_cam_data_w0 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_W0); + p->mp_cam_data_w1 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_W1); + p->mp_cam_data_w2 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_W2); + p->mp_cam_data_w3 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_W3); + p->mp_cam_data_w4 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_W4); + p->mp_cam_data_w5 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_W5); + p->mp_cam_data_ft0 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_FT0); + p->mp_cam_data_ft1 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_FT1); + p->mp_cam_data_ft2 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_FT2); + p->mp_cam_data_ft3 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_FT3); + p->mp_cam_data_ft4 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_FT4); + p->mp_cam_data_ft5 = nthw_register_get_field(p->mp_cam_data, KM_CAM_DATA_FT5); + /* TCAM */ + p->mp_tcam_ctrl = nthw_module_get_register(p->m_km, KM_TCAM_CTRL); + p->mp_tcam_addr = nthw_register_get_field(p->mp_tcam_ctrl, KM_TCAM_CTRL_ADR); + p->mp_tcam_cnt = nthw_register_get_field(p->mp_tcam_ctrl, KM_TCAM_CTRL_CNT); + p->mp_tcam_data = nthw_module_get_register(p->m_km, KM_TCAM_DATA); + p->mp_tcam_data_t = nthw_register_get_field(p->mp_tcam_data, KM_TCAM_DATA_T); + /* TCI */ + p->mp_tci_ctrl = nthw_module_get_register(p->m_km, KM_TCI_CTRL); + p->mp_tci_addr = nthw_register_get_field(p->mp_tci_ctrl, KM_TCI_CTRL_ADR); + p->mp_tci_cnt = nthw_register_get_field(p->mp_tci_ctrl, KM_TCI_CTRL_CNT); + p->mp_tci_data = nthw_module_get_register(p->m_km, KM_TCI_DATA); + p->mp_tci_data_color = nthw_register_get_field(p->mp_tci_data, KM_TCI_DATA_COLOR); + p->mp_tci_data_ft = nthw_register_get_field(p->mp_tci_data, KM_TCI_DATA_FT); + /* TCQ */ + p->mp_tcq_ctrl = nthw_module_get_register(p->m_km, KM_TCQ_CTRL); + p->mp_tcq_addr = nthw_register_get_field(p->mp_tcq_ctrl, KM_TCQ_CTRL_ADR); + p->mp_tcq_cnt = nthw_register_get_field(p->mp_tcq_ctrl, KM_TCQ_CTRL_CNT); + p->mp_tcq_data = nthw_module_get_register(p->m_km, KM_TCQ_DATA); + p->mp_tcq_data_bank_mask = + nthw_register_query_field(p->mp_tcq_data, KM_TCQ_DATA_BANK_MASK); + p->mp_tcq_data_qual = nthw_register_get_field(p->mp_tcq_data, KM_TCQ_DATA_QUAL); + + p->mp_rcp_data_dw0_b_dyn = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW0_B_DYN); + p->mp_rcp_data_dw0_b_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW0_B_OFS); + p->mp_rcp_data_dw2_b_dyn = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW2_B_DYN); + p->mp_rcp_data_dw2_b_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW2_B_OFS); + p->mp_rcp_data_sw4_b_dyn = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW4_B_DYN); + p->mp_rcp_data_sw4_b_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW4_B_OFS); + p->mp_rcp_data_sw5_b_dyn = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW5_B_DYN); + p->mp_rcp_data_sw5_b_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW5_B_OFS); + + if (!p->mp_rcp_data_dw0_b_dyn) { + /* old field defines */ + p->mp_rcp_data_dw0_b_dyn = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_QW0_B_DYN); + p->mp_rcp_data_dw0_b_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_QW0_B_OFS); + p->mp_rcp_data_dw2_b_dyn = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_QW4_B_DYN); + p->mp_rcp_data_dw2_b_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_QW4_B_OFS); + p->mp_rcp_data_sw4_b_dyn = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW8_B_DYN); + p->mp_rcp_data_sw4_b_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW8_B_OFS); + p->mp_rcp_data_sw5_b_dyn = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW9_B_DYN); + p->mp_rcp_data_sw5_b_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW9_B_OFS); + } + + /* v0.6+ */ + if (p->mp_rcp_data_dw8_dyn) { + p->mp_rcp_data_dw8_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW8_OFS); + p->mp_rcp_data_dw8_sel_a = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW8_SEL_A); + p->mp_rcp_data_dw8_sel_b = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW8_SEL_B); + p->mp_rcp_data_dw10_dyn = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW10_DYN); + p->mp_rcp_data_dw10_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW10_OFS); + p->mp_rcp_data_dw10_sel_a = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW10_SEL_A); + p->mp_rcp_data_dw10_sel_b = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_DW10_SEL_B); + + } else if (p->mp_rcp_data_sw8_dyn) { + p->mp_rcp_data_sw8_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW8_OFS); + p->mp_rcp_data_sw8_sel_a = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW8_SEL_A); + p->mp_rcp_data_sw8_sel_b = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW8_SEL_B); + p->mp_rcp_data_sw9_dyn = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW9_DYN); + p->mp_rcp_data_sw9_ofs = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW9_OFS); + p->mp_rcp_data_sw9_sel_a = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW9_SEL_A); + p->mp_rcp_data_sw9_sel_b = + nthw_register_query_field(p->mp_rcp_data, KM_RCP_DATA_SW9_SEL_B); + } + + return 0; +} + +/* RCP */ +void km_nthw_rcp_select(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_addr, val); +}; + +void km_nthw_rcp_cnt(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_cnt, val); +}; + +void km_nthw_rcp_qw0_dyn(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw0_dyn, val); +}; + +void km_nthw_rcp_qw0_ofs(const struct km_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw0_ofs, val); +}; + +void km_nthw_rcp_qw0_sel_a(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw0_sel_a, val); +}; + +void km_nthw_rcp_qw0_sel_b(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw0_sel_b, val); +}; + +void km_nthw_rcp_qw4_dyn(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw4_dyn, val); +}; + +void km_nthw_rcp_qw4_ofs(const struct km_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw4_ofs, val); +}; + +void km_nthw_rcp_qw4_sel_a(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw4_sel_a, val); +}; + +void km_nthw_rcp_qw4_sel_b(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw4_sel_b, val); +}; + +void km_nthw_rcp_dw8_dyn(const struct km_nthw *p, uint32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_rcp_data_dw8_dyn, val); +}; + +void km_nthw_rcp_swx_cch(const struct km_nthw *p, uint32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_rcp_data_swx_cch, val); +}; + +void km_nthw_rcp_dw8_ofs(const struct km_nthw *p, int32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_rcp_data_dw8_ofs, val); +}; + +void km_nthw_rcp_dw8_sel_a(const struct km_nthw *p, uint32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_rcp_data_dw8_sel_a, val); +}; + +void km_nthw_rcp_dw8_sel_b(const struct km_nthw *p, uint32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_rcp_data_dw8_sel_b, val); +}; + +void km_nthw_rcp_dw10_dyn(const struct km_nthw *p, uint32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_rcp_data_dw10_dyn, val); +}; + +void km_nthw_rcp_dw10_ofs(const struct km_nthw *p, int32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_rcp_data_dw10_ofs, val); +}; + +void km_nthw_rcp_dw10_sel_a(const struct km_nthw *p, uint32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_rcp_data_dw10_sel_a, val); +}; + +void km_nthw_rcp_dw10_sel_b(const struct km_nthw *p, uint32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_rcp_data_dw10_sel_b, val); +}; + +void km_nthw_rcp_swx_sel_a(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_swx_sel_a, val); +}; + +void km_nthw_rcp_swx_sel_b(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_swx_sel_b, val); +}; + +void km_nthw_rcp_mask_b(const struct km_nthw *p, const uint32_t *val) +{ + nthw_field_set_val(p->mp_rcp_data_mask_b, val, p->mp_rcp_data_mask_b->mn_words); +}; + +void km_nthw_rcp_mask_da(const struct km_nthw *p, const uint32_t *val) +{ + nthw_field_set_val(p->mp_rcp_data_mask_a, val, p->mp_rcp_data_mask_a->mn_words); +}; /* for DW8/DW10 from v6+ */ + +void km_nthw_rcp_dual(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_dual, val); +}; + +void km_nthw_rcp_paired(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_paired, val); +}; + +void km_nthw_rcp_el_a(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_el_a, val); +}; + +void km_nthw_rcp_el_b(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_el_b, val); +}; + +void km_nthw_rcp_info_a(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_info_a, val); +}; + +void km_nthw_rcp_info_b(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_info_b, val); +}; + +void km_nthw_rcp_ftm_a(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_ftm_a, val); +}; + +void km_nthw_rcp_ftm_b(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_ftm_b, val); +}; + +void km_nthw_rcp_bank_a(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_bank_a, val); +}; + +void km_nthw_rcp_bank_b(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_bank_b, val); +}; + +void km_nthw_rcp_kl_a(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_kl_a, val); +}; + +void km_nthw_rcp_kl_b(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_kl_b, val); +}; + +void km_nthw_rcp_keyway_a(const struct km_nthw *p, uint32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_rcp_data_keyway_a, val); +}; + +void km_nthw_rcp_keyway_b(const struct km_nthw *p, uint32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_rcp_data_keyway_b, val); +}; + +void km_nthw_rcp_synergy_mode(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_synergy_mode, val); +}; + +void km_nthw_rcp_dw0_b_dyn(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_dw0_b_dyn, val); +}; + +void km_nthw_rcp_dw0_b_ofs(const struct km_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_dw0_b_ofs, val); +}; + +void km_nthw_rcp_dw2_b_dyn(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_dw2_b_dyn, val); +}; + +void km_nthw_rcp_dw2_b_ofs(const struct km_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_dw2_b_ofs, val); +}; + +void km_nthw_rcp_sw4_b_dyn(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_sw4_b_dyn, val); +}; + +void km_nthw_rcp_sw4_b_ofs(const struct km_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_sw4_b_ofs, val); +}; + +void km_nthw_rcp_sw5_b_dyn(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_sw5_b_dyn, val); +}; + +void km_nthw_rcp_sw5_b_ofs(const struct km_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_sw5_b_ofs, val); +}; + +void km_nthw_rcp_flush(const struct km_nthw *p) +{ + nthw_register_flush(p->mp_rcp_ctrl, 1); + nthw_register_flush(p->mp_rcp_data, 1); +}; + +/* CAM */ +void km_nthw_cam_select(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_addr, val); +}; + +void km_nthw_cam_cnt(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_cnt, val); +}; + +void km_nthw_cam_w0(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_w0, val); +}; + +void km_nthw_cam_w1(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_w1, val); +}; + +void km_nthw_cam_w2(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_w2, val); +}; + +void km_nthw_cam_w3(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_w3, val); +}; + +void km_nthw_cam_w4(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_w4, val); +}; + +void km_nthw_cam_w5(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_w5, val); +}; + +void km_nthw_cam_ft0(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_ft0, val); +}; + +void km_nthw_cam_ft1(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_ft1, val); +}; + +void km_nthw_cam_ft2(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_ft2, val); +}; + +void km_nthw_cam_ft3(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_ft3, val); +}; + +void km_nthw_cam_ft4(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_ft4, val); +}; + +void km_nthw_cam_ft5(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_cam_data_ft5, val); +}; + +void km_nthw_cam_flush(const struct km_nthw *p) +{ + nthw_register_flush(p->mp_cam_ctrl, 1); + nthw_register_flush(p->mp_cam_data, 1); +}; + +/* TCAM */ +void km_nthw_tcam_select(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_tcam_addr, val); +}; + +void km_nthw_tcam_cnt(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_tcam_cnt, val); +}; + +void km_nthw_tcam_t(const struct km_nthw *p, uint32_t *val) +{ + nthw_field_set_val(p->mp_tcam_data_t, val, 3); +}; + +void km_nthw_tcam_flush(const struct km_nthw *p) +{ + nthw_register_flush(p->mp_tcam_ctrl, 1); + nthw_register_flush(p->mp_tcam_data, 1); +}; + +/* TCI */ +void km_nthw_tci_select(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_tci_addr, val); +}; + +void km_nthw_tci_cnt(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_tci_cnt, val); +}; + +void km_nthw_tci_color(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_tci_data_color, val); +}; + +void km_nthw_tci_ft(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_tci_data_ft, val); +}; + +void km_nthw_tci_flush(const struct km_nthw *p) +{ + nthw_register_flush(p->mp_tci_ctrl, 1); + nthw_register_flush(p->mp_tci_data, 1); +}; + +/* TCQ */ +void km_nthw_tcq_select(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_tcq_addr, val); +}; + +void km_nthw_tcq_cnt(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_tcq_cnt, val); +}; + +void km_nthw_tcq_bank_mask(const struct km_nthw *p, uint32_t val) +{ + CHECK_AND_SET_VALUE(p->mp_tcq_data_bank_mask, val); +}; + +void km_nthw_tcq_qual(const struct km_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_tcq_data_qual, val); +}; + +void km_nthw_tcq_flush(const struct km_nthw *p) +{ + nthw_register_flush(p->mp_tcq_ctrl, 1); + nthw_register_flush(p->mp_tcq_data, 1); +}; diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_km.h b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_km.h new file mode 100644 index 0000000000..510aaaae98 --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_km.h @@ -0,0 +1,214 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __FLOW_NTHW_KM_H__ +#define __FLOW_NTHW_KM_H__ + +#include + +#include "nthw_fpga_model.h" + +struct km_nthw; + +typedef struct km_nthw km_nthw_t; + +struct km_nthw *km_nthw_new(void); +void km_nthw_delete(struct km_nthw *p); +int km_nthw_init(struct km_nthw *p, nthw_fpga_t *p_fpga, int n_instance); + +int km_nthw_setup(struct km_nthw *p, int n_idx, int n_idx_cnt); +void km_nthw_set_debug_mode(struct km_nthw *p, unsigned int n_debug_mode); + +/* RCP initial v3 */ +void km_nthw_rcp_select(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_cnt(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_qw0_dyn(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_qw0_ofs(const struct km_nthw *p, int32_t val); +void km_nthw_rcp_qw0_sel_a(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_qw0_sel_b(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_qw4_dyn(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_qw4_ofs(const struct km_nthw *p, int32_t val); +void km_nthw_rcp_qw4_sel_a(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_qw4_sel_b(const struct km_nthw *p, uint32_t val); +/* subst in v6 */ +void km_nthw_rcp_dw8_dyn(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_dw8_ofs(const struct km_nthw *p, int32_t val); +void km_nthw_rcp_dw8_sel_a(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_dw8_sel_b(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_dw10_dyn(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_dw10_ofs(const struct km_nthw *p, int32_t val); +void km_nthw_rcp_dw10_sel_a(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_dw10_sel_b(const struct km_nthw *p, uint32_t val); + +void km_nthw_rcp_swx_cch(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_swx_sel_a(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_swx_sel_b(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_mask_da(const struct km_nthw *p, const uint32_t *val); +void km_nthw_rcp_mask_b(const struct km_nthw *p, const uint32_t *val); +void km_nthw_rcp_dual(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_paired(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_el_a(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_el_b(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_info_a(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_info_b(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_ftm_a(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_ftm_b(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_bank_a(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_bank_b(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_kl_a(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_kl_b(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_keyway_a(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_keyway_b(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_synergy_mode(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_dw0_b_dyn(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_dw0_b_ofs(const struct km_nthw *p, int32_t val); +void km_nthw_rcp_dw2_b_dyn(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_dw2_b_ofs(const struct km_nthw *p, int32_t val); +void km_nthw_rcp_sw4_b_dyn(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_sw4_b_ofs(const struct km_nthw *p, int32_t val); +void km_nthw_rcp_sw5_b_dyn(const struct km_nthw *p, uint32_t val); +void km_nthw_rcp_sw5_b_ofs(const struct km_nthw *p, int32_t val); +void km_nthw_rcp_flush(const struct km_nthw *p); +/* CAM */ +void km_nthw_cam_select(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_cnt(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_w0(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_w1(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_w2(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_w3(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_w4(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_w5(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_ft0(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_ft1(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_ft2(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_ft3(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_ft4(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_ft5(const struct km_nthw *p, uint32_t val); +void km_nthw_cam_flush(const struct km_nthw *p); +/* TCAM */ +void km_nthw_tcam_select(const struct km_nthw *p, uint32_t val); +void km_nthw_tcam_cnt(const struct km_nthw *p, uint32_t val); +void km_nthw_tcam_t(const struct km_nthw *p, uint32_t *val); +void km_nthw_tcam_flush(const struct km_nthw *p); +/* TCI */ +void km_nthw_tci_select(const struct km_nthw *p, uint32_t val); +void km_nthw_tci_cnt(const struct km_nthw *p, uint32_t val); +void km_nthw_tci_color(const struct km_nthw *p, uint32_t val); +void km_nthw_tci_ft(const struct km_nthw *p, uint32_t val); +void km_nthw_tci_flush(const struct km_nthw *p); +/* TCQ */ +void km_nthw_tcq_select(const struct km_nthw *p, uint32_t val); +void km_nthw_tcq_cnt(const struct km_nthw *p, uint32_t val); +void km_nthw_tcq_bank_mask(const struct km_nthw *p, uint32_t val); +void km_nthw_tcq_qual(const struct km_nthw *p, uint32_t val); + +void km_nthw_tcq_flush(const struct km_nthw *p); + +struct km_nthw { + uint8_t m_physical_adapter_no; + nthw_fpga_t *mp_fpga; + + nthw_module_t *m_km; + + nthw_register_t *mp_rcp_ctrl; + nthw_field_t *mp_rcp_addr; + nthw_field_t *mp_rcp_cnt; + nthw_register_t *mp_rcp_data; + nthw_field_t *mp_rcp_data_qw0_dyn; + nthw_field_t *mp_rcp_data_qw0_ofs; + nthw_field_t *mp_rcp_data_qw0_sel_a; + nthw_field_t *mp_rcp_data_qw0_sel_b; + nthw_field_t *mp_rcp_data_qw4_dyn; + nthw_field_t *mp_rcp_data_qw4_ofs; + nthw_field_t *mp_rcp_data_qw4_sel_a; + nthw_field_t *mp_rcp_data_qw4_sel_b; + nthw_field_t *mp_rcp_data_sw8_dyn; + nthw_field_t *mp_rcp_data_sw8_ofs; + nthw_field_t *mp_rcp_data_sw8_sel_a; + nthw_field_t *mp_rcp_data_sw8_sel_b; + nthw_field_t *mp_rcp_data_sw9_dyn; + nthw_field_t *mp_rcp_data_sw9_ofs; + nthw_field_t *mp_rcp_data_sw9_sel_a; + nthw_field_t *mp_rcp_data_sw9_sel_b; + + nthw_field_t *mp_rcp_data_dw8_dyn; /* substituted Sw from v6+ */ + nthw_field_t *mp_rcp_data_dw8_ofs; /* substituted Sw from v6+ */ + nthw_field_t *mp_rcp_data_dw8_sel_a; /* substituted Sw from v6+ */ + nthw_field_t *mp_rcp_data_dw8_sel_b; /* substituted Sw from v6+ */ + nthw_field_t *mp_rcp_data_dw10_dyn; /* substituted Sw from v6+ */ + nthw_field_t *mp_rcp_data_dw10_ofs; /* substituted Sw from v6+ */ + nthw_field_t *mp_rcp_data_dw10_sel_a; /* substituted Sw from v6+ */ + nthw_field_t *mp_rcp_data_dw10_sel_b; /* substituted Sw from v6+ */ + + nthw_field_t *mp_rcp_data_swx_ovs_sb; + nthw_field_t *mp_rcp_data_swx_cch; + nthw_field_t *mp_rcp_data_swx_sel_a; + nthw_field_t *mp_rcp_data_swx_sel_b; + nthw_field_t *mp_rcp_data_mask_a; + nthw_field_t *mp_rcp_data_mask_b; + nthw_field_t *mp_rcp_data_dual; + nthw_field_t *mp_rcp_data_paired; + nthw_field_t *mp_rcp_data_el_a; + nthw_field_t *mp_rcp_data_el_b; + nthw_field_t *mp_rcp_data_info_a; + nthw_field_t *mp_rcp_data_info_b; + nthw_field_t *mp_rcp_data_ftm_a; + nthw_field_t *mp_rcp_data_ftm_b; + nthw_field_t *mp_rcp_data_bank_a; + nthw_field_t *mp_rcp_data_bank_b; + nthw_field_t *mp_rcp_data_kl_a; + nthw_field_t *mp_rcp_data_kl_b; + nthw_field_t *mp_rcp_data_flow_set; + nthw_field_t *mp_rcp_data_keyway_a; + nthw_field_t *mp_rcp_data_keyway_b; + nthw_field_t *mp_rcp_data_synergy_mode; + nthw_field_t *mp_rcp_data_dw0_b_dyn; + nthw_field_t *mp_rcp_data_dw0_b_ofs; + nthw_field_t *mp_rcp_data_dw2_b_dyn; + nthw_field_t *mp_rcp_data_dw2_b_ofs; + nthw_field_t *mp_rcp_data_sw4_b_dyn; + nthw_field_t *mp_rcp_data_sw4_b_ofs; + nthw_field_t *mp_rcp_data_sw5_b_dyn; + nthw_field_t *mp_rcp_data_sw5_b_ofs; + + nthw_register_t *mp_cam_ctrl; + nthw_field_t *mp_cam_addr; + nthw_field_t *mp_cam_cnt; + nthw_register_t *mp_cam_data; + nthw_field_t *mp_cam_data_w0; + nthw_field_t *mp_cam_data_w1; + nthw_field_t *mp_cam_data_w2; + nthw_field_t *mp_cam_data_w3; + nthw_field_t *mp_cam_data_w4; + nthw_field_t *mp_cam_data_w5; + nthw_field_t *mp_cam_data_ft0; + nthw_field_t *mp_cam_data_ft1; + nthw_field_t *mp_cam_data_ft2; + nthw_field_t *mp_cam_data_ft3; + nthw_field_t *mp_cam_data_ft4; + nthw_field_t *mp_cam_data_ft5; + + nthw_register_t *mp_tcam_ctrl; + nthw_field_t *mp_tcam_addr; + nthw_field_t *mp_tcam_cnt; + nthw_register_t *mp_tcam_data; + nthw_field_t *mp_tcam_data_t; + + nthw_register_t *mp_tci_ctrl; + nthw_field_t *mp_tci_addr; + nthw_field_t *mp_tci_cnt; + nthw_register_t *mp_tci_data; + nthw_field_t *mp_tci_data_color; + nthw_field_t *mp_tci_data_ft; + + nthw_register_t *mp_tcq_ctrl; + nthw_field_t *mp_tcq_addr; + nthw_field_t *mp_tcq_cnt; + nthw_register_t *mp_tcq_data; + nthw_field_t *mp_tcq_data_bank_mask; + nthw_field_t *mp_tcq_data_qual; +}; + +#endif /* __FLOW_NTHW_KM_H__ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h index d4ccc5157d..7d48e4012e 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h @@ -21,6 +21,7 @@ #define MOD_HIF (0x7815363UL) #define MOD_I2CM (0x93bc7780UL) #define MOD_IIC (0x7629cddbUL) +#define MOD_KM (0xcfbd9dbeUL) #define MOD_MAC_PCS (0x7abe24c7UL) #define MOD_PCIE3 (0xfbc48c18UL) #define MOD_PCI_RD_TG (0x9ad9eed2UL) diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h index dad498256f..96676bf8d4 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h @@ -20,6 +20,7 @@ #include "nthw_fpga_reg_defs_hif.h" #include "nthw_fpga_reg_defs_i2cm.h" #include "nthw_fpga_reg_defs_iic.h" +#include "nthw_fpga_reg_defs_km.h" #include "nthw_fpga_reg_defs_mac_pcs.h" #include "nthw_fpga_reg_defs_pcie3.h" #include "nthw_fpga_reg_defs_pci_rd_tg.h" diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h new file mode 100644 index 0000000000..03273dced0 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h @@ -0,0 +1,126 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Napatech A/S + */ + +/* + * nthw_fpga_reg_defs_km.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_KM_ +#define _NTHW_FPGA_REG_DEFS_KM_ + +/* KM */ +#define NTHW_MOD_KM (0xcfbd9dbeUL) +#define KM_CAM_CTRL (0x601dcc08UL) +#define KM_CAM_CTRL_ADR (0xee5e10b0UL) +#define KM_CAM_CTRL_CNT (0xfe568961UL) +#define KM_CAM_DATA (0xcfcc4e11UL) +#define KM_CAM_DATA_FT0 (0x138589ccUL) +#define KM_CAM_DATA_FT1 (0x6482b95aUL) +#define KM_CAM_DATA_FT2 (0xfd8be8e0UL) +#define KM_CAM_DATA_FT3 (0x8a8cd876UL) +#define KM_CAM_DATA_FT4 (0x14e84dd5UL) +#define KM_CAM_DATA_FT5 (0x63ef7d43UL) +#define KM_CAM_DATA_W0 (0xff7d6c5fUL) +#define KM_CAM_DATA_W1 (0x887a5cc9UL) +#define KM_CAM_DATA_W2 (0x11730d73UL) +#define KM_CAM_DATA_W3 (0x66743de5UL) +#define KM_CAM_DATA_W4 (0xf810a846UL) +#define KM_CAM_DATA_W5 (0x8f1798d0UL) +#define KM_RCP_CTRL (0xf8dbfdd1UL) +#define KM_RCP_CTRL_ADR (0xf3df02baUL) +#define KM_RCP_CTRL_CNT (0xe3d79b6bUL) +#define KM_RCP_DATA (0x570a7fc8UL) +#define KM_RCP_DATA_BANK_A (0x7fd7bd1UL) +#define KM_RCP_DATA_BANK_B (0x9ef42a6bUL) +#define KM_RCP_DATA_DUAL (0x428e6b23UL) +#define KM_RCP_DATA_DW0_B_DYN (0x342bde5aUL) +#define KM_RCP_DATA_DW0_B_OFS (0x962253fcUL) +#define KM_RCP_DATA_DW10_DYN (0x54eccf30UL) +#define KM_RCP_DATA_DW10_OFS (0xf6e54296UL) +#define KM_RCP_DATA_DW10_SEL_A (0x6237e887UL) +#define KM_RCP_DATA_DW10_SEL_B (0xfb3eb93dUL) +#define KM_RCP_DATA_DW2_B_DYN (0xa3b4cf73UL) +#define KM_RCP_DATA_DW2_B_OFS (0x1bd42d5UL) +#define KM_RCP_DATA_DW8_B_DYN (0x7c4903dUL) +#define KM_RCP_DATA_DW8_B_OFS (0xa5cd1d9bUL) +#define KM_RCP_DATA_DW8_DYN (0x3f6b49f0UL) +#define KM_RCP_DATA_DW8_OFS (0x9d62c456UL) +#define KM_RCP_DATA_DW8_SEL_A (0xad16725bUL) +#define KM_RCP_DATA_DW8_SEL_B (0x341f23e1UL) +#define KM_RCP_DATA_EL_A (0x4335d7dbUL) +#define KM_RCP_DATA_EL_B (0xda3c8661UL) +#define KM_RCP_DATA_FLOW_SET (0x6b56d647UL) +#define KM_RCP_DATA_FTM_A (0xdb75ed61UL) +#define KM_RCP_DATA_FTM_B (0x427cbcdbUL) +#define KM_RCP_DATA_INFO_A (0x2dd79cf0UL) +#define KM_RCP_DATA_INFO_B (0xb4decd4aUL) +#define KM_RCP_DATA_KEYWAY_A (0xd0e5dc89UL) +#define KM_RCP_DATA_KEYWAY_B (0x49ec8d33UL) +#define KM_RCP_DATA_KL_A (0xa3eaa0e8UL) +#define KM_RCP_DATA_KL_B (0x3ae3f152UL) +#define KM_RCP_DATA_MASK_A (0x54d84646UL) +#define KM_RCP_DATA_MASK_B (0xcdd117fcUL) +#define KM_RCP_DATA_PAIRED (0x7847653UL) +#define KM_RCP_DATA_QW0_B_DYN (0xd27cd964UL) +#define KM_RCP_DATA_QW0_B_OFS (0x707554c2UL) +#define KM_RCP_DATA_QW0_DYN (0x3afdb158UL) +#define KM_RCP_DATA_QW0_OFS (0x98f43cfeUL) +#define KM_RCP_DATA_QW0_SEL_A (0x78ae3b02UL) +#define KM_RCP_DATA_QW0_SEL_B (0xe1a76ab8UL) +#define KM_RCP_DATA_QW4_B_DYN (0x2633fd77UL) +#define KM_RCP_DATA_QW4_B_OFS (0x843a70d1UL) +#define KM_RCP_DATA_QW4_DYN (0xcf7d1798UL) +#define KM_RCP_DATA_QW4_OFS (0x6d749a3eUL) +#define KM_RCP_DATA_QW4_SEL_A (0x8ce11f11UL) +#define KM_RCP_DATA_QW4_SEL_B (0x15e84eabUL) +#define KM_RCP_DATA_SW4_B_DYN (0x8c5d5f1UL) +#define KM_RCP_DATA_SW4_B_OFS (0xaacc5857UL) +#define KM_RCP_DATA_SW5_B_DYN (0xaeb2de45UL) +#define KM_RCP_DATA_SW5_B_OFS (0xcbb53e3UL) +#define KM_RCP_DATA_SW8_B_DYN (0xcf65bf85UL) +#define KM_RCP_DATA_SW8_B_OFS (0x6d6c3223UL) +#define KM_RCP_DATA_SW8_DYN (0x9d12ebb0UL) +#define KM_RCP_DATA_SW8_OFS (0x3f1b6616UL) +#define KM_RCP_DATA_SW8_SEL_A (0x65b75de3UL) +#define KM_RCP_DATA_SW8_SEL_B (0xfcbe0c59UL) +#define KM_RCP_DATA_SW9_B_DYN (0x6912b431UL) +#define KM_RCP_DATA_SW9_B_OFS (0xcb1b3997UL) +#define KM_RCP_DATA_SW9_DYN (0xa072c200UL) +#define KM_RCP_DATA_SW9_OFS (0x27b4fa6UL) +#define KM_RCP_DATA_SW9_SEL_A (0xc3c05657UL) +#define KM_RCP_DATA_SW9_SEL_B (0x5ac907edUL) +#define KM_RCP_DATA_SWX_CCH (0x5821d596UL) +#define KM_RCP_DATA_SWX_OVS_SB (0x808773bdUL) +#define KM_RCP_DATA_SWX_SEL_A (0xee011106UL) +#define KM_RCP_DATA_SWX_SEL_B (0x770840bcUL) +#define KM_RCP_DATA_SYNERGY_MODE (0x35a76c4aUL) +#define KM_STATUS (0x2f1f9d13UL) +#define KM_STATUS_TCQ_RDY (0x653553c4UL) +#define KM_TCAM_CTRL (0x18fbc021UL) +#define KM_TCAM_CTRL_ADR (0x6c84a404UL) +#define KM_TCAM_CTRL_CNT (0x7c8c3dd5UL) +#define KM_TCAM_DATA (0xb72a4238UL) +#define KM_TCAM_DATA_T (0xa995a553UL) +#define KM_TCI_CTRL (0x1a6da705UL) +#define KM_TCI_CTRL_ADR (0xc7590d78UL) +#define KM_TCI_CTRL_CNT (0xd75194a9UL) +#define KM_TCI_DATA (0xb5bc251cUL) +#define KM_TCI_DATA_COLOR (0x324017ecUL) +#define KM_TCI_DATA_FT (0x38afba77UL) +#define KM_TCQ_CTRL (0xf5e827f3UL) +#define KM_TCQ_CTRL_ADR (0xf320cc64UL) +#define KM_TCQ_CTRL_CNT (0xe32855b5UL) +#define KM_TCQ_DATA (0x5a39a5eaUL) +#define KM_TCQ_DATA_BANK_MASK (0x97cf4b5aUL) +#define KM_TCQ_DATA_QUAL (0x4422cc93UL) + +#endif /* _NTHW_FPGA_REG_DEFS_KM_ */ + +/* + * Auto-generated file - do *NOT* edit + */