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Signed-off-by: Oleksandr Kolomeiets --- drivers/net/ntnic/include/hw_mod_backend.h | 37 ++++ drivers/net/ntnic/meson.build | 1 + drivers/net/ntnic/nthw/flow_api/flow_api.c | 14 ++ .../nthw/flow_api/hw_mod/hw_mod_backend.c | 1 + .../ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c | 170 ++++++++++++++++++ .../supported/nthw_fpga_9563_055_049_0000.c | 57 +++++- 6 files changed, 279 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c diff --git a/drivers/net/ntnic/include/hw_mod_backend.h b/drivers/net/ntnic/include/hw_mod_backend.h index 6bf651272f..13e0d1731e 100644 --- a/drivers/net/ntnic/include/hw_mod_backend.h +++ b/drivers/net/ntnic/include/hw_mod_backend.h @@ -537,6 +537,42 @@ struct qsl_func_s { struct hw_mod_qsl_v7_s v7; }; }; +enum hw_qsl_e { + /* functions */ + HW_QSL_RCP_PRESET_ALL = 0, + HW_QSL_RCP_COMPARE, + HW_QSL_RCP_FIND, + HW_QSL_QST_PRESET_ALL, + /* fields */ + HW_QSL_RCP_DISCARD = FIELD_START_INDEX, + HW_QSL_RCP_DROP, + HW_QSL_RCP_TBL_LO, + HW_QSL_RCP_TBL_HI, + HW_QSL_RCP_TBL_IDX, + HW_QSL_RCP_TBL_MSK, + HW_QSL_RCP_LR, + HW_QSL_RCP_TSA, + HW_QSL_RCP_VLI, + HW_QSL_QST_QUEUE, + HW_QSL_QST_EN, /* Alias: HW_QSL_QST_QEN */ + HW_QSL_QST_TX_PORT, + HW_QSL_QST_LRE, + HW_QSL_QST_TCI, + HW_QSL_QST_VEN, + HW_QSL_QEN_EN, + HW_QSL_UNMQ_DEST_QUEUE, + HW_QSL_UNMQ_EN, +}; +bool hw_mod_qsl_present(struct flow_api_backend_s *be); +int hw_mod_qsl_alloc(struct flow_api_backend_s *be); +void hw_mod_qsl_free(struct flow_api_backend_s *be); +int hw_mod_qsl_reset(struct flow_api_backend_s *be); +int hw_mod_qsl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); +int hw_mod_qsl_qst_flush(struct flow_api_backend_s *be, int start_idx, int count); +int hw_mod_qsl_qen_flush(struct flow_api_backend_s *be, int start_idx, int count); +int hw_mod_qsl_unmq_flush(struct flow_api_backend_s *be, int start_idx, int count); +int hw_mod_qsl_unmq_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, + uint32_t value); struct slc_lr_func_s { COMMON_FUNC_INFO_S; @@ -721,6 +757,7 @@ struct flow_api_backend_s { struct km_func_s km; struct flm_func_s flm; struct hsh_func_s hsh; + struct qsl_func_s qsl; /* NIC attributes */ unsigned int num_phy_ports; diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 18aafc57f0..02981ef987 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -53,6 +53,7 @@ sources = files( 'nthw/flow_api/hw_mod/hw_mod_flm.c', 'nthw/flow_api/hw_mod/hw_mod_hsh.c', 'nthw/flow_api/hw_mod/hw_mod_km.c', + 'nthw/flow_api/hw_mod/hw_mod_qsl.c', 'nthw/flow_filter/flow_nthw_cat.c', 'nthw/flow_filter/flow_nthw_csu.c', 'nthw/flow_filter/flow_nthw_flm.c', diff --git a/drivers/net/ntnic/nthw/flow_api/flow_api.c b/drivers/net/ntnic/nthw/flow_api/flow_api.c index b43c8fef1a..5d6571310c 100644 --- a/drivers/net/ntnic/nthw/flow_api/flow_api.c +++ b/drivers/net/ntnic/nthw/flow_api/flow_api.c @@ -144,6 +144,14 @@ int flow_delete_eth_dev(struct flow_eth_dev *eth_dev) /* delete all created flows from this device */ pthread_mutex_lock(&ndev->mtx); + /* + * remove unmatched queue if setup in QSL + * remove exception queue setting in QSL UNM + */ + hw_mod_qsl_unmq_set(&ndev->be, HW_QSL_UNMQ_DEST_QUEUE, eth_dev->port, 0); + hw_mod_qsl_unmq_set(&ndev->be, HW_QSL_UNMQ_EN, eth_dev->port, 0); + hw_mod_qsl_unmq_flush(&ndev->be, eth_dev->port, 1); + #ifdef FLOW_DEBUG ndev->be.iface->set_debug_mode(ndev->be.be_dev, FLOW_BACKEND_DEBUG_MODE_NONE); #endif @@ -293,6 +301,12 @@ struct flow_nic_dev *flow_api_create(uint8_t adapter_no, const struct flow_api_b if (init_resource_elements(ndev, RES_HSH_RCP, ndev->be.hsh.nb_rcp)) goto err_exit; + if (init_resource_elements(ndev, RES_QSL_RCP, ndev->be.qsl.nb_rcp_categories)) + goto err_exit; + + if (init_resource_elements(ndev, RES_QSL_QST, ndev->be.qsl.nb_qst_entries)) + goto err_exit; + if (init_resource_elements(ndev, RES_SLC_LR_RCP, ndev->be.max_categories)) goto err_exit; diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c index 3ccc14c4ce..4f16235a67 100644 --- a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c +++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c @@ -21,6 +21,7 @@ static const struct { { "KM", hw_mod_km_alloc, hw_mod_km_free, hw_mod_km_reset, hw_mod_km_present }, { "FLM", hw_mod_flm_alloc, hw_mod_flm_free, hw_mod_flm_reset, hw_mod_flm_present }, { "HSH", hw_mod_hsh_alloc, hw_mod_hsh_free, hw_mod_hsh_reset, hw_mod_hsh_present }, + { "QSL", hw_mod_qsl_alloc, hw_mod_qsl_free, hw_mod_qsl_reset, hw_mod_qsl_present }, }; #define MOD_COUNT (ARRAY_SIZE(module)) diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c new file mode 100644 index 0000000000..f69717cf84 --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c @@ -0,0 +1,170 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include +#include + +#include "hw_mod_backend.h" + +#define _MOD_ "QSL" +#define _VER_ be->qsl.ver + +#define QSL_QEN_ENTRIES 32 +#define QSL_QNMQ_ENTRIES 256 + +bool hw_mod_qsl_present(struct flow_api_backend_s *be) +{ + return be->iface->get_qsl_present(be->be_dev); +} + +int hw_mod_qsl_alloc(struct flow_api_backend_s *be) +{ + int nb; + _VER_ = be->iface->get_qsl_version(be->be_dev); + NT_LOG(DBG, FILTER, "QSL MODULE VERSION %i.%i\n", VER_MAJOR(_VER_), VER_MINOR(_VER_)); + + nb = be->iface->get_nb_qsl_categories(be->be_dev); + + if (nb <= 0) + return COUNT_ERROR(qsl_categories); + + be->qsl.nb_rcp_categories = (uint32_t)nb; + + nb = be->iface->get_nb_qsl_qst_entries(be->be_dev); + + if (nb <= 0) + return COUNT_ERROR(qsl_qst_entries); + + be->qsl.nb_qst_entries = (uint32_t)nb; + + switch (_VER_) { + case 7: + if (!callocate_mod((struct common_func_s *)&be->qsl, 4, &be->qsl.v7.rcp, + be->qsl.nb_rcp_categories, sizeof(struct qsl_v7_rcp_s), + &be->qsl.v7.qst, be->qsl.nb_qst_entries, + sizeof(struct qsl_v7_qst_s), &be->qsl.v7.qen, QSL_QEN_ENTRIES, + sizeof(struct qsl_v7_qen_s), &be->qsl.v7.unmq, QSL_QNMQ_ENTRIES, + sizeof(struct qsl_v7_unmq_s))) + return -1; + + break; + + /* end case 7 */ + default: + return UNSUP_VER; + } + + return 0; +} + +void hw_mod_qsl_free(struct flow_api_backend_s *be) +{ + if (be->qsl.base) { + free(be->qsl.base); + be->qsl.base = NULL; + } +} + +int hw_mod_qsl_reset(struct flow_api_backend_s *be) +{ + /* Zero entire cache area */ + zero_module_cache((struct common_func_s *)(&be->qsl)); + + NT_LOG(DBG, FILTER, "INIT QSL RCP\n"); + hw_mod_qsl_rcp_flush(be, 0, ALL_ENTRIES); + + NT_LOG(DBG, FILTER, "INIT QSL QST\n"); + hw_mod_qsl_qst_flush(be, 0, ALL_ENTRIES); + + NT_LOG(DBG, FILTER, "INIT QSL QEN\n"); + hw_mod_qsl_qen_flush(be, 0, ALL_ENTRIES); + + NT_LOG(DBG, FILTER, "INIT QSL UNMQ\n"); + be->iface->qsl_unmq_flush(be->be_dev, &be->qsl, 0, 256); + + return 0; +} + +int hw_mod_qsl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count) +{ + if (count == ALL_ENTRIES) + count = be->qsl.nb_rcp_categories; + + if ((unsigned int)(start_idx + count) > be->qsl.nb_rcp_categories) + return INDEX_TOO_LARGE; + + return be->iface->qsl_rcp_flush(be->be_dev, &be->qsl, start_idx, count); +} + +int hw_mod_qsl_qst_flush(struct flow_api_backend_s *be, int start_idx, int count) +{ + if (count == ALL_ENTRIES) + count = be->qsl.nb_qst_entries; + + if ((unsigned int)(start_idx + count) > be->qsl.nb_qst_entries) + return INDEX_TOO_LARGE; + + return be->iface->qsl_qst_flush(be->be_dev, &be->qsl, start_idx, count); +} + +int hw_mod_qsl_qen_flush(struct flow_api_backend_s *be, int start_idx, int count) +{ + if (count == ALL_ENTRIES) + count = QSL_QEN_ENTRIES; + + if ((start_idx + count) > QSL_QEN_ENTRIES) + return INDEX_TOO_LARGE; + + return be->iface->qsl_qen_flush(be->be_dev, &be->qsl, start_idx, count); +} + +int hw_mod_qsl_unmq_flush(struct flow_api_backend_s *be, int start_idx, int count) +{ + if (count == ALL_ENTRIES) + count = QSL_QNMQ_ENTRIES; + + if ((start_idx + count) > QSL_QNMQ_ENTRIES) + return INDEX_TOO_LARGE; + + return be->iface->qsl_unmq_flush(be->be_dev, &be->qsl, start_idx, count); +} + +static int hw_mod_qsl_unmq_mod(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, + uint32_t *value, int get) +{ + if (index >= QSL_QNMQ_ENTRIES) + return INDEX_TOO_LARGE; + + switch (_VER_) { + case 7: + switch (field) { + case HW_QSL_UNMQ_DEST_QUEUE: + GET_SET(be->qsl.v7.unmq[index].dest_queue, value); + break; + + case HW_QSL_UNMQ_EN: + GET_SET(be->qsl.v7.unmq[index].en, value); + break; + + default: + return UNSUP_FIELD; + } + + break; + + /* end case 7 */ + default: + return UNSUP_VER; + } + + return 0; +} + +int hw_mod_qsl_unmq_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, + uint32_t value) +{ + return hw_mod_qsl_unmq_mod(be, field, index, &value, 0); +} diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c index 4317da8094..7eeb210b80 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c @@ -1297,6 +1297,60 @@ static nthw_fpga_register_init_s pci_wr_tg_registers[] = { { PCI_WR_TG_TG_WR_RUN, 4, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wr_run_fields }, }; +static nthw_fpga_field_init_s qsl_qen_ctrl_fields[] = { + { QSL_QEN_CTRL_ADR, 5, 0, 0x0000 }, + { QSL_QEN_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_qen_data_fields[] = { + { QSL_QEN_DATA_EN, 4, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_qst_ctrl_fields[] = { + { QSL_QST_CTRL_ADR, 12, 0, 0x0000 }, + { QSL_QST_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_qst_data_fields[] = { + { QSL_QST_DATA_LRE, 1, 9, 0x0000 }, { QSL_QST_DATA_QEN, 1, 7, 0x0000 }, + { QSL_QST_DATA_QUEUE, 7, 0, 0x0000 }, { QSL_QST_DATA_TCI, 16, 10, 0x0000 }, + { QSL_QST_DATA_TX_PORT, 1, 8, 0x0000 }, { QSL_QST_DATA_VEN, 1, 26, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_rcp_ctrl_fields[] = { + { QSL_RCP_CTRL_ADR, 5, 0, 0x0000 }, + { QSL_RCP_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_rcp_data_fields[] = { + { QSL_RCP_DATA_DISCARD, 1, 0, 0x0000 }, { QSL_RCP_DATA_DROP, 2, 1, 0x0000 }, + { QSL_RCP_DATA_LR, 2, 51, 0x0000 }, { QSL_RCP_DATA_TBL_HI, 12, 15, 0x0000 }, + { QSL_RCP_DATA_TBL_IDX, 12, 27, 0x0000 }, { QSL_RCP_DATA_TBL_LO, 12, 3, 0x0000 }, + { QSL_RCP_DATA_TBL_MSK, 12, 39, 0x0000 }, { QSL_RCP_DATA_TSA, 1, 53, 0x0000 }, + { QSL_RCP_DATA_VLI, 2, 54, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_unmq_ctrl_fields[] = { + { QSL_UNMQ_CTRL_ADR, 1, 0, 0x0000 }, + { QSL_UNMQ_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_unmq_data_fields[] = { + { QSL_UNMQ_DATA_DEST_QUEUE, 7, 0, 0x0000 }, + { QSL_UNMQ_DATA_EN, 1, 7, 0x0000 }, +}; + +static nthw_fpga_register_init_s qsl_registers[] = { + { QSL_QEN_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_qen_ctrl_fields }, + { QSL_QEN_DATA, 5, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, qsl_qen_data_fields }, + { QSL_QST_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_qst_ctrl_fields }, + { QSL_QST_DATA, 3, 27, NTHW_FPGA_REG_TYPE_WO, 0, 6, qsl_qst_data_fields }, + { QSL_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_rcp_ctrl_fields }, + { QSL_RCP_DATA, 1, 56, NTHW_FPGA_REG_TYPE_WO, 0, 9, qsl_rcp_data_fields }, + { QSL_UNMQ_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_unmq_ctrl_fields }, + { QSL_UNMQ_DATA, 7, 8, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_unmq_data_fields }, +}; + static nthw_fpga_field_init_s rac_dbg_ctrl_fields[] = { { RAC_DBG_CTRL_C, 32, 0, 0x0000 }, }; @@ -1456,6 +1510,7 @@ static nthw_fpga_module_init_s fpga_modules[] = { MOD_PCI_WR_TG, 0, MOD_PCI_WR_TG, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 2304, 7, pci_wr_tg_registers }, + { MOD_QSL, 0, MOD_QSL, 0, 7, NTHW_FPGA_BUS_TYPE_RAB1, 1792, 8, qsl_registers }, { MOD_RAC, 0, MOD_RAC, 3, 0, NTHW_FPGA_BUS_TYPE_PCI, 8192, 14, rac_registers }, { MOD_RST9563, 0, MOD_RST9563, 0, 5, NTHW_FPGA_BUS_TYPE_RAB0, 1024, 5, rst9563_registers }, }; @@ -1617,5 +1672,5 @@ static nthw_fpga_prod_param_s product_parameters[] = { }; nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000 = { - 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 18, fpga_modules, + 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 19, fpga_modules, };