@@ -24,8 +24,10 @@
#include "bnxt_util.h"
#include "tf_core.h"
+#include "tfc.h"
#include "bnxt_ulp.h"
#include "bnxt_tf_common.h"
+#include "bnxt_mpc.h"
#include "bnxt_vnic.h"
/* Vendor ID */
@@ -1034,6 +1036,7 @@ struct bnxt {
struct bnxt_ring_stats_ext *prev_tx_ring_stats_ext;
struct bnxt_vnic_queue_db vnic_queue_db;
+ struct bnxt_mpc *mpc;
#define BNXT_MAX_MC_ADDRS ((bp)->max_mcast_addr)
struct rte_ether_addr *mcast_addr_list;
rte_iova_t mc_list_dma_addr;
@@ -8,6 +8,7 @@
#include <stdbool.h>
#include <rte_io.h>
+#include <rte_version.h>
#include "hsi_struct_def_dpdk.h"
struct bnxt_db_info;
@@ -15,6 +16,10 @@ struct bnxt_db_info;
#define CMP_TYPE(cmp) \
(((struct cmpl_base *)cmp)->type & CMPL_BASE_TYPE_MASK)
+#define CMPL_VALID(cmp, v) \
+ (!!(rte_le_to_cpu_32(((struct cmpl_base *)(cmp))->info3_v) & \
+ CMPL_BASE_V) == !(v))
+
/* Get completion length from completion type, in 16-byte units. */
#define CMP_LEN(cmp_type) (((cmp_type) & 1) + 1)
@@ -28,6 +33,14 @@ struct bnxt_db_info;
#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
+#define NEXT_CMPL(cpr, idx, v, inc) do { \
+ (idx) += (inc); \
+ if (unlikely((idx) >= (cpr)->cp_ring_struct->ring_size)) { \
+ (v) = !(v); \
+ (idx) = 0; \
+ } \
+} while (0)
+
#define B_CP_DB_REARM(cpr, raw_cons) \
rte_write32((DB_CP_REARM_FLAGS | \
DB_RING_IDX(&((cpr)->cp_db), raw_cons)), \
@@ -74,6 +87,8 @@ struct bnxt_cp_ring_info {
uint32_t hw_stats_ctx_id;
struct bnxt_ring *cp_ring_struct;
+ bool valid;
+ uint32_t epoch;
};
#define RX_CMP_L2_ERRORS \
@@ -104,10 +119,13 @@ bool bnxt_is_recovery_enabled(struct bnxt *bp);
bool bnxt_is_primary_func(struct bnxt *bp);
void bnxt_stop_rxtx(struct rte_eth_dev *eth_dev);
+#if (RTE_VERSION_NUM(21, 8, 0, 0) < RTE_VERSION)
+void bnxt_start_rxtx(struct rte_eth_dev *eth_dev);
+#endif
/**
* Check validity of a completion ring entry. If the entry is valid, include a
- * C11 rte_memory_order_acquire fence to ensure that subsequent loads of fields in the
+ * C11 __ATOMIC_ACQUIRE fence to ensure that subsequent loads of fields in the
* completion are not hoisted by the compiler or by the CPU to come before the
* loading of the "valid" field.
*
@@ -124,13 +142,13 @@ void bnxt_stop_rxtx(struct rte_eth_dev *eth_dev);
static __rte_always_inline bool
bnxt_cpr_cmp_valid(const void *cmpl, uint32_t raw_cons, uint32_t ring_size)
{
- const struct cmpl_base *c = cmpl;
+ const struct cmpl_base *c = (const struct cmpl_base *)cmpl;
bool expected, valid;
expected = !(raw_cons & ring_size);
valid = !!(rte_le_to_cpu_32(c->info3_v) & CMPL_BASE_V);
if (valid == expected) {
- rte_atomic_thread_fence(rte_memory_order_acquire);
+ rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
return true;
}
return false;
@@ -2370,7 +2370,7 @@ int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
return rc;
}
-static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
+int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
{
int rc;
struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
@@ -7449,6 +7449,49 @@ int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
return rc;
}
+int bnxt_hwrm_func_cfg_mpc(struct bnxt *bp, uint8_t mpc_chnls_msk, bool enable)
+{
+ struct hwrm_func_cfg_input req = {0};
+ struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
+ int rc;
+ uint16_t mpc_chnls = 0;
+
+ HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
+ req.fid = rte_cpu_to_le_16(0xffff);
+ req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS);
+ if (enable) {
+ if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TCE))
+ mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE;
+ if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RCE))
+ mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE;
+ if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TE_CFA))
+ mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE;
+ if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RE_CFA))
+ mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE;
+ if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_PRIMATE))
+ mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE;
+ } else {
+ if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TCE))
+ mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE;
+ if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RCE))
+ mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE;
+ if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TE_CFA))
+ mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE;
+ if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RE_CFA))
+ mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE;
+ if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_PRIMATE))
+ mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE;
+ }
+ req.mpc_chnls = rte_cpu_to_le_16(mpc_chnls);
+
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT();
+ HWRM_UNLOCK();
+
+ return rc;
+}
+
int
bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
@@ -7471,3 +7514,41 @@ bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
return rc;
}
+
+int bnxt_hwrm_tf_oem_cmd(struct bnxt *bp,
+ uint32_t *in,
+ uint16_t in_len,
+ uint32_t *out,
+ uint16_t out_len)
+{
+ struct hwrm_oem_cmd_output *resp = bp->hwrm_cmd_resp_addr;
+ struct hwrm_oem_cmd_input req = {0};
+ int rc = 0;
+
+ if (!BNXT_VF(bp)) {
+ PMD_DRV_LOG(DEBUG, "Not a VF. Command not supported\n");
+ return -ENOTSUP;
+ }
+
+ HWRM_PREP(&req, HWRM_OEM_CMD, BNXT_USE_CHIMP_MB);
+
+ req.oem_id = rte_cpu_to_le_32(0x14e4);
+ req.naming_authority =
+ HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG;
+ req.message_family =
+ HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW;
+ memcpy(req.oem_data, in, in_len);
+
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT();
+ if (resp->oem_id == 0x14e4 &&
+ resp->naming_authority ==
+ HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG &&
+ resp->message_family ==
+ HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW)
+ memcpy(out, resp->oem_data, out_len);
+ HWRM_UNLOCK();
+
+ return rc;
+}
@@ -367,6 +367,10 @@ int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr);
void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index);
int bnxt_alloc_hwrm_tx_ring(struct bnxt *bp, int queue_index);
int bnxt_hwrm_config_host_mtu(struct bnxt *bp);
+int bnxt_hwrm_func_cfg_mpc(struct bnxt *bp,
+ uint8_t mpc_chnls_msk,
+ bool enable);
+int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr);
int bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);
int bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);
int bnxt_hwrm_func_backing_store_qcaps_v2(struct bnxt *bp);
@@ -375,4 +379,9 @@ int bnxt_hwrm_func_backing_store_cfg_v2(struct bnxt *bp,
int bnxt_hwrm_func_backing_store_types_count(struct bnxt *bp);
int bnxt_hwrm_func_backing_store_ctx_alloc(struct bnxt *bp, uint16_t types);
int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp);
+int bnxt_hwrm_tf_oem_cmd(struct bnxt *bp,
+ uint32_t *in,
+ uint16_t in_len,
+ uint32_t *out,
+ uint16_t out_len);
#endif
new file mode 100644
@@ -0,0 +1,853 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include <inttypes.h>
+#include <rte_malloc.h>
+#include <unistd.h>
+
+#include "bnxt.h"
+#include "bnxt_ring.h"
+#include "bnxt_mpc.h"
+#include "bnxt_hwrm.h"
+#include "hsi_struct_def_dpdk.h"
+
+/*#define MPC_DEBUG 1*/
+
+#define BNXT_MPC_BP_SIZE 16
+
+static int bnxt_mpc_chnls_enable(struct bnxt *bp)
+{
+ struct bnxt_mpc *mpc = bp->mpc;
+ uint8_t mpc_chnl_msk = 0;
+ int i, rc;
+
+ if (!mpc)
+ return -EINVAL;
+
+ for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) {
+ if (!(mpc->mpc_chnls_cap & (1 << i)))
+ continue;
+ mpc_chnl_msk |= (1 << i);
+ }
+ mpc->mpc_chnls_en = mpc_chnl_msk;
+
+ if (!BNXT_PF(bp))
+ return 0;
+
+ rc = bnxt_hwrm_func_cfg_mpc(bp, mpc_chnl_msk, true);
+ if (rc != 0) {
+ mpc->mpc_chnls_en = 0;
+ PMD_DRV_LOG(ERR, "MPC chnls enabling failed rc:%d\n", rc);
+ }
+
+ return rc;
+}
+
+static int bnxt_mpc_chnls_disable(struct bnxt *bp)
+{
+ struct bnxt_mpc *mpc = bp->mpc;
+ uint8_t mpc_chnl_msk = 0;
+ int i, rc;
+
+ if (!mpc)
+ return -EINVAL;
+ mpc->mpc_chnls_en = 0;
+
+ if (!BNXT_PF(bp))
+ return 0;
+
+ for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) {
+ if (!(mpc->mpc_chnls_en & (1 << i)))
+ continue;
+ mpc_chnl_msk |= (1 << i);
+ }
+ rc = bnxt_hwrm_func_cfg_mpc(bp, mpc_chnl_msk, false);
+ if (rc != 0)
+ PMD_DRV_LOG(ERR, "MPC chnls disabling failed rc:%d\n", rc);
+
+ return rc;
+}
+
+static void bnxt_mpc_queue_release_mbufs(struct bnxt_mpc_txq *mpc_queue)
+{
+ struct bnxt_sw_mpc_bd *sw_ring;
+ uint16_t i;
+
+ if (!mpc_queue)
+ return;
+
+ sw_ring = mpc_queue->mpc_ring->mpc_buf_ring;
+ if (!sw_ring)
+ return;
+
+ for (i = 0; i < mpc_queue->mpc_ring->mpc_ring_struct->ring_size; i++) {
+ if (sw_ring[i].mpc_mbuf) {
+ rte_free(sw_ring[i].mpc_mbuf);
+ sw_ring[i].mpc_mbuf = NULL;
+ }
+ }
+}
+
+static void bnxt_mpc_queue_release_one(struct bnxt_mpc_txq *mpc_queue)
+{
+ if (!mpc_queue)
+ return;
+
+ if (is_bnxt_in_error(mpc_queue->bp))
+ return;
+ /* Free MPC ring HW descriptors */
+ bnxt_mpc_queue_release_mbufs(mpc_queue);
+ bnxt_free_ring(mpc_queue->mpc_ring->mpc_ring_struct);
+ /* Free MPC completion ring HW descriptors */
+ bnxt_free_ring(mpc_queue->cp_ring->cp_ring_struct);
+
+ rte_memzone_free(mpc_queue->mz);
+ mpc_queue->mz = NULL;
+
+ rte_free(mpc_queue->free);
+ rte_free(mpc_queue);
+}
+
+static void bnxt_mpc_ring_free_one(struct bnxt_mpc_txq *mpc_queue)
+{
+ struct bnxt_cp_ring_info *cpr;
+ struct bnxt_mpc_ring_info *mpr;
+ struct bnxt_ring *ring;
+
+ if (!mpc_queue)
+ return;
+
+ if (is_bnxt_in_error(mpc_queue->bp))
+ return;
+
+ mpr = mpc_queue->mpc_ring;
+ ring = mpr->mpc_ring_struct;
+ if (ring->fw_ring_id == INVALID_HW_RING_ID)
+ return;
+
+ cpr = mpc_queue->cp_ring;
+ bnxt_hwrm_ring_free(mpc_queue->bp, ring,
+ HWRM_RING_FREE_INPUT_RING_TYPE_TX,
+ cpr->cp_ring_struct->fw_ring_id);
+ ring->fw_ring_id = INVALID_HW_RING_ID;
+ memset(mpr->mpc_desc_ring, 0,
+ mpr->mpc_ring_struct->ring_size * sizeof(*mpr->mpc_desc_ring));
+ memset(mpr->mpc_buf_ring, 0,
+ mpr->mpc_ring_struct->ring_size * sizeof(*mpr->mpc_buf_ring));
+ mpr->raw_prod = 0;
+ mpr->raw_cons = 0;
+
+ bnxt_free_cp_ring(mpc_queue->bp, cpr);
+ bnxt_hwrm_stat_ctx_free(mpc_queue->bp, cpr);
+}
+
+int bnxt_mpc_close(struct bnxt *bp)
+{
+ int i, rc = 0;
+ struct bnxt_mpc_txq *mpc_queue;
+ struct bnxt_mpc *mpc;
+
+ rc = is_bnxt_in_error(bp);
+ if (rc)
+ return rc;
+
+ if (!bp->mpc)
+ return 0;
+
+ mpc = bp->mpc;
+ /* free the MPC TX ring for each channel. */
+ for (i = 0 ; i < BNXT_MPC_CHNL_MAX; i++) {
+ if (!(mpc->mpc_chnls_en & (1 << i)))
+ continue;
+ mpc_queue = mpc->mpc_txq[i];
+ if (!mpc_queue)
+ continue;
+ bnxt_mpc_ring_free_one(mpc_queue);
+ bnxt_mpc_queue_release_one(mpc_queue);
+ mpc->mpc_txq[i] = NULL;
+ }
+
+ rc = bnxt_mpc_chnls_disable(bp);
+ if (rc)
+ PMD_DRV_LOG(ERR, "MPC channels disable failed rc:%d\n", rc);
+
+ return rc;
+}
+
+static int bnxt_init_mpc_ring_struct(struct bnxt_mpc_txq *mpc_queue,
+ unsigned int socket_id)
+{
+ struct bnxt_cp_ring_info *cpr;
+ struct bnxt_mpc_ring_info *mpr;
+ struct bnxt_ring *ring;
+ int rc = 0;
+
+ mpr = rte_zmalloc_socket("bnxt_mpc_ring",
+ sizeof(struct bnxt_mpc_ring_info),
+ RTE_CACHE_LINE_SIZE, socket_id);
+ if (mpr == NULL)
+ return -ENOMEM;
+ mpc_queue->mpc_ring = mpr;
+
+ ring = rte_zmalloc_socket("bnxt_mpc_ring_struct",
+ sizeof(struct bnxt_ring),
+ RTE_CACHE_LINE_SIZE, socket_id);
+ if (ring == NULL) {
+ PMD_DRV_LOG(ERR, "MPC ring struct alloc failed rc:%d\n", rc);
+ rc = -ENOMEM;
+ goto bnxt_init_mpc_ring_struct_err;
+ }
+
+ mpr->mpc_ring_struct = ring;
+ ring->ring_size = rte_align32pow2(mpc_queue->nb_mpc_desc);
+ ring->ring_mask = ring->ring_size - 1;
+ ring->bd = (void *)mpr->mpc_desc_ring;
+ ring->bd_dma = mpr->mpc_desc_mapping;
+ ring->vmem_size = ring->ring_size * sizeof(struct bnxt_sw_mpc_bd);
+ ring->vmem = (void **)&mpr->mpc_buf_ring;
+ ring->fw_ring_id = INVALID_HW_RING_ID;
+
+ cpr = rte_zmalloc_socket("bnxt_mpc_ring",
+ sizeof(struct bnxt_cp_ring_info),
+ RTE_CACHE_LINE_SIZE, socket_id);
+ if (cpr == NULL) {
+ PMD_DRV_LOG(ERR, "MPC cp ring alloc failed rc:%d\n", rc);
+ rc = -ENOMEM;
+ goto bnxt_init_mpc_ring_struct_err1;
+ }
+ mpc_queue->cp_ring = cpr;
+
+ ring = rte_zmalloc_socket("bnxt_mpc_ring_struct",
+ sizeof(struct bnxt_ring),
+ RTE_CACHE_LINE_SIZE, socket_id);
+ if (ring == NULL) {
+ PMD_DRV_LOG(ERR, "MPC cp ring struct alloc failed rc:%d\n", rc);
+ rc = -ENOMEM;
+ goto bnxt_init_mpc_ring_struct_err2;
+ }
+ cpr->cp_ring_struct = ring;
+ ring->ring_size = mpr->mpc_ring_struct->ring_size;
+ ring->ring_mask = ring->ring_size - 1;
+ ring->bd = (void *)cpr->cp_desc_ring;
+ ring->bd_dma = cpr->cp_desc_mapping;
+ ring->vmem_size = 0;
+ ring->vmem = NULL;
+ ring->fw_ring_id = INVALID_HW_RING_ID;
+
+ return 0;
+
+bnxt_init_mpc_ring_struct_err2:
+ rte_free(cpr);
+bnxt_init_mpc_ring_struct_err1:
+ rte_free(ring);
+bnxt_init_mpc_ring_struct_err:
+ rte_free(mpr);
+ mpc_queue->mpc_ring = NULL;
+ return rc;
+}
+
+/*
+ * For a MPC queue, allocates a completion ring with vmem and bd ring,
+ * stats mem, a TX ring with vmem and bd ring.
+ *
+ * Order in the allocation is:
+ * stats - Always non-zero length
+ * cp vmem - Always zero-length, supported for the bnxt_ring abstraction
+ * tx vmem - Only non-zero length
+ * cp bd ring - Always non-zero length
+ * tx bd ring - Only non-zero length
+ */
+
+static int bnxt_alloc_mpc_rings(struct bnxt_mpc_txq *mpc_queue,
+ const char *suffix)
+{
+ struct bnxt_ring *cp_ring;
+ struct bnxt_cp_ring_info *cp_ring_info;
+ struct bnxt_mpc_ring_info *mpc_ring_info;
+ struct bnxt_ring *ring;
+ struct rte_pci_device *pdev;
+ const struct rte_memzone *mz = NULL;
+ char mz_name[RTE_MEMZONE_NAMESIZE];
+ rte_iova_t mz_phys_addr;
+
+ if (!mpc_queue)
+ return -EINVAL;
+
+ pdev = mpc_queue->bp->pdev;
+ mpc_ring_info = mpc_queue->mpc_ring;
+ cp_ring = mpc_queue->cp_ring->cp_ring_struct;
+ cp_ring_info = mpc_queue->cp_ring;
+
+ int stats_len = BNXT_HWRM_CTX_GET_SIZE(mpc_queue->bp);
+ stats_len = RTE_CACHE_LINE_ROUNDUP(stats_len);
+ stats_len = RTE_ALIGN(stats_len, 128);
+
+ int cp_vmem_start = stats_len;
+ int cp_vmem_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size);
+ cp_vmem_len = RTE_ALIGN(cp_vmem_len, 128);
+
+ int nq_vmem_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size);
+ nq_vmem_len = RTE_ALIGN(nq_vmem_len, 128);
+
+ int nq_vmem_start = cp_vmem_start + cp_vmem_len;
+
+ int mpc_vmem_start = nq_vmem_start + nq_vmem_len;
+ int mpc_vmem_len =
+ RTE_CACHE_LINE_ROUNDUP(mpc_ring_info->mpc_ring_struct->vmem_size);
+ mpc_vmem_len = RTE_ALIGN(mpc_vmem_len, 128);
+
+ int cp_ring_start = mpc_vmem_start + mpc_vmem_len;
+ cp_ring_start = RTE_ALIGN(cp_ring_start, 4096);
+
+ int cp_ring_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->ring_size *
+ sizeof(struct cmpl_base));
+ cp_ring_len = RTE_ALIGN(cp_ring_len, 128);
+
+ int mpc_ring_start = cp_ring_start + cp_ring_len;
+ mpc_ring_start = RTE_ALIGN(mpc_ring_start, 4096);
+ int mpc_ring_len =
+ RTE_CACHE_LINE_ROUNDUP(mpc_ring_info->mpc_ring_struct->ring_size *
+ sizeof(struct tx_bd_mp_cmd));
+ mpc_ring_len = RTE_ALIGN(mpc_ring_len, 4096);
+
+ int total_alloc_len = mpc_ring_start + mpc_ring_len;
+ snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
+ "bnxt_" PCI_PRI_FMT "-%04x_%s", pdev->addr.domain,
+ pdev->addr.bus, pdev->addr.devid, pdev->addr.function,
+ mpc_queue->chnl_id, suffix);
+ mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
+ mz = rte_memzone_lookup(mz_name);
+ if (!mz) {
+ mz = rte_memzone_reserve_aligned(mz_name, total_alloc_len,
+ SOCKET_ID_ANY,
+ RTE_MEMZONE_2MB |
+ RTE_MEMZONE_SIZE_HINT_ONLY |
+ RTE_MEMZONE_IOVA_CONTIG,
+ getpagesize());
+ if (mz == NULL || !mz->addr)
+ return -ENOMEM;
+ }
+ memset(mz->addr, 0, mz->len);
+ mz_phys_addr = mz->iova;
+
+ mpc_queue->mz = mz;
+ ring = mpc_ring_info->mpc_ring_struct;
+
+ ring->bd = ((char *)mz->addr + mpc_ring_start);
+ mpc_ring_info->mpc_desc_ring = (struct tx_bd_mp_cmd *)ring->bd;
+ ring->bd_dma = mz_phys_addr + mpc_ring_start;
+ mpc_ring_info->mpc_desc_mapping = ring->bd_dma;
+ ring->mem_zone = (const void *)mz;
+
+ if (ring->vmem_size) {
+ ring->vmem = (void **)((char *)mz->addr + mpc_vmem_start);
+ mpc_ring_info->mpc_buf_ring =
+ (struct bnxt_sw_mpc_bd *)ring->vmem;
+ }
+
+ cp_ring->bd = ((char *)mz->addr + cp_ring_start);
+ cp_ring->bd_dma = mz_phys_addr + cp_ring_start;
+ cp_ring_info->cp_desc_ring = cp_ring->bd;
+ cp_ring_info->cp_desc_mapping = cp_ring->bd_dma;
+ cp_ring->mem_zone = (const void *)mz;
+
+ if (cp_ring->vmem_size)
+ *cp_ring->vmem = (char *)mz->addr + stats_len;
+
+ cp_ring_info->hw_stats = mz->addr;
+ cp_ring_info->hw_stats_map = mz_phys_addr;
+ cp_ring_info->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
+
+ return 0;
+}
+
+static void bnxt_init_one_mpc_ring(struct bnxt_mpc_txq *mpc_queue)
+{
+ struct bnxt_mpc_ring_info *mpr = mpc_queue->mpc_ring;
+ struct bnxt_cp_ring_info *cpr = mpc_queue->cp_ring;
+ struct bnxt_ring *ring = mpr->mpc_ring_struct;
+
+ mpc_queue->wake_thresh = ring->ring_size / 2;
+ ring->fw_ring_id = INVALID_HW_RING_ID;
+ mpr->epoch = 0;
+ cpr->epoch = 0;
+}
+
+static uint16_t get_mpc_ring_logical_id(uint8_t mpc_cap,
+ enum bnxt_mpc_chnl chnl_id,
+ uint16_t offset)
+{
+ unsigned int i;
+ uint8_t logical_id = 0;
+
+ for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) {
+ if (!(mpc_cap & (1 << i)))
+ continue;
+
+ if (i == chnl_id)
+ return (logical_id + offset);
+
+ logical_id++;
+ }
+
+ return INVALID_HW_RING_ID;
+}
+
+static int bnxt_mpc_queue_setup_one(struct bnxt *bp, enum bnxt_mpc_chnl chnl_id,
+ uint16_t nb_desc, unsigned int socket_id)
+{
+ int rc = 0;
+ struct bnxt_mpc *mpc;
+ struct bnxt_mpc_txq *mpc_queue;
+
+ if (!bp || !bp->mpc)
+ return 0;
+
+ mpc = bp->mpc;
+ mpc_queue = rte_zmalloc_socket("bnxt_mpc_queue",
+ sizeof(struct bnxt_mpc_txq),
+ RTE_CACHE_LINE_SIZE, socket_id);
+ if (!mpc_queue) {
+ PMD_DRV_LOG(ERR, "bnxt_mpc_queue allocation failed!");
+ return -ENOMEM;
+ }
+
+ mpc_queue->free =
+ rte_zmalloc_socket(NULL,
+ sizeof(struct bnxt_mpc_mbuf *) * nb_desc,
+ RTE_CACHE_LINE_SIZE, socket_id);
+ if (!mpc_queue->free) {
+ PMD_DRV_LOG(ERR, "allocation of mpc mbuf free array failed!");
+ rc = -ENOMEM;
+ goto bnxt_mpc_queue_setup_one_err;
+ }
+ mpc_queue->bp = bp;
+ mpc_queue->nb_mpc_desc = nb_desc;
+ /* TBD: hardcoded to 1 for now and should be tuned later for perf */
+ mpc_queue->free_thresh = BNXT_MPC_DESC_THRESH;
+
+ rc = bnxt_init_mpc_ring_struct(mpc_queue, socket_id);
+ if (rc)
+ goto bnxt_mpc_queue_setup_one_err1;
+
+ mpc_queue->chnl_id = chnl_id;
+
+ /* allocate MPC TX ring hardware descriptors */
+ rc = bnxt_alloc_mpc_rings(mpc_queue, "mpc");
+ if (rc) {
+ PMD_DRV_LOG(ERR, "ring_dma_zone_reserve for mpc_ring failed!");
+ rc = -ENOMEM;
+ goto bnxt_mpc_queue_setup_one_err1;
+ }
+ bnxt_init_one_mpc_ring(mpc_queue);
+ mpc_queue->queue_idx = get_mpc_ring_logical_id(bp->mpc->mpc_chnls_cap,
+ chnl_id,
+ bp->tx_cp_nr_rings);
+ mpc_queue->started = true;
+ mpc->mpc_txq[chnl_id] = mpc_queue;
+
+ return 0;
+
+bnxt_mpc_queue_setup_one_err1:
+ rte_free(mpc_queue->free);
+bnxt_mpc_queue_setup_one_err:
+ rte_free(mpc_queue);
+ return rc;
+}
+
+static int bnxt_mpc_ring_alloc_one(struct bnxt *bp, enum bnxt_mpc_chnl chnl_id)
+{
+ int rc = 0;
+ struct bnxt_mpc_txq *mpc_queue;
+ struct bnxt_cp_ring_info *cpr;
+ struct bnxt_ring *cp_ring;
+ struct bnxt_mpc_ring_info *mpr;
+ struct bnxt_ring *ring;
+ struct bnxt_coal coal;
+ uint32_t map_index;
+
+ if (!bp || !bp->mpc)
+ return 0;
+
+ mpc_queue = bp->mpc->mpc_txq[chnl_id];
+ if (!mpc_queue)
+ return -EINVAL;
+
+ bnxt_init_dflt_coal(&coal);
+ cpr = mpc_queue->cp_ring;
+ cp_ring = cpr->cp_ring_struct;
+ map_index = mpc_queue->queue_idx;
+
+ rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "mpc ring %d stats alloc failed rc:%d!\n",
+ chnl_id, rc);
+ return rc;
+ }
+ rc = bnxt_alloc_cmpl_ring(bp, map_index, cpr);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "mpc ring %d cmpl ring alloc failed rc:%d!\n",
+ chnl_id, rc);
+ goto bnxt_mpc_ring_alloc_one_err;
+ }
+ mpr = mpc_queue->mpc_ring;
+ ring = mpr->mpc_ring_struct;
+ map_index = BNXT_MPC_MAP_INDEX(chnl_id, mpc_queue->queue_idx);
+
+ rc = bnxt_hwrm_ring_alloc(bp,
+ ring,
+ HWRM_RING_ALLOC_INPUT_RING_TYPE_TX,
+ map_index,
+ cpr->hw_stats_ctx_id,
+ cp_ring->fw_ring_id,
+ MPC_HW_COS_ID);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "mpc ring %d tx ring alloc failed rc:%d!\n",
+ chnl_id, rc);
+ goto bnxt_mpc_ring_alloc_one_err1;
+ }
+
+ bnxt_set_db(bp, &mpr->db, HWRM_RING_ALLOC_INPUT_RING_TYPE_TX, chnl_id,
+ ring->fw_ring_id, ring->ring_mask);
+
+ bnxt_hwrm_set_ring_coal(bp, &coal, cp_ring->fw_ring_id);
+
+ return rc;
+
+bnxt_mpc_ring_alloc_one_err1:
+ bnxt_free_cp_ring(bp, cpr);
+bnxt_mpc_ring_alloc_one_err:
+ bnxt_hwrm_stat_ctx_free(bp, cpr);
+ return rc;
+}
+
+int bnxt_mpc_open(struct bnxt *bp)
+{
+ int rc = 0;
+ enum bnxt_mpc_chnl i;
+ struct bnxt_mpc *mpc;
+ unsigned int socket_id;
+
+ rc = is_bnxt_in_error(bp);
+ if (rc)
+ return rc;
+
+ if (!bp->mpc)
+ return 0;
+
+ /* enable the MPC channels first */
+ rc = bnxt_mpc_chnls_enable(bp);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "MPC channels enable failed rc:%d\n", rc);
+ return rc;
+ }
+ socket_id = rte_lcore_to_socket_id(rte_get_main_lcore());
+ mpc = bp->mpc;
+
+ /* Limit to MPC TE_CFA and RE_CFA */
+ mpc->mpc_chnls_cap &= (1 << HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA) |
+ (1 << HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA);
+
+ /* allocate one MPC TX ring for each channel. */
+ for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) {
+ if (!(mpc->mpc_chnls_cap & (1 << i)))
+ continue;
+ rc = bnxt_mpc_queue_setup_one(bp, i, BNXT_MPC_NB_DESC, socket_id);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "MPC queue %d setup failed rc:%d\n",
+ i, rc);
+ goto bnxt_mpc_open_err;
+ }
+ rc = bnxt_mpc_ring_alloc_one(bp, i);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "MPC ring %d alloc failed rc:%d\n",
+ i, rc);
+ goto bnxt_mpc_open_err;
+ }
+ }
+
+ return rc;
+
+bnxt_mpc_open_err:
+ bnxt_mpc_close(bp);
+ return rc;
+}
+
+static inline uint32_t bnxt_mpc_bds_in_hw(struct bnxt_mpc_txq *mpc_queue)
+{
+ struct bnxt_mpc_ring_info *mpc_ring = mpc_queue->mpc_ring;
+#ifdef MPC_DEBUG
+ printf("Raw prod:%d Raw cons:%d Mask:0x%08x Result:%d\n",
+ mpc_ring->raw_prod,
+ mpc_ring->raw_cons,
+ mpc_ring->mpc_ring_struct->ring_mask,
+ ((mpc_ring->raw_prod - mpc_ring->raw_cons) &
+ mpc_ring->mpc_ring_struct->ring_mask));
+ printf("Ring size:%d\n", mpc_queue->mpc_ring->mpc_ring_struct->ring_size);
+#endif
+ return ((mpc_ring->raw_prod - mpc_ring->raw_cons) &
+ mpc_ring->mpc_ring_struct->ring_mask);
+}
+
+int bnxt_mpc_cmd_cmpl(struct bnxt_mpc_txq *mpc_queue, struct bnxt_mpc_mbuf *out_msg)
+{
+ struct bnxt_cp_ring_info *cpr = mpc_queue->cp_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ struct cmpl_base *mpc_cmpl;
+ uint32_t nb_mpc_cmds = 0;
+ struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
+ struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
+ uint32_t ring_mask = cp_ring_struct->ring_mask;
+ uint32_t idx = raw_cons;
+ uint32_t num_bds;
+ bool is_long =
+ (out_msg->cmp_type == CMPL_BASE_TYPE_MID_PATH_LONG ? true : false);
+
+ do {
+ cons = RING_CMPL(ring_mask, raw_cons);
+#ifdef MPC_DEBUG
+ printf("raw_cons:%d cons:%d\n", raw_cons, cons);
+#endif
+ mpc_cmpl = &cpr->cp_desc_ring[cons];
+
+ rte_prefetch_non_temporal(&cp_desc_ring[(cons + 2) &
+ ring_mask]);
+
+ if (!CMPL_VALID(mpc_cmpl, cpr->valid)) {
+ break;
+ } else if (is_long) {
+ uint32_t cons_tmp = cons + 1;
+ uint32_t valid;
+ struct cmpl_base *tmp_mpc_cmpl = &cp_desc_ring[cons_tmp & ring_mask];
+
+ if ((cons_tmp & ring_mask) < (cons & ring_mask))
+ valid = !cpr->valid;
+ else
+ valid = cpr->valid;
+
+ if (!CMPL_VALID(tmp_mpc_cmpl, valid))
+ break;
+ }
+
+ NEXT_CMPL(cpr,
+ cons,
+ cpr->valid,
+ (is_long ? 2 : 1));
+
+ rte_prefetch0(&cp_desc_ring[cons]);
+
+ if (likely(CMP_TYPE(mpc_cmpl) == out_msg->cmp_type)) {
+ nb_mpc_cmds++;
+ idx = raw_cons;
+ raw_cons = cons;
+ break;
+ } else {
+ RTE_LOG_DP(DEBUG, BNXT, "Unhandled CMP type %02x\n",
+ CMP_TYPE(mpc_cmpl));
+ }
+#ifdef MPC_DEBUG
+ printf("info2:0x%08x nb_mpc_cmds:%d\n", mpc_cmpl->info2, nb_mpc_cmds);
+#endif
+ raw_cons = cons;
+ } while (nb_mpc_cmds < ring_mask);
+
+ if (nb_mpc_cmds) {
+ memcpy(out_msg->msg_data,
+ &cpr->cp_desc_ring[idx],
+ BNXT_MPC_BP_SIZE);
+
+ if (is_long) {
+ uint32_t tidx = idx + 1;
+
+ if (tidx >= BNXT_MPC_NB_DESC)
+ tidx = 0;
+
+ memcpy(out_msg->msg_data + BNXT_MPC_BP_SIZE,
+ &cpr->cp_desc_ring[tidx],
+ BNXT_MPC_BP_SIZE);
+ }
+
+#ifdef MPC_DEBUG
+ printf("cp_raw_cons:%d\n", cpr->cp_raw_cons);
+#endif
+ if (is_long)
+ num_bds = 2;
+ else
+ num_bds = 1;
+
+ cpr->cp_raw_cons = idx + num_bds;
+
+ /* Handle the wrap */
+ if (cpr->cp_raw_cons >= BNXT_MPC_NB_DESC) {
+#ifdef MPC_DEBUG
+ printf("Completion queue epoch flip from: %d to %d\n",
+ cpr->epoch,
+ (cpr->epoch == 0 ? 1 : 0));
+#endif
+ cpr->epoch = (cpr->epoch == 0 ? 1 : 0);
+ cpr->cp_raw_cons -= BNXT_MPC_NB_DESC;
+ }
+
+ bnxt_db_mpc_cq(cpr);
+ }
+
+ return nb_mpc_cmds;
+}
+
+static inline uint32_t bnxt_mpc_avail(struct bnxt_mpc_txq *mpc_queue)
+{
+ /* Tell compiler to fetch mpc indices from memory. */
+ rte_compiler_barrier();
+
+ return ((mpc_queue->mpc_ring->mpc_ring_struct->ring_size -
+ bnxt_mpc_bds_in_hw(mpc_queue)) - 1);
+}
+
+#ifdef MPC_DEBUG
+void dump_bd(uint8_t *bd, uint32_t num_bd)
+{
+ int j;
+ int i;
+
+ for (j = 0; j < num_bd; j++) {
+ printf("%d: ", j);
+ for (i = 0; i < BNXT_MPC_BP_SIZE; i++) {
+ printf("%02x", *bd);
+ bd++;
+ }
+
+ printf("\n");
+ }
+ printf("\n");
+}
+#endif
+
+static uint16_t bnxt_mpc_xmit(struct bnxt_mpc_mbuf *mpc_cmd,
+ struct bnxt_mpc_txq *mpc_queue,
+ uint32_t *opaque)
+{
+ struct bnxt_mpc_ring_info *mpr = mpc_queue->mpc_ring;
+ struct bnxt_ring *ring = mpr->mpc_ring_struct;
+ unsigned short nr_bds = 0;
+ uint16_t prod;
+ struct bnxt_sw_mpc_bd *mpc_buf;
+ struct tx_bd_mp_cmd *mpc_bd;
+ uint8_t *msg_buf;
+ int i;
+
+ if (unlikely(is_bnxt_in_error(mpc_queue->bp)))
+ return -EIO;
+
+ nr_bds = (mpc_cmd->msg_size + sizeof(struct tx_bd_mp_cmd) - 1)
+ / sizeof(struct tx_bd_mp_cmd) + 1;
+
+ prod = RING_IDX(ring, mpr->raw_prod);
+#ifdef MPC_DEBUG
+ printf("tx raw prod:%d prod:%d\n", mpr->raw_prod, prod);
+#endif
+ mpc_buf = &mpr->mpc_buf_ring[prod];
+ mpc_buf->mpc_mbuf = mpc_cmd;
+ mpc_buf->nr_bds = nr_bds;
+
+ mpc_bd = &mpr->mpc_desc_ring[prod];
+ memset(mpc_bd, 0, sizeof(struct tx_bd_mp_cmd));
+ mpc_bd->opaque = *opaque;
+ mpc_bd->flags_type = nr_bds << TX_BD_MP_CMD_FLAGS_BD_CNT_SFT;
+ mpc_bd->flags_type |= TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD;
+ mpc_bd->len = mpc_cmd->msg_size;
+
+ /* copy the messages to the subsequent inline bds */
+ for (i = 0; i < nr_bds - 1; i++) {
+ mpr->raw_prod = RING_NEXT(mpr->raw_prod) % BNXT_MPC_NB_DESC;
+ prod = RING_IDX(ring, mpr->raw_prod);
+#ifdef MPC_DEUBG
+ printf("tx raw prod:%d prod:%d\n", mpr->raw_prod, prod);
+#endif
+ mpc_bd = &mpr->mpc_desc_ring[prod];
+ msg_buf = mpc_cmd->msg_data + i * sizeof(struct tx_bd_mp_cmd);
+ memcpy(mpc_bd, msg_buf, sizeof(struct tx_bd_mp_cmd));
+ }
+
+ mpr->raw_prod = RING_NEXT(mpr->raw_prod) % BNXT_MPC_NB_DESC;
+#ifdef MPC_DEBUG
+ printf("tx raw prod:%d prod:%d\n", mpr->raw_prod, prod);
+#endif
+ return 0;
+}
+
+int bnxt_mpc_send(struct bnxt *bp,
+ struct bnxt_mpc_mbuf *in_msg,
+ struct bnxt_mpc_mbuf *out_msg,
+ uint32_t *opaque,
+ bool batch)
+{
+ int rc;
+ struct bnxt_mpc_txq *mpc_queue = bp->mpc->mpc_txq[in_msg->chnl_id];
+ int retry = BNXT_MPC_RX_RETRY;
+ uint32_t pi = 0;
+
+ if (out_msg->cmp_type != CMPL_BASE_TYPE_MID_PATH_SHORT &&
+ out_msg->cmp_type != CMPL_BASE_TYPE_MID_PATH_LONG)
+ return -1;
+
+#ifdef MPC_DEBUG
+ if (mpc_queue == NULL || mpc_queue->mpc_ring == NULL)
+ return -1;
+#endif
+
+ /*
+ * Save the producer index so that if wrapping occurs
+ * it can be detected.
+ */
+ pi = mpc_queue->mpc_ring->raw_prod;
+ rc = bnxt_mpc_xmit(in_msg, mpc_queue, opaque);
+
+ if (unlikely(rc))
+ return -1;
+#ifdef MPC_DEBUG
+ printf("raw_prod:%d pi:%d\n", mpc_queue->mpc_ring->raw_prod, pi);
+#endif
+ /*
+ * If the producer index wraps then toggle the epoch.
+ */
+ if (mpc_queue->mpc_ring->raw_prod < pi) {
+#ifdef MPC_DEBUG
+ printf("Tx queue epoch flip from: %d to %d\n",
+ mpc_queue->mpc_ring->epoch,
+ (mpc_queue->mpc_ring->epoch == 0 ? 1 : 0));
+#endif
+ mpc_queue->mpc_ring->epoch = (mpc_queue->mpc_ring->epoch == 0 ? 1 : 0);
+ }
+
+#ifdef MPC_DEBUG
+ dump_bd(&mpc_queue->mpc_ring->mpc_desc_ring[pi], 4);
+#endif
+ /*
+ * Ring the Tx doorbell.
+ */
+ bnxt_db_mpc_write(&mpc_queue->mpc_ring->db,
+ mpc_queue->mpc_ring->raw_prod,
+ mpc_queue->mpc_ring->epoch);
+
+ if (batch)
+ return 0;
+
+ /* Wait for response */
+ do {
+ rte_delay_us_block(BNXT_MPC_RX_US_DELAY);
+
+ rc = bnxt_mpc_cmd_cmpl(mpc_queue, out_msg);
+
+ if (rc == 1)
+ return 0;
+#ifdef MPC_DEBUG
+ printf("Received zero or more than one completion:%d\n", rc);
+#endif
+ retry--;
+ } while (retry);
+
+ return -1;
+}
new file mode 100644
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _BNXT_MPC_H_
+#define _BNXT_MPC_H_
+
+#include <inttypes.h>
+#include <stdbool.h>
+#include <rte_malloc.h>
+
+/* MPC Batch support */
+extern bool bnxt_tfc_mpc_batch;
+extern uint8_t bnxt_mpc_batch_count;
+
+#define BNXT_MPC_RX_RETRY 100000
+
+#define BNXT_MPC_NB_DESC 128
+#define BNXT_MPC_DESC_THRESH 3
+#define BNXT_MPC_CHNL_SHIFT 16
+#define BNXT_MPC_QIDX_MSK 0xFFFF
+#define BNXT_MPC_CHNL(x) ((x) >> BNXT_MPC_CHNL_SHIFT)
+#define BNXT_MPC_QIDX(x) ((x) & BNXT_MPC_QIDX_MSK)
+#define BNXT_MPC_MAP_INDEX(x, y) (((x) << BNXT_MPC_CHNL_SHIFT) | (y))
+
+#define BNXT_MPC_CHNLS_SUPPORTED 2 /* Limit to MPC TE_CFA and RE_CFA */
+
+/* BNXT_MPC_RINGS_SUPPORTED set to 1 TE_CFA and 1 1 RE_CFA types.
+ * Can be set upto tx_nr_rings * BNXT_MPC_CHNLS_SUPPORTED if needed.
+ */
+#define BNXT_MPC_RINGS_SUPPORTED (1 * BNXT_MPC_CHNLS_SUPPORTED)
+
+/* Defines the number of msgs there are in an MPC msg completion event.
+ * Used to pass an opaque value into the MPC msg xmit function. The
+ * completion processing uses this value to ring the doorbell correctly to
+ * signal "completion event processing complete" to the hardware.
+ */
+#define BNXT_MPC_COMP_MSG_COUNT 1
+
+/* Defines the uS delay prior to processing an MPC completion */
+#define BNXT_MPC_RX_US_DELAY 1
+
+enum bnxt_mpc_chnl {
+ BNXT_MPC_CHNL_TCE = 0,
+ BNXT_MPC_CHNL_RCE = 1,
+ BNXT_MPC_CHNL_TE_CFA = 2,
+ BNXT_MPC_CHNL_RE_CFA = 3,
+ BNXT_MPC_CHNL_PRIMATE = 4,
+ BNXT_MPC_CHNL_MAX = 5,
+};
+
+struct bnxt_sw_mpc_bd {
+ struct bnxt_mpc_mbuf *mpc_mbuf; /* mpc mbuf associated with mpc bd */
+ unsigned short nr_bds;
+};
+
+struct bnxt_mpc_ring_info {
+ uint16_t raw_prod;
+ uint16_t raw_cons;
+ struct bnxt_db_info db;
+
+ struct tx_bd_mp_cmd *mpc_desc_ring;
+ struct bnxt_sw_mpc_bd *mpc_buf_ring;
+
+ rte_iova_t mpc_desc_mapping;
+
+ uint32_t dev_state;
+
+ struct bnxt_ring *mpc_ring_struct;
+ uint32_t epoch;
+};
+
+struct bnxt_mpc_mbuf {
+ enum bnxt_mpc_chnl chnl_id;
+ uint8_t cmp_type;
+ uint8_t *msg_data;
+ /* MPC msg size in bytes, must be multiple of 16Bytes */
+ uint16_t msg_size;
+};
+
+struct bnxt_mpc_txq {
+ enum bnxt_mpc_chnl chnl_id;
+ uint32_t queue_idx;
+ uint16_t nb_mpc_desc; /* number of MPC descriptors */
+ uint16_t free_thresh;/* minimum mpc cmds before freeing */
+ int wake_thresh;
+ uint8_t started; /* MPC queue is started */
+
+ struct bnxt *bp;
+ struct bnxt_mpc_ring_info *mpc_ring;
+ unsigned int cp_nr_rings;
+ struct bnxt_cp_ring_info *cp_ring;
+ const struct rte_memzone *mz;
+ struct bnxt_mpc_mbuf **free;
+
+ void (*cmpl_handler_cb)(struct bnxt_mpc_txq *mpc_queue,
+ uint32_t nb_mpc_cmds);
+};
+
+struct bnxt_mpc {
+ uint8_t mpc_chnls_cap;
+ uint8_t mpc_chnls_en;
+ struct bnxt_mpc_txq *mpc_txq[BNXT_MPC_CHNL_MAX];
+};
+
+int bnxt_mpc_open(struct bnxt *bp);
+int bnxt_mpc_close(struct bnxt *bp);
+int bnxt_mpc_send(struct bnxt *bp,
+ struct bnxt_mpc_mbuf *in_msg,
+ struct bnxt_mpc_mbuf *out_msg,
+ uint32_t *opaque,
+ bool batch);
+int bnxt_mpc_cmd_cmpl(struct bnxt_mpc_txq *mpc_queue, struct bnxt_mpc_mbuf *out_msg);
+int bnxt_mpc_poll_cmd_cmpls(struct bnxt_mpc_txq *mpc_queue);
+
+#endif
@@ -57,6 +57,7 @@ int bnxt_alloc_ring_grps(struct bnxt *bp)
/* P5 does not support ring groups.
* But we will use the array to save RSS context IDs.
*/
+ /* TODO Revisit for Thor 2 */
if (BNXT_CHIP_P5_P7(bp)) {
bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
} else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
@@ -329,7 +330,7 @@ int bnxt_alloc_rings(struct bnxt *bp, unsigned int socket_id, uint16_t qidx,
return 0;
}
-static void bnxt_init_dflt_coal(struct bnxt_coal *coal)
+void bnxt_init_dflt_coal(struct bnxt_coal *coal)
{
/* Tick values in micro seconds.
* 1 coal_buf x bufs_per_record = 1 completion record.
@@ -347,12 +348,12 @@ static void bnxt_init_dflt_coal(struct bnxt_coal *coal)
coal->cmpl_aggr_dma_tmr_during_int = BNXT_CMPL_AGGR_DMA_TMR_DURING_INT;
}
-static void bnxt_set_db(struct bnxt *bp,
- struct bnxt_db_info *db,
- uint32_t ring_type,
- uint32_t map_idx,
- uint32_t fid,
- uint32_t ring_mask)
+void bnxt_set_db(struct bnxt *bp,
+ struct bnxt_db_info *db,
+ uint32_t ring_type,
+ uint32_t map_idx,
+ uint32_t fid,
+ uint32_t ring_mask)
{
if (BNXT_CHIP_P5_P7(bp)) {
int db_offset = DB_PF_OFFSET;
@@ -400,8 +401,8 @@ static void bnxt_set_db(struct bnxt *bp,
db->db_ring_mask = ring_mask;
}
-static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
- struct bnxt_cp_ring_info *cpr)
+int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
+ struct bnxt_cp_ring_info *cpr)
{
struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
uint32_t nq_ring_id = HWRM_NA_SIGNATURE;
@@ -37,7 +37,8 @@
#define MAX_CP_DESC_CNT (16 * 1024)
#define INVALID_HW_RING_ID ((uint16_t)-1)
-#define INVALID_STATS_CTX_ID ((uint16_t)-1)
+#define INVALID_STATS_CTX_ID ((uint16_t)-1)
+#define MPC_HW_COS_ID ((uint16_t)-2)
struct bnxt_ring {
void *bd;
@@ -80,6 +81,15 @@ void bnxt_free_async_cp_ring(struct bnxt *bp);
int bnxt_alloc_async_ring_struct(struct bnxt *bp);
int bnxt_alloc_rxtx_nq_ring(struct bnxt *bp);
void bnxt_free_rxtx_nq_ring(struct bnxt *bp);
+void bnxt_init_dflt_coal(struct bnxt_coal *coal);
+int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
+ struct bnxt_cp_ring_info *cpr);
+void bnxt_set_db(struct bnxt *bp,
+ struct bnxt_db_info *db,
+ uint32_t ring_type,
+ uint32_t map_idx,
+ uint32_t fid,
+ uint32_t ring_mask);
static inline void bnxt_db_write(struct bnxt_db_info *db, uint32_t idx)
{
@@ -98,6 +108,27 @@ static inline void bnxt_db_write(struct bnxt_db_info *db, uint32_t idx)
}
}
+static inline void bnxt_db_mpc_write(struct bnxt_db_info *db, uint32_t idx, uint32_t epoch)
+{
+ uint32_t db_idx = DB_RING_IDX(db, idx);
+ void *doorbell = db->doorbell;
+
+ if (likely(db->db_64)) {
+ uint64_t key_idx = db->db_key64 | db_idx |
+ (epoch << 24);
+#ifdef RING_DEBUG
+ printf("DB: 0x%08x:%08x\n",
+ (uint32_t)((key_idx >> 32) & 0xFFFFFFFF),
+ (uint32_t)(key_idx & 0xFFFFFFFF));
+#endif
+ rte_write64_relaxed(key_idx, doorbell);
+ } else {
+ uint32_t key_idx = db->db_key32 | db_idx;
+
+ rte_write32_relaxed(key_idx, doorbell);
+ }
+}
+
/* Ring an NQ doorbell and disable interrupts for the ring. */
static inline void bnxt_db_nq(struct bnxt_cp_ring_info *cpr)
{
@@ -143,4 +174,25 @@ static inline void bnxt_db_cq(struct bnxt_cp_ring_info *cpr)
B_CP_DIS_DB(cpr, cp_raw_cons);
}
}
+
+static inline void bnxt_db_mpc_cq(struct bnxt_cp_ring_info *cpr)
+{
+ struct bnxt_db_info *db = &cpr->cp_db;
+ uint32_t idx = DB_RING_IDX(&cpr->cp_db, cpr->cp_raw_cons);
+
+ if (likely(db->db_64)) {
+ uint64_t key_idx = db->db_key64 | idx |
+ (cpr->epoch << 24);
+ void *doorbell = db->doorbell;
+
+ rte_compiler_barrier();
+ rte_write64_relaxed(key_idx, doorbell);
+ } else {
+ uint32_t cp_raw_cons = cpr->cp_raw_cons;
+
+ rte_compiler_barrier();
+ B_CP_DIS_DB(cpr, cp_raw_cons);
+ }
+}
+
#endif
@@ -3,6 +3,10 @@
* All rights reserved.
*/
+/*!
+ * \file
+ * \brief Exported functions for CFA HW programming
+ */
#ifndef _HCAPI_CFA_H_
#define _HCAPI_CFA_H_
@@ -104,18 +108,7 @@ struct hcapi_cfa_devops {
extern const size_t CFA_RM_HANDLE_DATA_SIZE;
-#if SUPPORT_CFA_HW_ALL
-extern const struct hcapi_cfa_devops cfa_p4_devops;
-extern const struct hcapi_cfa_devops cfa_p58_devops;
-
-#elif defined(SUPPORT_CFA_HW_P4) && SUPPORT_CFA_HW_P4
extern const struct hcapi_cfa_devops cfa_p4_devops;
-uint64_t hcapi_cfa_p4_key_hash(uint64_t *key_data, uint16_t bitlen);
-/* SUPPORT_CFA_HW_P4 */
-#elif defined(SUPPORT_CFA_HW_P58) && SUPPORT_CFA_HW_P58
extern const struct hcapi_cfa_devops cfa_p58_devops;
-uint64_t hcapi_cfa_p58_key_hash(uint64_t *key_data, uint16_t bitlen);
-/* SUPPORT_CFA_HW_P58 */
-#endif
#endif /* HCAPI_CFA_H_ */
@@ -1,12 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
-/*!
- * \file
- * \brief Exported functions for CFA HW programming
- */
#ifndef _HCAPI_CFA_DEFS_H_
#define _HCAPI_CFA_DEFS_H_
@@ -23,34 +19,24 @@
#define CFA_BITS_PER_BYTE (8)
#define CFA_BITS_PER_WORD (sizeof(uint32_t) * CFA_BITS_PER_BYTE)
#define __CFA_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
+#ifndef CFA_ALIGN
#define CFA_ALIGN(x, a) __CFA_ALIGN_MASK((x), (a) - 1)
+#endif
#define CFA_ALIGN_256(x) CFA_ALIGN(x, 256)
#define CFA_ALIGN_128(x) CFA_ALIGN(x, 128)
#define CFA_ALIGN_32(x) CFA_ALIGN(x, 32)
-#define NUM_WORDS_ALIGN_32BIT(x) (CFA_ALIGN_32(x) / CFA_BITS_PER_WORD)
-#define NUM_WORDS_ALIGN_128BIT(x) (CFA_ALIGN_128(x) / CFA_BITS_PER_WORD)
-#define NUM_WORDS_ALIGN_256BIT(x) (CFA_ALIGN_256(x) / CFA_BITS_PER_WORD)
-
/* TODO: redefine according to chip variant */
#define CFA_GLOBAL_CFG_DATA_SZ (100)
-#ifndef SUPPORT_CFA_HW_P4
-#define SUPPORT_CFA_HW_P4 (0)
-#endif
-
-#ifndef SUPPORT_CFA_HW_P45
-#define SUPPORT_CFA_HW_P45 (0)
-#endif
-
-#ifndef SUPPORT_CFA_HW_P58
-#define SUPPORT_CFA_HW_P58 (0)
-#endif
-
-#if SUPPORT_CFA_HW_ALL
#include "hcapi_cfa_p4.h"
#include "hcapi_cfa_p58.h"
-#endif /* SUPPORT_CFA_HW_ALL */
+
+#define CFA_PROF_L2CTXT_TCAM_MAX_FIELD_CNT CFA_P58_PROF_L2_CTXT_TCAM_MAX_FLD
+#define CFA_PROF_L2CTXT_REMAP_MAX_FIELD_CNT CFA_P58_PROF_L2_CTXT_RMP_DR_MAX_FLD
+#define CFA_PROF_MAX_KEY_CFG_SZ sizeof(struct cfa_p58_prof_key_cfg)
+#define CFA_KEY_MAX_FIELD_CNT 0
+#define CFA_ACT_MAX_TEMPLATE_SZ 0
/*
* Hashing defines
@@ -61,6 +47,7 @@
#define ucrc32(ch, crc) (crc32tbl[((crc) ^ (ch)) & 0xff] ^ ((crc) >> 8))
#define crc32(x, y) crc32i(~0, x, y)
+
/**
* CFA HW version definition
*/
@@ -68,7 +55,8 @@ enum hcapi_cfa_ver {
HCAPI_CFA_P40 = 0, /**< CFA phase 4.0 */
HCAPI_CFA_P45 = 1, /**< CFA phase 4.5 */
HCAPI_CFA_P58 = 2, /**< CFA phase 5.8 */
- HCAPI_CFA_PMAX = 3
+ HCAPI_CFA_P59 = 3, /**< CFA phase 5.9 */
+ HCAPI_CFA_PMAX = 4
};
/**
@@ -100,7 +88,7 @@ enum hcapi_cfa_hwops {
* operation is also undo the add operation
* performed by the HCAPI_CFA_HWOPS_ADD op.
*/
- HCAPI_CFA_HWOPS_EVICT, /*< This operation is used to evict entries from
+ HCAPI_CFA_HWOPS_EVICT, /*< This operation is used to edit entries from
* CFA cache memories. This operation is only
* applicable to tables that use CFA caches.
*/
@@ -116,6 +104,44 @@ enum hcapi_cfa_key_ctrlops {
HCAPI_CFA_KEY_CTRLOPS_MAX
};
+/**
+ * CFA HW field structure definition
+ */
+struct hcapi_cfa_field {
+ /** [in] Starting bit position pf the HW field within a HW table
+ * entry.
+ */
+ uint16_t bitpos;
+ /** [in] Number of bits for the HW field. */
+ uint16_t bitlen;
+};
+
+/**
+ * CFA HW table entry layout structure definition
+ */
+struct hcapi_cfa_layout {
+ /** [out] Bit order of layout */
+ bool is_msb_order;
+ /** [out] Size in bits of entry */
+ uint32_t total_sz_in_bits;
+ /** [out] data pointer of the HW layout fields array */
+ struct hcapi_cfa_field *field_array;
+ /** [out] number of HW field entries in the HW layout field array */
+ uint32_t array_sz;
+ /** [out] layout_id - layout id associated with the layout */
+ uint16_t layout_id;
+};
+
+/**
+ * CFA HW data object definition
+ */
+struct hcapi_cfa_data_obj {
+ /** [in] HW field identifier. Used as an index to a HW table layout */
+ uint16_t field_id;
+ /** [in] Value of the HW field */
+ uint64_t val;
+};
+
/**
* CFA HW definition
*/
@@ -294,6 +320,91 @@ struct hcapi_cfa_key_loc {
uint32_t mem_idx;
};
+/**
+ * CFA HW layout table definition
+ */
+struct hcapi_cfa_layout_tbl {
+ /** [out] data pointer to an array of fix formatted layouts supported.
+ * The index to the array is the CFA HW table ID
+ */
+ const struct hcapi_cfa_layout *tbl;
+ /** [out] number of fix formatted layouts in the layout array */
+ uint16_t num_layouts;
+};
+
+/**
+ * Key template consists of key fields that can be enabled/disabled
+ * individually.
+ */
+struct hcapi_cfa_key_template {
+ /** [in] key field enable field array, set 1 to the correspeonding
+ * field enable to make a field valid
+ */
+ uint8_t field_en[CFA_KEY_MAX_FIELD_CNT];
+ /** [in] Identify if the key template is for TCAM. If false, the
+ * key template is for EM. This field is mandantory for device that
+ * only support fix key formats.
+ */
+ bool is_wc_tcam_key;
+ /** [in] Identify if the key template will be use for IPv6 Keys.
+ *
+ */
+ bool is_ipv6_key;
+};
+
+/**
+ * key layout consist of field array, key bitlen, key ID, and other meta data
+ * pertain to a key
+ */
+struct hcapi_cfa_key_layout {
+ /** [out] key layout data */
+ struct hcapi_cfa_layout *layout;
+ /** [out] actual key size in number of bits */
+ uint16_t bitlen;
+ /** [out] key identifier and this field is only valid for device
+ * that supports fix key formats
+ */
+ uint16_t id;
+ /** [out] Identified the key layout is WC TCAM key */
+ bool is_wc_tcam_key;
+ /** [out] Identify if the key template will be use for IPv6 Keys.
+ *
+ */
+ bool is_ipv6_key;
+ /** [out] total slices size, valid for WC TCAM key only. It can be
+ * used by the user to determine the total size of WC TCAM key slices
+ * in bytes.
+ */
+ uint16_t slices_size;
+};
+
+/**
+ * key layout memory contents
+ */
+struct hcapi_cfa_key_layout_contents {
+ /** key layouts */
+ struct hcapi_cfa_key_layout key_layout;
+
+ /** layout */
+ struct hcapi_cfa_layout layout;
+
+ /** fields */
+ struct hcapi_cfa_field field_array[CFA_KEY_MAX_FIELD_CNT];
+};
+
+/**
+ * Action template consists of action fields that can be enabled/disabled
+ * individually.
+ */
+struct hcapi_cfa_action_template {
+ /** [in] CFA version for the action template */
+ enum hcapi_cfa_ver hw_ver;
+ /** [in] action field enable field array, set 1 to the correspeonding
+ * field enable to make a field valid
+ */
+ uint8_t data[CFA_ACT_MAX_TEMPLATE_SZ];
+};
+
/**
* Action record info
*/
@@ -332,6 +443,421 @@ struct hcapi_cfa_action_obj {
struct hcapi_cfa_action_layout *layout;
};
+/**
+ * action layout consist of field array, action wordlen and action format ID
+ */
+struct hcapi_cfa_action_layout {
+ /** [in] action identifier */
+ uint16_t id;
+ /** [out] action layout data */
+ struct hcapi_cfa_layout *layout;
+ /** [out] actual action record size in number of bits */
+ uint16_t bitlen;
+};
+
+/**
+ * CFA backing store type definition
+ */
+enum hcapi_cfa_bs_type {
+ HCAPI_CFA_BS_TYPE_LKUP, /**< EM LKUP backing store type */
+ HCAPI_CFA_BS_TYPE_ACT, /**< Action backing store type */
+ HCAPI_CFA_BS_TYPE_MAX
+};
+
+/**
+ * CFA backing store configuration data object
+ */
+struct hcapi_cfa_bs_cfg {
+ enum hcapi_cfa_bs_type type;
+ uint16_t tbl_scope;
+ struct hcapi_cfa_bs_db *bs_db;
+};
+
+/**
+ * CFA backing store data base object
+ */
+struct hcapi_cfa_bs_db {
+ /** [in] memory manager database signature */
+ uint32_t signature;
+#define HCAPI_CFA_BS_SIGNATURE 0xCFA0B300
+ /** [in] memory manager database base pointer (VA) */
+ void *mgmt_db;
+ /** [in] memory manager database size in bytes */
+ uint32_t mgmt_db_sz;
+ /** [in] Backing store memory pool base pointer
+ * (VA – backed by IOVA which is DMA accessible))
+ */
+ void *bs_ptr;
+ /** [in] bs_offset - byte offset to the section of the
+ * backing store memory managed by the backing store
+ * memory manager.
+ * For EM backing store, this is the starting byte
+ * offset to the EM record memory.
+ * For Action backing store, this offset is 0.
+ */
+ uint32_t offset;
+ /** [in] backing store memory pool size in bytes
+ */
+ uint32_t bs_sz;
+};
+
+/**
+ * \defgroup CFA_HCAPI_PUT_API
+ * HCAPI used for writing to the hardware
+ * @{
+ */
+
+/**
+ * This API provides the functionality to program a specified value to a
+ * HW field based on the provided programming layout.
+ *
+ * @param[in,out] obj_data
+ * A data pointer to a CFA HW key/mask data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in] field_id
+ * ID of the HW field to be programmed
+ *
+ * @param[in] val
+ * Value of the HW field to be programmed
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_put_field(uint64_t *data_buf,
+ const struct hcapi_cfa_layout *layout,
+ uint16_t field_id, uint64_t val);
+
+/**
+ * This API provides the functionality to program an array of field values
+ * with corresponding field IDs to a number of profiler sub-block fields
+ * based on the fixed profiler sub-block hardware programming layout.
+ *
+ * @param[in, out] obj_data
+ * A pointer to a CFA profiler key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in] field_tbl
+ * A pointer to an array that consists of the object field
+ * ID/value pairs
+ *
+ * @param[in] field_tbl_sz
+ * Number of entries in the table
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_put_fields(uint64_t *obj_data,
+ const struct hcapi_cfa_layout *layout,
+ struct hcapi_cfa_data_obj *field_tbl,
+ uint16_t field_tbl_sz);
+/**
+ * This API provides the functionality to program an array of field values
+ * with corresponding field IDs to a number of profiler sub-block fields
+ * based on the fixed profiler sub-block hardware programming layout. This
+ * API will swap the n byte blocks before programming the field array.
+ *
+ * @param[in, out] obj_data
+ * A pointer to a CFA profiler key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in] field_tbl
+ * A pointer to an array that consists of the object field
+ * ID/value pairs
+ *
+ * @param[in] field_tbl_sz
+ * Number of entries in the table
+ *
+ * @param[in] data_size
+ * size of the data in bytes
+ *
+ * @param[in] n
+ * block size in bytes
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_put_fields_swap(uint64_t *obj_data,
+ const struct hcapi_cfa_layout *layout,
+ struct hcapi_cfa_data_obj *field_tbl,
+ uint16_t field_tbl_sz, uint16_t data_size,
+ uint16_t n);
+/**
+ * This API provides the functionality to write a value to a
+ * field within the bit position and bit length of a HW data
+ * object based on a provided programming layout.
+ *
+ * @param[in, out] act_obj
+ * A pointer of the action object to be initialized
+ *
+ * @param[in] layout
+ * A pointer of the programming layout
+ *
+ * @param field_id
+ * [in] Identifier of the HW field
+ *
+ * @param[in] bitpos_adj
+ * Bit position adjustment value
+ *
+ * @param[in] bitlen_adj
+ * Bit length adjustment value
+ *
+ * @param[in] val
+ * HW field value to be programmed
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_put_field_rel(uint64_t *obj_data,
+ const struct hcapi_cfa_layout *layout,
+ uint16_t field_id, int16_t bitpos_adj,
+ int16_t bitlen_adj, uint64_t val);
+
+/*@}*/
+
+/**
+ * \defgroup CFA_HCAPI_GET_API
+ * HCAPI used for writing to the hardware
+ * @{
+ */
+
+/**
+ * This API provides the functionality to get the word length of
+ * a layout object.
+ *
+ * @param[in] layout
+ * A pointer of the HW layout
+ *
+ * @return
+ * Word length of the layout object
+ */
+uint16_t hcapi_cfa_get_wordlen(const struct hcapi_cfa_layout *layout);
+
+/**
+ * The API provides the functionality to get bit offset and bit
+ * length information of a field from a programming layout.
+ *
+ * @param[in] layout
+ * A pointer of the action layout
+ *
+ * @param[out] slice
+ * A pointer to the action offset info data structure
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_get_slice(const struct hcapi_cfa_layout *layout,
+ uint16_t field_id, struct hcapi_cfa_field *slice);
+
+/**
+ * This API provides the functionality to read the value of a
+ * CFA HW field from CFA HW data object based on the hardware
+ * programming layout.
+ *
+ * @param[in] obj_data
+ * A pointer to a CFA HW key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in] field_id
+ * ID of the HW field to be programmed
+ *
+ * @param[out] val
+ * Value of the HW field
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_get_field(uint64_t *obj_data,
+ const struct hcapi_cfa_layout *layout,
+ uint16_t field_id, uint64_t *val);
+
+/**
+ * This API provides the functionality to read 128-bit value of
+ * a CFA HW field from CFA HW data object based on the hardware
+ * programming layout.
+ *
+ * @param[in] obj_data
+ * A pointer to a CFA HW key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in] field_id
+ * ID of the HW field to be programmed
+ *
+ * @param[out] val_msb
+ * Msb value of the HW field
+ *
+ * @param[out] val_lsb
+ * Lsb value of the HW field
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_get128_field(uint64_t *obj_data,
+ const struct hcapi_cfa_layout *layout,
+ uint16_t field_id, uint64_t *val_msb,
+ uint64_t *val_lsb);
+
+/**
+ * This API provides the functionality to read a number of
+ * HW fields from a CFA HW data object based on the hardware
+ * programming layout.
+ *
+ * @param[in] obj_data
+ * A pointer to a CFA profiler key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in, out] field_tbl
+ * A pointer to an array that consists of the object field
+ * ID/value pairs
+ *
+ * @param[in] field_tbl_sz
+ * Number of entries in the table
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_get_fields(uint64_t *obj_data,
+ const struct hcapi_cfa_layout *layout,
+ struct hcapi_cfa_data_obj *field_tbl,
+ uint16_t field_tbl_sz);
+
+/**
+ * This API provides the functionality to read a number of
+ * HW fields from a CFA HW data object based on the hardware
+ * programming layout.This API will swap the n byte blocks before
+ * retrieving the field array.
+ *
+ * @param[in] obj_data
+ * A pointer to a CFA profiler key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in, out] field_tbl
+ * A pointer to an array that consists of the object field
+ * ID/value pairs
+ *
+ * @param[in] field_tbl_sz
+ * Number of entries in the table
+ *
+ * @param[in] data_size
+ * size of the data in bytes
+ *
+ * @param[in] n
+ * block size in bytes
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_get_fields_swap(uint64_t *obj_data,
+ const struct hcapi_cfa_layout *layout,
+ struct hcapi_cfa_data_obj *field_tbl,
+ uint16_t field_tbl_sz, uint16_t data_size,
+ uint16_t n);
+
+/**
+ * Get a value to a specific location relative to a HW field
+ *
+ * This API provides the functionality to read HW field from
+ * a section of a HW data object identified by the bit position
+ * and bit length from a given programming layout in order to avoid
+ * reading the entire HW data object.
+ *
+ * @param[in] obj_data
+ * A pointer of the data object to read from
+ *
+ * @param[in] layout
+ * A pointer of the programming layout
+ *
+ * @param[in] field_id
+ * Identifier of the HW field
+ *
+ * @param[in] bitpos_adj
+ * Bit position adjustment value
+ *
+ * @param[in] bitlen_adj
+ * Bit length adjustment value
+ *
+ * @param[out] val
+ * Value of the HW field
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_get_field_rel(uint64_t *obj_data,
+ const struct hcapi_cfa_layout *layout,
+ uint16_t field_id, int16_t bitpos_adj,
+ int16_t bitlen_adj, uint64_t *val);
+
+/**
+ * Get the length of the layout in words
+ *
+ * @param[in] layout
+ * A pointer to the layout to determine the number of words
+ * required
+ *
+ * @return
+ * number of words needed for the given layout
+ */
+uint16_t cfa_hw_get_wordlen(const struct hcapi_cfa_layout *layout);
+
+/**
+ * This function is used to initialize a layout_contents structure
+ *
+ * The struct hcapi_cfa_key_layout is complex as there are three
+ * layers of abstraction. Each of those layer need to be properly
+ * initialized.
+ *
+ * @param[in] contents
+ * A pointer of the layout contents to initialize
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_init_key_contents(struct hcapi_cfa_key_layout_contents *contents);
+
+/**
+ * This function is used to validate a key template
+ *
+ * The struct hcapi_cfa_key_template is complex as there are three
+ * layers of abstraction. Each of those layer need to be properly
+ * validated.
+ *
+ * @param[in] key_template
+ * A pointer of the key template contents to validate
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_is_valid_key_template(struct hcapi_cfa_key_template *key_template);
+
+/**
+ * This function is used to validate a key layout
+ *
+ * The struct hcapi_cfa_key_layout is complex as there are three
+ * layers of abstraction. Each of those layer need to be properly
+ * validated.
+ *
+ * @param[in] key_layout
+ * A pointer of the key layout contents to validate
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int hcapi_cfa_is_valid_key_layout(struct hcapi_cfa_key_layout *key_layout);
+
/**
* This function is used to hash E/EM keys
*
new file mode 100644
@@ -0,0 +1,92 @@
+#
+# Copyright(c) 2019-2021 Broadcom Limited, all rights reserved
+# Contains proprietary and confidential information.
+#
+# This source file is the property of Broadcom Limited, and
+# may not be copied or distributed in any isomorphic form without
+# the prior written consent of Broadcom Limited.
+#
+
+# Needed for compilation with chip-specific regdef.h
+add_definitions(-DFIRMWARE_VIEW=1)
+
+# Platform specific defines
+if (cfa_p70)
+ add_definitions(-DSUPPORT_CFA_HW_P70=1)
+ set(PXX_FOLDER p70)
+ set (tsm_needed 1)
+ set (mm_needed 1)
+endif ()
+
+if (cfa_p80)
+ add_definitions(-DSUPPORT_CFA_HW_P80=1)
+ set(PXX_FOLDER p80)
+ set (tcm_needed 1)
+endif ()
+
+# Reset Doc dir variables
+set(CFA_API_DOC_DIRS "" CACHE INTERNAL "")
+set(CFA_DESIGN_DOC_DIRS "" CACHE INTERNAL "")
+set(CFA_UT_DOC_DIRS "" CACHE INTERNAL "")
+
+# Include sub directories
+
+if (idm_needed)
+ add_subdirectory(idm)
+ set(idm_libs cfa-idm-lib cfa-idm-lib-ut)
+endif ()
+
+if (tbm_needed)
+ add_subdirectory(tbm)
+ set(tbm_libs cfa-tbm-lib cfa-tbm-lib-ut)
+endif ()
+
+if (gim_needed)
+ add_subdirectory(gim)
+ set(gim_libs cfa-gim-lib cfa-gim-lib-ut)
+endif ()
+
+if (mm_needed)
+ add_subdirectory(mm)
+ set(mm_libs cfa-mm-lib cfa-mm-lib-ut)
+endif ()
+
+if (tsm_needed)
+ add_subdirectory(tpm)
+ add_subdirectory(tim)
+ set(cfa-tim-lib cfa-tim-lib-ut cfa-tpm-lib cfa-tpm-lib-ut)
+endif ()
+
+if (tcm_needed)
+ add_subdirectory(tcm)
+ set(tcm_libs cfa-tcm-lib cfa-tcm-lib-ut)
+endif ()
+
+if (rdm_needed)
+ add_subdirectory(rdm)
+ set(rdm_libs cfa-rdm-lib cfa-rdm-lib-ut)
+endif ()
+
+# Update Doxygen dirs for api documentation
+#set(CFA_API_DOC_DIRS ${CFA_API_DOC_DIRS}
+# ${CMAKE_CURRENT_SOURCE_DIR}/include
+# CACHE INTERNAL "")
+
+# Update Doxygen dirs for design documentation
+#set(CFA_DESIGN_DOC_DIRS ${CFA_DESIGN_DOC_DIRS}
+# ${CMAKE_CURRENT_SOURCE_DIR}/include
+# CACHE INTERNAL "")
+
+# Include docs
+#if (DOXYGEN_FOUND)
+# add_subdirectory(docs)
+# add_custom_target(cfa-v3-docs
+# DEPENDS hcapi-cfa-api-docs
+# hcapi-cfa-design-docs
+# hcapi-cfa-ut-docs
+# )
+#endif (DOXYGEN_FOUND)
+
+add_custom_target(cfa-v3-libs
+ ALL
+ DEPENDS ${tpm_libs} ${tim_libs} ${mm_libs})
new file mode 100644
@@ -0,0 +1,42 @@
+/****************************************************************************
+ * Copyright(c) 2022 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * @file cfa_bld_mpc.c
+ *
+ * @brief CFA Builder MPC binding api
+ */
+
+#include <errno.h>
+#include "cfa_bld.h"
+#include "host/cfa_bld_mpcops.h"
+
+#if SUPPORT_CFA_HW_P70
+#include "cfa_bld_p70_mpcops.h"
+#endif
+
+int cfa_bld_mpc_bind(enum cfa_ver hw_ver, struct cfa_bld_mpcinfo *mpcinfo)
+{
+ if (!mpcinfo)
+ return -EINVAL;
+
+ switch (hw_ver) {
+ case CFA_P40:
+ case CFA_P45:
+ case CFA_P58:
+ case CFA_P59:
+ return -ENOTSUP;
+ case CFA_P70:
+#if SUPPORT_CFA_HW_P70
+ return cfa_bld_p70_mpc_bind(hw_ver, mpcinfo);
+#else
+ return -ENOTSUP;
+#endif
+ default:
+ return -EINVAL;
+ }
+}
new file mode 100644
@@ -0,0 +1,578 @@
+/****************************************************************************
+ * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * @file cfa_bld_defs.h
+ *
+ * @brief CFA Builder library structure definitions and API
+ */
+
+#ifndef _CFA_BLD_DEFS_H_
+#define _CFA_BLD_DEFS_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "cfa_resources.h"
+#include "cfa_types.h"
+
+/**
+ * @addtogroup CFA_BLD CFA Builder Library
+ * \ingroup CFA_V3
+ * The CFA builder library is a set of APIs provided the following services:
+ *
+ * 1. Provide users generic put service to convert software programming data
+ * into a hardware data bit stream according to a HW layout representation,
+ * or generic get service to extract value of a field or values of a number
+ * of fields from the raw hardware data bit stream according to a HW layout.
+ *
+ * - A software programming data is represented in {field_idx, val}
+ * structure.
+ * - A HW layout is represented with array of CFA field structures with
+ * {bitpos, bitlen} and identified by a layout id corresponding to a CFA
+ * HW table.
+ * - A HW data bit stream are bits that is formatted according to a HW
+ * layout representation.
+ *
+ * 2. Provide EM/WC key and action related service APIs to compile layout,
+ * init, and manipulate key and action data objects.
+ *
+ * 3. Provide CFA mid-path message building APIs. (TBD)
+ *
+ * The CFA builder library is designed to run in the primate firmware and also
+ * as part of the following host base diagnostic software.
+ * - Lcdiag
+ * - Truflow CLI
+ * - coredump decorder
+ *
+ * @{
+ */
+
+/** @name CFA Builder Common Definition
+ * CFA builder common structures and enumerations
+ */
+
+/**@{*/
+/**
+ * CFA HW KEY CONTROL OPCODE definition
+ */
+enum cfa_key_ctrlops {
+ CFA_KEY_CTRLOPS_INSERT, /**< insert WC control bits */
+ CFA_KEY_CTRLOPS_STRIP, /**< strip WC control bits */
+ CFA_KEY_CTRLOPS_SWAP, /**< swap EM cache lines */
+ CFA_KEY_CTRLOPS_MAX
+};
+
+/**
+ * CFA HW field structure definition
+ */
+struct cfa_field {
+ /** [in] Starting bit position pf the HW field within a HW table
+ * entry.
+ */
+ uint16_t bitpos;
+ /** [in] Number of bits for the HW field. */
+ uint16_t bitlen;
+};
+
+/**
+ * CFA HW table entry layout structure definition
+ */
+struct cfa_layout {
+ /** [out] Bit order of layout
+ * if swap_order_bitpos is non-zero, the bit order of the layout
+ * will be swapped after this bit. swap_order_bitpos must be a
+ * multiple of 64. This is currently only used for inlined action
+ * records where the AR is lsb and the following inlined actions
+ * must be msb.
+ */
+ bool is_msb_order;
+ /** [out] Reverse is_msb_order after this bit if non-zero */
+ uint16_t swap_order_bitpos;
+ /** [out] Size in bits of entry */
+ uint32_t total_sz_in_bits;
+ /** [in/out] data pointer of the HW layout fields array */
+ struct cfa_field *field_array;
+ /** [out] number of HW field entries in the HW layout field array */
+ uint32_t array_sz;
+ /** [out] layout_id - layout id associated with the layout */
+ uint16_t layout_id;
+};
+
+/**
+ * CFA HW data object definition
+ */
+struct cfa_data_obj {
+ /** [in] HW field identifier. Used as an index to a HW table layout */
+ uint16_t field_id;
+ /** [in] Value of the HW field */
+ uint64_t val;
+};
+
+/**
+ * CFA HW key buffer definition
+ */
+struct cfa_key_obj {
+ /** [in] pointer to the key data buffer */
+ uint32_t *data;
+ /** [in] buffer len in bytes */
+ uint32_t data_len_bytes;
+ /** [out] Data length in bits
+ * When cfa_key_obj is passed as an output parameter, the updated
+ * key length (if the key length changes) is returned in this field by the
+ * key processing api (e.g cfa_bld_key_transform)
+ * When cfa_key_obj is passed as an input parameter, this field is unused
+ * and need not be initialized by the caller.
+ */
+ uint32_t data_len_bits;
+ /** [in] Pointer to the key layout */
+ struct cfa_key_layout *layout;
+};
+
+/**
+ * CFA HW layout table definition
+ */
+struct cfa_layout_tbl {
+ /** [out] data pointer to an array of fix formatted layouts supported.
+ * The index to the array is either the CFA resource subtype or
+ * remap table ID
+ */
+ const struct cfa_layout *layouts;
+ /** [out] number of fix formatted layouts in the layout array */
+ uint16_t num_layouts;
+};
+
+/**
+ * key layout consist of field array, key bitlen, key ID, and other meta data
+ * pertain to a key
+ */
+struct cfa_key_layout {
+ /** [in/out] key layout data */
+ struct cfa_layout *layout;
+ /** [out] actual key size in number of bits */
+ uint16_t bitlen;
+ /** [out] key identifier and this field is only valid for device
+ * that supports fix key formats
+ */
+ uint16_t id;
+ /** [out] Identified the key layout is WC TCAM key */
+ bool is_wc_tcam_key;
+ /** [out] Identify if the key template will be use for IPv6 Keys.
+ *
+ * Note: This is important for Thor2 as the field length for the FlowId
+ * is dependent on the L3 flow type. For Thor2 for IPv4 Keys, the Flow
+ * Id field is 16 bits, for all other types (IPv6, ARP, PTP, EAP, RoCE,
+ * FCoE, UPAR), the Flow Id field length is 20 bits.
+ */
+ bool is_ipv6_key;
+ /** [out] total number of slices, valid for WC TCAM key only. It can be
+ * used by the user to pass in the num_slices to write to the hardware.
+ */
+ uint16_t num_slices;
+};
+
+/**
+ * CFA HW key table definition
+ *
+ * Applicable to EEM and on-chip EM table only.
+ */
+struct cfa_key_tbl {
+ /** [in] For EEM, this is the KEY0 base mem pointer. For off-chip EM,
+ * this is the base mem pointer of the key table.
+ */
+ uint8_t *base0;
+ /** [in] total size of the key table in bytes. For EEM, this size is
+ * same for both KEY0 and KEY1 table.
+ */
+ uint32_t size;
+ /** [in] number of key buckets, applicable for newer chips */
+ uint32_t num_buckets;
+ /** [in] For EEM, this is KEY1 base mem pointer. Fo on-chip EM,
+ * this is the key record memory base pointer within the key table,
+ * applicable for newer chip
+ */
+ uint8_t *base1;
+ /** [in] Optional - If the table is managed by a Backing Store
+ * database, then this object can be use to configure the EM Key.
+ */
+ struct cfa_bs_db *bs_db;
+ /** [in] Page size for EEM tables */
+ uint32_t page_size;
+};
+
+/**
+ * CFA HW key data definition
+ */
+struct cfa_key_data {
+ /** [in] For on-chip key table, it is the offset in unit of smallest
+ * key. For off-chip key table, it is the byte offset relative
+ * to the key record memory base and adjusted for page and entry size.
+ */
+ uint32_t offset;
+ /** [in] HW key data buffer pointer */
+ uint8_t *data;
+ /** [in] size of the key in bytes */
+ uint16_t size;
+ /** [in] optional table scope ID */
+ uint8_t tbl_scope;
+ /** [in] the fid owner of the key */
+ uint64_t metadata;
+ /** [in] stored with the bucket which can be used to by
+ * the caller to retreved later via the GET HW OP.
+ */
+};
+
+/**
+ * CFA HW key location definition
+ */
+struct cfa_key_loc {
+ /** [out] on-chip EM bucket offset or off-chip EM bucket mem pointer */
+ uint64_t bucket_mem_ptr;
+ /** [out] off-chip EM key offset mem pointer */
+ uint64_t mem_ptr;
+ /** [out] index within the array of the EM buckets */
+ uint32_t bucket_mem_idx;
+ /** [out] index within the EM bucket */
+ uint8_t bucket_idx;
+ /** [out] index within the EM records */
+ uint32_t mem_idx;
+};
+
+/**
+ * Action record info
+ */
+struct cfa_action_addr {
+ /** [in] action SRAM block ID for on-chip action records or table
+ * scope of the action backing store
+ */
+ uint16_t blk_id;
+ /** [in] ar_id or cache line aligned address offset for the action
+ * record
+ */
+ uint32_t offset;
+};
+
+/**
+ * Action object definition
+ */
+struct cfa_action_obj {
+ /** [in] pointer to the action data buffer */
+ uint64_t *data;
+ /** [in] buffer len in bytes */
+ uint32_t len;
+ /** [in] pointer to the action layout */
+ struct cfa_action_layout *layout;
+};
+
+/**
+ * action layout consist of field array, action wordlen and action format ID
+ */
+struct cfa_action_layout {
+ /** [in] action identifier */
+ uint16_t id;
+ /** [out] action layout data */
+ struct cfa_layout *layout;
+ /** [out] actual action record size in number of bits */
+ uint16_t bitlen;
+};
+
+/**@}*/
+
+/** @name CFA Builder PUT_FIELD APIs
+ * CFA Manager apis used for generating hw layout specific data objects that
+ * can be programmed to the hardware
+ */
+
+/**@{*/
+/**
+ * @brief This API provides the functionality to program a specified value to a
+ * HW field based on the provided programming layout.
+ *
+ * @param[in,out] data_buf
+ * A data pointer to a CFA HW key/mask data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in] field_id
+ * ID of the HW field to be programmed
+ *
+ * @param[in] val
+ * Value of the HW field to be programmed
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_put_field(uint64_t *data_buf, const struct cfa_layout *layout,
+ uint16_t field_id, uint64_t val);
+
+/**
+ * @brief This API provides the functionality to program an array of field
+ * values with corresponding field IDs to a number of profiler sub-block fields
+ * based on the fixed profiler sub-block hardware programming layout.
+ *
+ * @param[in, out] obj_data
+ * A pointer to a CFA profiler key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in] field_tbl
+ * A pointer to an array that consists of the object field
+ * ID/value pairs
+ *
+ * @param[in] field_tbl_sz
+ * Number of entries in the table
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_put_fields(uint64_t *obj_data, const struct cfa_layout *layout,
+ struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz);
+
+/**
+ * @brief This API provides the functionality to program an array of field
+ * values with corresponding field IDs to a number of profiler sub-block fields
+ * based on the fixed profiler sub-block hardware programming layout. This
+ * API will swap the n byte blocks before programming the field array.
+ *
+ * @param[in, out] obj_data
+ * A pointer to a CFA profiler key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in] field_tbl
+ * A pointer to an array that consists of the object field
+ * ID/value pairs
+ *
+ * @param[in] field_tbl_sz
+ * Number of entries in the table
+ *
+ * @param[in] data_size
+ * size of the data in bytes
+ *
+ * @param[in] n
+ * block size in bytes
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_put_fields_swap(uint64_t *obj_data, const struct cfa_layout *layout,
+ struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz,
+ uint16_t data_size, uint16_t n);
+
+/**
+ * @brief This API provides the functionality to write a value to a
+ * field within the bit position and bit length of a HW data
+ * object based on a provided programming layout.
+ *
+ * @param[in, out] obj_data
+ * A pointer of the action object to be initialized
+ *
+ * @param[in] layout
+ * A pointer of the programming layout
+ *
+ * @param field_id
+ * [in] Identifier of the HW field
+ *
+ * @param[in] bitpos_adj
+ * Bit position adjustment value
+ *
+ * @param[in] bitlen_adj
+ * Bit length adjustment value
+ *
+ * @param[in] val
+ * HW field value to be programmed
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_put_field_rel(uint64_t *obj_data, const struct cfa_layout *layout,
+ uint16_t field_id, int16_t bitpos_adj, int16_t bitlen_adj,
+ uint64_t val);
+
+/**@}*/
+
+/** @name CFA Builder GET_FIELD APIs
+ * CFA Manager apis used for extract hw layout specific fields from CFA HW
+ * data objects
+ */
+
+/**@{*/
+/**
+ * @brief The API provides the functionality to get bit offset and bit
+ * length information of a field from a programming layout.
+ *
+ * @param[in] layout
+ * A pointer of the action layout
+ *
+ * @param[in] field_id
+ * The field for which to retrieve the slice
+ *
+ * @param[out] slice
+ * A pointer to the action offset info data structure
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_get_slice(const struct cfa_layout *layout, uint16_t field_id,
+ struct cfa_field *slice);
+
+/**
+ * @brief This API provides the functionality to read the value of a
+ * CFA HW field from CFA HW data object based on the hardware
+ * programming layout.
+ *
+ * @param[in] obj_data
+ * A pointer to a CFA HW key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in] field_id
+ * ID of the HW field to be programmed
+ *
+ * @param[out] val
+ * Value of the HW field
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_get_field(uint64_t *obj_data, const struct cfa_layout *layout,
+ uint16_t field_id, uint64_t *val);
+
+/**
+ * @brief This API provides the functionality to read 128-bit value of
+ * a CFA HW field from CFA HW data object based on the hardware
+ * programming layout.
+ *
+ * @param[in] obj_data
+ * A pointer to a CFA HW key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in] field_id
+ * ID of the HW field to be programmed
+ *
+ * @param[out] val_msb
+ * Msb value of the HW field
+ *
+ * @param[out] val_lsb
+ * Lsb value of the HW field
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_get128_field(uint64_t *obj_data, const struct cfa_layout *layout,
+ uint16_t field_id, uint64_t *val_msb, uint64_t *val_lsb);
+
+/**
+ * @brief This API provides the functionality to read a number of
+ * HW fields from a CFA HW data object based on the hardware
+ * programming layout.
+ *
+ * @param[in] obj_data
+ * A pointer to a CFA profiler key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in, out] field_tbl
+ * A pointer to an array that consists of the object field
+ * ID/value pairs
+ *
+ * @param[in] field_tbl_sz
+ * Number of entries in the table
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_get_fields(uint64_t *obj_data, const struct cfa_layout *layout,
+ struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz);
+
+/**
+ * @brief This API provides the functionality to read a number of
+ * HW fields from a CFA HW data object based on the hardware
+ * programming layout.This API will swap the n byte blocks before
+ * retrieving the field array.
+ *
+ * @param[in] obj_data
+ * A pointer to a CFA profiler key/mask object data
+ *
+ * @param[in] layout
+ * A pointer to CFA HW programming layout
+ *
+ * @param[in, out] field_tbl
+ * A pointer to an array that consists of the object field
+ * ID/value pairs
+ *
+ * @param[in] field_tbl_sz
+ * Number of entries in the table
+ *
+ * @param[in] data_size
+ * size of the data in bytes
+ *
+ * @param[in] n
+ * block size in bytes
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_get_fields_swap(uint64_t *obj_data, const struct cfa_layout *layout,
+ struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz,
+ uint16_t data_size, uint16_t n);
+
+/**
+ * @brief Get a value to a specific location relative to a HW field
+ * This API provides the functionality to read HW field from
+ * a section of a HW data object identified by the bit position
+ * and bit length from a given programming layout in order to avoid
+ * reading the entire HW data object.
+ *
+ * @param[in] obj_data
+ * A pointer of the data object to read from
+ *
+ * @param[in] layout
+ * A pointer of the programming layout
+ *
+ * @param[in] field_id
+ * Identifier of the HW field
+ *
+ * @param[in] bitpos_adj
+ * Bit position adjustment value
+ *
+ * @param[in] bitlen_adj
+ * Bit length adjustment value
+ *
+ * @param[out] val
+ * Value of the HW field
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_get_field_rel(uint64_t *obj_data, const struct cfa_layout *layout,
+ uint16_t field_id, int16_t bitpos_adj, int16_t bitlen_adj,
+ uint64_t *val);
+
+/**
+ * @brief Get the length of the layout in words
+ *
+ * @param[in] layout
+ * A pointer to the layout to determine the number of words
+ * required
+ *
+ * @return
+ * number of words needed for the given layout
+ */
+uint16_t cfa_get_wordlen(const struct cfa_layout *layout);
+
+/**@}*/
+
+/**@}*/
+#endif /* _CFA_BLD_DEFS_H_*/
new file mode 100644
@@ -0,0 +1,524 @@
+/****************************************************************************
+ * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * @file cfa_bld.h
+ *
+ * @brief CFA HW independent Builder library public api header
+ */
+
+#ifndef _CFA_BLD_H_
+#define _CFA_BLD_H_
+
+#include "sys_util.h"
+#include "cfa_bld_defs.h"
+#include "cfa_bld_field_ids.h"
+
+/**
+ * @addtogroup CFA_BLD CFA Builder Library
+ * \ingroup CFA_V3
+ * @{
+ */
+
+/**
+ * Maximum key array size
+ */
+#define CFA_V3_KEY_MAX_FIELD_CNT \
+ MAX((uint16_t)CFA_BLD_EM_KEY_LAYOUT_MAX_FLD, \
+ (uint16_t)CFA_BLD_WC_TCAM_FKB_MAX_FLD)
+#define CFA_V3_ACT_MAX_TEMPLATE_SZ sizeof(struct cfa_bld_action_template)
+
+/** @name CFA Builder Templates
+ * CFA builder action and key templates definition and enumerations
+ */
+
+/**@{*/
+enum action_type {
+ /** Select this type to build an Full Action Record Object
+ */
+ CFA_BLD_ACT_OBJ_TYPE_FULL_ACT,
+ /** Select this type to build an Compact Action Record Object
+ */
+ CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT,
+ /** Select this type to build an MCG Action Record Object
+ */
+ CFA_BLD_ACT_OBJ_TYPE_MCG_ACT,
+ /** Select this type to build Standalone Modify Action Record Object */
+ CFA_BLD_ACT_OBJ_TYPE_MODIFY,
+ /** Select this type to build Standalone Stat Action Record Object */
+ CFA_BLD_ACT_OBJ_TYPE_STAT,
+ /** Select this type to build Standalone Source Action Record Object */
+ CFA_BLD_ACT_OBJ_TYPE_SRC_PROP,
+ /** Select this type to build Standalone Encap Action Record Object */
+ CFA_BLD_ACT_OBJ_TYPE_ENCAP,
+};
+
+enum stat_op {
+ /** Set to statistic to ingress to CFA
+ */
+ CFA_BLD_STAT_OP_INGRESS = 0,
+ /** Set to statistic to egress from CFA
+ */
+ CFA_BLD_STAT_OP_EGRESS = 1,
+};
+
+enum stat_type {
+ /** Set to statistic to Foward packet count(64b)/Foward byte
+ * count(64b)
+ */
+ CFA_BLD_STAT_COUNTER_SIZE_16B = 0,
+ /** Set to statistic to Forward packet count(64b)/Forward byte
+ * count(64b)/ TCP Flags(16b)/Timestamp(32b)
+ */
+ CFA_BLD_STAT_COUNTER_SIZE_24B = 1,
+ /** Set to statistic to Forward packet count(64b)/Forward byte
+ * count(64b)/Meter(drop or red) packet count(64b)/Meter(drop
+ * or red) byte count(64b)
+ */
+ CFA_BLD_STAT_COUNTER_SIZE_32B = 2,
+ /** Set to statistic to Forward packet count(64b)/Forward byte
+ * count(64b)/Meter(drop or red) packet count(38b)/Meter(drop
+ * or red) byte count(42b)/TCP Flags(16b)/Timestamp(32b)
+ */
+ CFA_BLD_STAT_COUNTER_SIZE_32B_ALL = 3,
+};
+
+enum encap_vtag {
+ CFA_BLD_ACT_ENCAP_VTAGS_PUSH_0 = 0,
+ CFA_BLD_ACT_ENCAP_VTAGS_PUSH_1,
+ CFA_BLD_ACT_ENCAP_VTAGS_PUSH_2
+};
+
+enum encap_l3 {
+ /** Set to disable any L3 encapsulation
+ * processing, default
+ */
+ CFA_BLD_ACT_ENCAP_L3_NONE = 0,
+ /** Set to enable L3 IPv4 encapsulation
+ */
+ CFA_BLD_ACT_ENCAP_L3_IPV4 = 4,
+ /** Set to enable L3 IPv6 encapsulation
+ */
+ CFA_BLD_ACT_ENCAP_L3_IPV6 = 5,
+ /** Set to enable L3 MPLS 8847 encapsulation
+ */
+ CFA_BLD_ACT_ENCAP_L3_MPLS_8847 = 6,
+ /** Set to enable L3 MPLS 8848 encapsulation
+ */
+ CFA_BLD_ACT_ENCAP_L3_MPLS_8848 = 7
+};
+
+enum encap_tunnel {
+ /** Set to disable Tunnel header encapsulation
+ * processing, default
+ */
+ CFA_BLD_ACT_ENCAP_TNL_NONE = 0,
+ /** Set to enable Tunnel Generic Full header
+ * encapsulation
+ */
+ CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL,
+ /** Set to enable VXLAN header encapsulation
+ */
+ CFA_BLD_ACT_ENCAP_TNL_VXLAN,
+ /** Set to enable NGE (VXLAN2) header encapsulation
+ */
+ CFA_BLD_ACT_ENCAP_TNL_NGE,
+ /** Set to enable NVGRE header encapsulation
+ */
+ CFA_BLD_ACT_ENCAP_TNL_NVGRE,
+ /** Set to enable GRE header encapsulation
+ */
+ CFA_BLD_ACT_ENCAP_TNL_GRE,
+ /** Set to enable Generic header after Tunnel
+ * L4 encapsulation
+ */
+ CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TL4,
+ /** Set to enable Generic header after Tunnel
+ * encapsulation
+ */
+ CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TNL
+};
+
+enum source_rec_type {
+ /** Set to Source MAC Address
+ */
+ CFA_BLD_SOURCE_MAC = 0,
+ /** Set to Source MAC and IPv4 Addresses
+ */
+ CFA_BLD_SOURCE_MAC_IPV4 = 1,
+ /** Set to Source MAC and IPv6 Addresses
+ */
+ CFA_BLD_SOURCE_MAC_IPV6 = 2,
+};
+
+/**
+ * From CFA phase 7.0 onwards, setting the modify vector bit
+ * 'ACT_MODIFY_TUNNEL_MODIFY' requires corresponding data fields to be
+ * set. This enum defines the parameters that determine the
+ * layout of this associated data fields. This structure
+ * is not used for versions older than CFA Phase 7.0 and setting
+ * the 'ACT_MODIFY_TUNNEL_MODIFY' bit will just delete the internal tunnel
+ */
+enum tunnel_modify_mode {
+ /* No change to tunnel protocol */
+ CFA_BLD_ACT_MOD_TNL_NO_PROTO_CHANGE = 0,
+ /* 8-bit tunnel protocol change */
+ CFA_BLD_ACT_MOD_TNL_8B_PROTO_CHANGE = 1,
+ /* 16-bit tunnel protocol change */
+ CFA_BLD_ACT_MOD_TNL_16B_PROTO_CHANGE = 2,
+ CFA_BLD_ACT_MOD_TNL_MAX
+};
+
+/**
+ * Action object template structure
+ *
+ * Template structure presents data fields that are necessary to know
+ * at the beginning of Action Builder (AB) processing. Like before the
+ * AB compilation. One such example could be a template that is
+ * flexible in size (Encap Record) and the presence of these fields
+ * allows for determining the template size as well as where the
+ * fields are located in the record.
+ *
+ * The template may also present fields that are not made visible to
+ * the caller by way of the action fields.
+ *
+ * Template fields also allow for additional checking on user visible
+ * fields. One such example could be the encap pointer behavior on a
+ * CFA_BLD_ACT_OBJ_TYPE_ACT or CFA_BLD_ACT_OBJ_TYPE_ACT_SRAM.
+ */
+struct cfa_bld_action_template {
+ /** Action Object type
+ *
+ * Controls the type of the Action Template
+ */
+ enum action_type obj_type;
+
+ /** Action Control
+ *
+ * Controls the internals of the Action Template
+ *
+ * act is valid when:
+ * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT)
+ * ||
+ * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT))
+ *
+ * Specifies whether each action is to be in-line or not.
+ */
+ struct {
+ /** Set to true to enable statistics
+ */
+ uint8_t stat_enable;
+ /** Set to true to enable statistics to be inlined
+ */
+ uint8_t stat_inline;
+ /** Set to true to enable statistics 1
+ */
+ uint8_t stat1_enable;
+ /** Set to true to enable statistics 1 to be inlined
+ */
+ uint8_t stat1_inline;
+ /** Set to true to enable encapsulation
+ */
+ uint8_t encap_enable;
+ /** Set to true to enable encapsulation to be inlined
+ */
+ uint8_t encap_inline;
+ /** Set to true to align the encap record to cache
+ * line
+ */
+ uint8_t encap_align;
+ /** Set to true to source
+ */
+ uint8_t source_enable;
+ /** Set to true to enable source to be inlined
+ */
+ uint8_t source_inline;
+ /** Set to true to enable modfication
+ */
+ uint8_t mod_enable;
+ /** Set to true to enable modify to be inlined
+ */
+ uint8_t mod_inline;
+ /** Set to true to enable subsequent MCGs
+ */
+ uint8_t mcg_subseq_enable;
+ } act;
+
+ /** Statistic Control
+ * Controls the type of statistic the template is describing
+ *
+ * stat is valid when:
+ * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) ||
+ * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT)) &&
+ * act.stat_enable || act.stat_inline)
+ */
+ struct {
+ enum stat_op op;
+ enum stat_type type;
+ } stat;
+
+ /** Encap Control
+ * Controls the type of encapsulation the template is
+ * describing
+ *
+ * encap is valid when:
+ * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) ||
+ * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT) &&
+ * act.encap_enable || act.encap_inline)
+ */
+ struct {
+ /** Set to true to enable L2 capability in the
+ * template
+ */
+ uint8_t l2_enable;
+ /** vtag controls the Encap Vector - VTAG Encoding, 4 bits
+ *
+ * <ul>
+ * <li> CFA_BLD_ACT_ENCAP_VTAGS_PUSH_0, default, no VLAN
+ * Tags applied
+ * <li> CFA_BLD_ACT_ENCAP_VTAGS_PUSH_1, adds capability to
+ * set 1 VLAN Tag. Action Template compile adds
+ * the following field to the action object
+ * TF_ER_VLAN1
+ * <li> CFA_BLD_ACT_ENCAP_VTAGS_PUSH_2, adds capability to
+ * set 2 VLAN Tags. Action Template compile adds
+ * the following fields to the action object
+ * TF_ER_VLAN1 and TF_ER_VLAN2
+ * </ul>
+ */
+ enum encap_vtag vtag;
+
+ /*
+ * The remaining fields are NOT supported when
+ * direction is RX and ((obj_type ==
+ * CFA_BLD_ACT_OBJ_TYPE_ACT) && act.encap_enable).
+ * cfa_bld_devops.act_compile_layout will perform the
+ * checking and skip remaining fields.
+ */
+ /** L3 Encap controls the Encap Vector - L3 Encoding,
+ * 3 bits. Defines the type of L3 Encapsulation the
+ * template is describing.
+ * <ul>
+ * <li> CFA_BLD_ACT_ENCAP_L3_NONE, default, no L3
+ * Encapsulation processing.
+ * <li> CFA_BLD_ACT_ENCAP_L3_IPV4, enables L3 IPv4
+ * Encapsulation.
+ * <li> CFA_BLD_ACT_ENCAP_L3_IPV6, enables L3 IPv6
+ * Encapsulation.
+ * <li> CFA_BLD_ACT_ENCAP_L3_MPLS_8847, enables L3 MPLS
+ * 8847 Encapsulation.
+ * <li> CFA_BLD_ACT_ENCAP_L3_MPLS_8848, enables L3 MPLS
+ * 8848 Encapsulation.
+ * </ul>
+ */
+ enum encap_l3 l3;
+
+#define CFA_BLD_ACT_ENCAP_MAX_MPLS_LABELS 8
+ /** 1-8 labels, valid when
+ * (l3 == CFA_BLD_ACT_ENCAP_L3_MPLS_8847) ||
+ * (l3 == CFA_BLD_ACT_ENCAP_L3_MPLS_8848)
+ *
+ * MAX number of MPLS Labels 8.
+ */
+ uint8_t l3_num_mpls_labels;
+
+ /** Set to true to enable L4 capability in the
+ * template.
+ *
+ * true adds TF_EN_UDP_SRC_PORT and
+ * TF_EN_UDP_DST_PORT to the template.
+ */
+ uint8_t l4_enable;
+
+ /** Tunnel Encap controls the Encap Vector - Tunnel
+ * Encap, 3 bits. Defines the type of Tunnel
+ * encapsulation the template is describing
+ * <ul>
+ * <li> CFA_BLD_ACT_ENCAP_TNL_NONE, default, no Tunnel
+ * Encapsulation processing.
+ * <li> CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL
+ * <li> CFA_BLD_ACT_ENCAP_TNL_VXLAN. NOTE: Expects
+ * l4_enable set to true;
+ * <li> CFA_BLD_ACT_ENCAP_TNL_NGE. NOTE: Expects l4_enable
+ * set to true;
+ * <li> CFA_BLD_ACT_ENCAP_TNL_NVGRE. NOTE: only valid if
+ * l4_enable set to false.
+ * <li> CFA_BLD_ACT_ENCAP_TNL_GRE.NOTE: only valid if
+ * l4_enable set to false.
+ * <li> CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TL4
+ * <li> CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TNL
+ * </ul>
+ */
+ enum encap_tunnel tnl;
+
+#define CFA_BLD_ACT_ENCAP_MAX_TUNNEL_GENERIC_SIZE 128
+ /** Number of bytes of generic tunnel header,
+ * valid when
+ * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL) ||
+ * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TL4) ||
+ * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TNL)
+ */
+ uint8_t tnl_generic_size;
+
+#define CFA_BLD_ACT_ENCAP_MAX_OPLEN 15
+ /** Number of 32b words of nge options,
+ * valid when
+ * (tnl == CFA_BLD_ACT_ENCAP_TNL_NGE)
+ */
+ uint8_t tnl_nge_op_len;
+
+ /** Set to true to enable SPDNIC tunnel
+ * template,
+ * valid when
+ * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL)
+ */
+ uint8_t spdnic_enable;
+
+ /** SPDNIC flags field,
+ * valid when
+ * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL)
+ */
+ uint8_t tnl_spdnic_flags;
+
+ /** Set to true to enable MAC/VLAN/IP/TNL overrides in the
+ * template
+ */
+ bool encap_override;
+ /* Currently not planned */
+ /* Custom Header */
+ /* uint8_t custom_enable; */
+ } encap;
+
+ /** Modify Control
+ *
+ * Controls the type of the Modify Action the template is
+ * describing
+ *
+ * modify is valid when:
+ * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) ||
+ * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT) &&
+ * act.modify_enable || act.modify_inline)
+ */
+/** Set to enable Modify of Metadata
+ */
+#define CFA_BLD_ACT_MODIFY_META 0x1
+/** Set to enable Delete of Outer VLAN
+ */
+#define CFA_BLD_ACT_MODIFY_DEL_OVLAN 0x2
+/** Set to enable Delete of Inner VLAN
+ */
+#define CFA_BLD_ACT_MODIFY_DEL_IVLAN 0x4
+/** Set to enable Replace or Add of Outer VLAN
+ */
+#define CFA_BLD_ACT_MODIFY_REPL_ADD_OVLAN 0x8
+/** Set to enable Replace or Add of Inner VLAN
+ */
+#define CFA_BLD_ACT_MODIFY_REPL_ADD_IVLAN 0x10
+/** Set to enable Modify of TTL
+ */
+#define CFA_BLD_ACT_MODIFY_TTL_UPDATE 0x20
+/** Set to enable delete of INT Tunnel
+ */
+#define CFA_BLD_ACT_MODIFY_DEL_INT_TNL 0x40
+/** For phase 7.0 this bit can be used to modify the tunnel
+ * protocol in addition to deleting internal or outer tunnel
+ */
+#define CFA_BLD_ACT_MODIFY_TUNNEL_MODIFY CFA_BLD_ACT_MODIFY_DEL_INT_TNL
+/** Set to enable Modify of Field
+ */
+#define CFA_BLD_ACT_MODIFY_FIELD 0x80
+/** Set to enable Modify of Destination MAC
+ */
+#define CFA_BLD_ACT_MODIFY_DMAC 0x100
+/** Set to enable Modify of Source MAC
+ */
+#define CFA_BLD_ACT_MODIFY_SMAC 0x200
+/** Set to enable Modify of Source IPv6 Address
+ */
+#define CFA_BLD_ACT_MODIFY_SRC_IPV6 0x400
+/** Set to enable Modify of Destination IPv6 Address
+ */
+#define CFA_BLD_ACT_MODIFY_DST_IPV6 0x800
+/** Set to enable Modify of Source IPv4 Address
+ */
+#define CFA_BLD_ACT_MODIFY_SRC_IPV4 0x1000
+/** Set to enable Modify of Destination IPv4 Address
+ */
+#define CFA_BLD_ACT_MODIFY_DST_IPV4 0x2000
+/** Set to enable Modify of L4 Source Port
+ */
+#define CFA_BLD_ACT_MODIFY_SRC_PORT 0x4000
+/** Set to enable Modify of L4 Destination Port
+ */
+#define CFA_BLD_ACT_MODIFY_DST_PORT 0x8000
+ uint16_t modify;
+
+/** Set to enable Modify of KID
+ */
+#define CFA_BLD_ACT_MODIFY_FIELD_KID 0x1
+
+ /* Valid for phase 7.0 or higher */
+ uint16_t field_modify;
+
+ /* Valid for phase 7.0 or higher */
+ enum tunnel_modify_mode tnl_mod_mode;
+
+ /** Source Control
+ *
+ * Controls the type of the Source Action the template is
+ * describing
+ *
+ * source is valid when:
+ * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) ||
+ * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT) &&
+ * act.source_enable || act.source_inline)
+ */
+ enum source_rec_type source;
+};
+
+/**
+ * Key template consists of key fields that can be enabled/disabled
+ * individually.
+ */
+struct cfa_key_template {
+ /** [in] Identify if the key template is for TCAM. If false, the
+ * key template is for EM. This field is mandantory for device that
+ * only support fix key formats.
+ */
+ bool is_wc_tcam_key;
+ /** [in] Identify if the key template will be use for IPv6 Keys.
+ *
+ * Note: This is important for THOR2 as the field length for the FlowId
+ * is dependent on the L3 flow type. For THOR2 for IPv4 Keys, the Flow
+ * Id field is 16 bits, for all other types (IPv6, ARP, PTP, EAP, RoCE,
+ * FCoE, UPAR), the Flow Id field length is 20 bits.
+ */
+ bool is_ipv6_key;
+ /** [in] key field enable field array, set 1 to the corresponding
+ * field enable to make a field valid
+ */
+ uint8_t field_en[CFA_V3_KEY_MAX_FIELD_CNT];
+};
+
+/**
+ * Action template consists of action fields that can be enabled/disabled
+ * individually.
+ */
+struct cfa_action_template {
+ /** [in] CFA version for the action template */
+ enum cfa_ver hw_ver;
+ /** [in] action field enable field array, set 1 to the corresponding
+ * field enable to make a field valid
+ */
+ uint8_t data[CFA_V3_ACT_MAX_TEMPLATE_SZ];
+};
+
+/**@}*/
+
+/**@}*/
+
+#endif /* _CFA_BLD_H_ */
new file mode 100644
@@ -0,0 +1,297 @@
+/****************************************************************************
+ * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * @file cfa_bld_devops.h
+ *
+ * @brief CFA Builder devops interface for host applications
+ */
+
+#ifndef _CFA_BLD_DEVOPS_H_
+#define _CFA_BLD_DEVOPS_H_
+
+#include <stdio.h>
+
+#include "cfa_bld.h"
+#include "cfa_bld_defs.h"
+
+struct cfa_bld_devops;
+
+/**
+ * @addtogroup CFA_BLD CFA Builder Library
+ * \ingroup CFA_V3
+ * @{
+ */
+
+/**
+ * CFA device information
+ */
+struct cfa_bld_devinfo {
+ /** [out] CFA Builder operations function pointer table */
+ const struct cfa_bld_devops *devops;
+};
+
+/**
+ * @name CFA_BLD CFA Builder Host Device OPS API
+ * CFA builder host specific API used by host CFA application to bind
+ * to different CFA devices and access device by using device OPS.
+ */
+
+/**@{*/
+/** CFA bind builder API
+ *
+ * This API retrieves the CFA global device configuration. This API should be
+ * called first before doing any operations to CFA through API. The returned
+ * global device information should be referenced throughout the lifetime of
+ * the CFA application.
+ *
+ * @param[in] hw_ver
+ * hardware version of the CFA
+ *
+ * @param[out] dev_info
+ * CFA global device information
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_bld_bind(enum cfa_ver hw_ver, struct cfa_bld_devinfo *dev_info);
+
+/** CFA device specific function hooks structure
+ *
+ * The following device hooks can be defined; unless noted otherwise, they are
+ * optional and can be filled with a null pointer. The pupose of these hooks
+ * to support CFA device operations for different device variants.
+ */
+struct cfa_bld_devops {
+ /** Get CFA layout for hw fix format tables
+ *
+ * This API takes returns the CFA layout for a given resource type
+ * resource subtype and CFA direction.
+ *
+ * @param[in] rtype
+ * CFA HW resource type. Valid values are CFA_RTYPE_XXX
+ *
+ * @param[in] rsubtype
+ * CFA HW resource sub type for the given resource type 'rtype'
+ * Valid values are CFA_RSUBTYPE_XXX_YYY, where XXX is the resource
+ * type
+ *
+ * @param[in] dir
+ * CFA direction. RX/TX. Note that the returned layout is different
+ * for RX and TX, only for VEB and VSPT tables. For all tables, the
+ * layout is the same for both directions.
+ *
+ * @param[out] layout
+ * Pointer to the table layout to be returned
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ * @note example usage: To get L2 context TCAM table, use
+ * struct cfa_layout *l2ctxt_tcam_layout;
+ * devops->cfa_bld_get_table_layout(CFA_RTYPE_TCAM,
+ * CFA_RSUBTYPE_TCAM_L2CTX,
+ * CFA_TX,
+ * &l2ctxt_tcam_layout);
+ */
+ int (*cfa_bld_get_table_layout)(enum cfa_resource_type rtype,
+ uint8_t rsubtype, enum cfa_dir dir,
+ struct cfa_layout **layout);
+
+ /** Get CFA layout for HW remap tables
+ *
+ * This API takes returns the CFA remap layout for a given tcam
+ * resource sub type, remap type and CFA direction.
+ *
+ * @param[in] st
+ * CFA TCAM table sub types. Valid values are CFA_RSUBTYPE_TCAM_XXX
+ *
+ * @param[in] rmp_tt
+ * CFA Remap table type. See enum cfa_remap_tbl_type
+ *
+ * @param[in] dir
+ * CFA direction. RX/TX.
+ *
+ * @param[out] layout
+ * Pointer to the remap table layout to be returned
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ * @note example usage: To get Profiler TCAM Remap bypass table, use
+ * struct cfa_layout *prof_tcam_rmp_byp_layout;
+ * devops->cfa_bld_get_remap_table_layout(CFA_RSUBTYPE_TCAM_PROF_TCAM,
+ * CFA_REMAP_TBL_TYPE_BYPASS,
+ * CFA_TX,
+ * &prof_tcam_rmp_byp_layout);
+ */
+ int (*cfa_bld_get_remap_table_layout)(enum cfa_resource_subtype_tcam st,
+ enum cfa_remap_tbl_type rmp_tt,
+ enum cfa_dir dir,
+ struct cfa_layout **layout);
+
+ /** build key layout
+ *
+ * This API takes the user provided key template as input and
+ * compiles it into a key layout supported by the hardware.
+ * It is intended that an application will only compile a
+ * key layout once for the provided key template and then
+ * reference the key layout throughout the lifetime of that
+ * key template.
+ *
+ * @param[in] key_template
+ * A pointer to the key template
+ *
+ * @param[in,out] layout
+ * A pointer of the key layout
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+ int (*cfa_bld_key_compile_layout)(struct cfa_key_template *t,
+ struct cfa_key_layout *l);
+
+ /** Print formatted key object
+ *
+ * This API prints in human readable form the data in a key
+ * object based upon the key layout provided. It also provides the
+ * option to provide a raw byte output.
+ *
+ * @param[in] stream
+ * Generally set to stdout (stderr possible)
+ *
+ * @param[in] key_obj
+ * A pointer to the key_obj to be displayed
+ *
+ * @param[in] key_layout
+ * A pointer to the key_layout indicating the key format
+ *
+ * @param[in] decode
+ * If set, decode the fields, if clear provide raw byte output.
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+ int (*cfa_bld_key_print_obj)(FILE *stream, struct cfa_key_obj *key_obj,
+ struct cfa_key_layout *key_layout,
+ bool decode);
+
+ /** Transform key data with device specific control information
+ *
+ * This API inserts or strips device specific control information
+ * to/from a key object.
+ *
+ * @param[in] op
+ * specify key transform operations.
+ *
+ * @param[in] key_obj
+ * A pointer of the key object to be transformed
+ *
+ * @param[out] key_obj_out
+ * A pointer of the transformed key data object
+ * The updated bitlen for the transformed key is returned
+ * in the data_len_bits field of this object.
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+ int (*cfa_bld_key_transform)(enum cfa_key_ctrlops op,
+ struct cfa_key_obj *key_obj,
+ struct cfa_key_obj *key_obj_out);
+
+ /** build action layout
+ *
+ * This API takes the user provided action template as input and
+ * compiles it into an action layout supported by the hardware.
+ * It is intended that an application will only compile an
+ * action layout once for the provided action template and then
+ * reference the action layout throughout the lifetime of that
+ * action template.
+ *
+ * @param[in] act_template
+ * A pointer to the action template
+ *
+ * @param[in,out] layout
+ * A pointer of the action layout
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+ int (*cfa_bld_act_compile_layout)(struct cfa_action_template *t,
+ struct cfa_action_layout *l);
+
+ /** initialize action private fields
+ *
+ * This API provides the functionality to zero out the action
+ * object data fields and set pre-initialized private fields
+ * based on the layout. Any action object must be initialized
+ * using this API before any put and get APIs can be executed
+ * for an action object.
+ *
+ * @param[in,out] act_obj
+ * A pointer of the action object to be initialized
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+ int (*cfa_bld_action_init_obj)(struct cfa_action_obj *act_obj);
+
+ /** compute inline action object pointers/offsets
+ *
+ * This API provides the functionality to compute and set
+ * pointers/offset to the inlined actions in an action record.
+ * This API is applicable only to the action object type that
+ * support inline actions.
+ *
+ * @param[in,out] act_obj
+ * A pointer of the action object to be initialized
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+ int (*cfa_bld_action_compute_ptr)(struct cfa_action_obj *obj);
+
+ /** Print action object
+ *
+ * This API presents the action object in human readable
+ * format.
+ *
+ *
+ * @param[in] stream
+ * Generally set to stdout (stderr possible)
+ *
+ * @param[in,out] act_obj
+ * A pointer of the action object to be displayed
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+ int (*cfa_bld_action_print_obj)(FILE *stream,
+ struct cfa_action_obj *obj,
+ bool decode);
+
+ /** Print field object
+ *
+ * This API prints out the raw field output
+ *
+ * @param[in] fld_obj
+ * A pointer fld_obj to be displayed
+ *
+ * @param[in] fld_layout
+ * A pointer to the cfa_layout indicating the field format
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+ int (*cfa_bld_fld_print_obj)(uint64_t *fld_obj,
+ struct cfa_layout *layout);
+};
+
+/**@}*/
+
+/**@}*/
+#endif /* _CFA_BLD_DEVOPS_H_ */
new file mode 100644
@@ -0,0 +1,1542 @@
+/****************************************************************************
+ * Copyright(c) 2021 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * @file cfa_bld_field_ids.h
+ *
+ * @brief Enumerations definitions for CFA HW table fields, Action record
+ * fields and Lookup Key (EM/WC-TCAM) fields.
+ *
+ * This file is independent of the CFA HW version and defines the
+ * superset of the enumeration values for table, action and EM/WC-TCAM
+ * bit fields. This file is meant for use by host applications that
+ * support multiple devices with different CFA Hw versions.
+ *
+ * These enum definitions should be updated whenever any of the
+ * definitions in the auto-generated header 'cfa_bld_pxx_field_ids.h'
+ * file gets any new enum values.
+ */
+
+#ifndef _CFA_BLD_FIELD_IDS_H_
+#define _CFA_BLD_FIELD_IDS_H_
+
+/**
+ * Lookup Field Range Check Range Memory Fields:
+ */
+enum cfa_bld_lkup_frc_profile_flds {
+ CFA_BLD_LKUP_FRC_PROFILE_FIELD_SEL_1_FLD = 0,
+ CFA_BLD_LKUP_FRC_PROFILE_RANGE_CHECK_1_FLD = 1,
+ CFA_BLD_LKUP_FRC_PROFILE_FIELD_SEL_0_FLD = 2,
+ CFA_BLD_LKUP_FRC_PROFILE_RANGE_CHECK_0_FLD = 3,
+ CFA_BLD_LKUP_FRC_PROFILE_MAX_FLD
+};
+
+/**
+ * Lookup Connection Tracking State Memory Fields:
+ */
+enum cfa_bld_lkup_ct_state_flds {
+ CFA_BLD_LKUP_CT_STATE_NOTIFY_FLD = 0,
+ CFA_BLD_LKUP_CT_STATE_NOTIFY_STATE_FLD = 1,
+ CFA_BLD_LKUP_CT_STATE_ACTION_FLD = 2,
+ CFA_BLD_LKUP_CT_STATE_TIMER_SELECT_FLD = 3,
+ CFA_BLD_LKUP_CT_STATE_TIMER_PRELOAD_FLD = 4,
+ CFA_BLD_LKUP_CT_STATE_MAX_FLD
+};
+
+/**
+ * Lookup Connection Tracking State Machine Rule Memory Fields:
+ */
+enum cfa_bld_lkup_ct_rule_flds {
+ CFA_BLD_LKUP_CT_RULE_VALID_FLD = 0,
+ CFA_BLD_LKUP_CT_RULE_MASK_FLD = 1,
+ CFA_BLD_LKUP_CT_RULE_PKT_NOT_BG_FLD = 2,
+ CFA_BLD_LKUP_CT_RULE_STATE_FLD = 3,
+ CFA_BLD_LKUP_CT_RULE_TCP_FLAGS_FLD = 4,
+ CFA_BLD_LKUP_CT_RULE_PROT_IS_TCP_FLD = 5,
+ CFA_BLD_LKUP_CT_RULE_MSB_UPDT_FLD = 6,
+ CFA_BLD_LKUP_CT_RULE_FLAGS_FAILED_FLD = 7,
+ CFA_BLD_LKUP_CT_RULE_WIN_FAILED_FLD = 8,
+ CFA_BLD_LKUP_CT_RULE_MAX_FLD
+};
+
+/**
+ * Lookup Connection Tracking State Machine Rule Record Memory Fields:
+ */
+enum cfa_bld_lkup_ct_rule_record_flds {
+ CFA_BLD_LKUP_CT_RULE_RECORD_ACTION_FLD = 0,
+ CFA_BLD_LKUP_CT_RULE_RECORD_NEXT_STATE_FLD = 1,
+ CFA_BLD_LKUP_CT_RULE_RECORD_SEND_FLD = 2,
+ CFA_BLD_LKUP_CT_RULE_RECORD_MAX_FLD
+};
+
+/**
+ * VEB Destination Bitmap Remap Table. Fields:
+ */
+enum cfa_bld_act_veb_rmp_flds {
+ CFA_BLD_ACT_VEB_RMP_MODE_FLD = 0,
+ CFA_BLD_ACT_VEB_RMP_ENABLE_FLD = 1,
+ CFA_BLD_ACT_VEB_RMP_BITMAP_FLD = 2,
+ CFA_BLD_ACT_VEB_RMP_MAX_FLD
+};
+
+/**
+ * Lookup Field Range Check Range Memory Fields:
+ */
+enum cfa_bld_lkup_frc_range_flds {
+ CFA_BLD_LKUP_FRC_RANGE_RANGE_LO_FLD = 0,
+ CFA_BLD_LKUP_FRC_RANGE_RANGE_HI_FLD = 1,
+ CFA_BLD_LKUP_FRC_RANGE_MAX_FLD
+};
+
+/**
+ * L2 Context TCAM. Fields:
+ */
+enum cfa_bld_prof_l2_ctxt_tcam_flds {
+ CFA_BLD_PROF_L2_CTXT_TCAM_VALID_FLD = 0,
+ CFA_BLD_PROF_L2_CTXT_TCAM_SPARE_FLD = 1,
+ CFA_BLD_PROF_L2_CTXT_TCAM_MPASS_CNT_FLD = 2,
+ CFA_BLD_PROF_L2_CTXT_TCAM_RCYC_FLD = 3,
+ CFA_BLD_PROF_L2_CTXT_TCAM_LOOPBACK_FLD = 4,
+ CFA_BLD_PROF_L2_CTXT_TCAM_SPIF_FLD = 5,
+ CFA_BLD_PROF_L2_CTXT_TCAM_PARIF_FLD = 6,
+ CFA_BLD_PROF_L2_CTXT_TCAM_SVIF_FLD = 7,
+ CFA_BLD_PROF_L2_CTXT_TCAM_METADATA_FLD = 8,
+ CFA_BLD_PROF_L2_CTXT_TCAM_L2_FUNC_FLD = 9,
+ CFA_BLD_PROF_L2_CTXT_TCAM_ROCE_FLD = 10,
+ CFA_BLD_PROF_L2_CTXT_TCAM_PURE_LLC_FLD = 11,
+ CFA_BLD_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_FLD = 12,
+ CFA_BLD_PROF_L2_CTXT_TCAM_T_HDR_TYPE_FLD = 13,
+ CFA_BLD_PROF_L2_CTXT_TCAM_ID_CTXT_FLD = 14,
+ CFA_BLD_PROF_L2_CTXT_TCAM_MAC0_FLD = 15,
+ CFA_BLD_PROF_L2_CTXT_TCAM_MAC1_FLD = 16,
+ CFA_BLD_PROF_L2_CTXT_TCAM_VTAG_PRESENT_FLD = 17,
+ CFA_BLD_PROF_L2_CTXT_TCAM_TWO_VTAGS_FLD = 18,
+ CFA_BLD_PROF_L2_CTXT_TCAM_OVLAN_VID_FLD = 19,
+ CFA_BLD_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_FLD = 20,
+ CFA_BLD_PROF_L2_CTXT_TCAM_IVLAN_VID_FLD = 21,
+ CFA_BLD_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_FLD = 22,
+ CFA_BLD_PROF_L2_CTXT_TCAM_ETYPE_FLD = 23,
+ CFA_BLD_PROF_L2_CTXT_TCAM_MAX_FLD
+};
+
+/**
+ * Profiler Profile Lookup TCAM Fields:
+ */
+enum cfa_bld_prof_profile_tcam_flds {
+ CFA_BLD_PROF_PROFILE_TCAM_VALID_FLD = 0,
+ CFA_BLD_PROF_PROFILE_TCAM_SPARE_FLD = 1,
+ CFA_BLD_PROF_PROFILE_TCAM_LOOPBACK_FLD = 2,
+ CFA_BLD_PROF_PROFILE_TCAM_PKT_TYPE_FLD = 3,
+ CFA_BLD_PROF_PROFILE_TCAM_RCYC_FLD = 4,
+ CFA_BLD_PROF_PROFILE_TCAM_METADATA_FLD = 5,
+ CFA_BLD_PROF_PROFILE_TCAM_AGG_ERROR_FLD = 6,
+ CFA_BLD_PROF_PROFILE_TCAM_L2_FUNC_FLD = 7,
+ CFA_BLD_PROF_PROFILE_TCAM_PROF_FUNC_FLD = 8,
+ CFA_BLD_PROF_PROFILE_TCAM_HREC_NEXT_FLD = 9,
+ CFA_BLD_PROF_PROFILE_TCAM_INT_HDR_TYPE_FLD = 10,
+ CFA_BLD_PROF_PROFILE_TCAM_INT_HDR_GROUP_FLD = 11,
+ CFA_BLD_PROF_PROFILE_TCAM_INT_IFA_TAIL_FLD = 12,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL2_HDR_VALID_FLD = 13,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_FLD = 14,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_FLD = 15,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_FLD = 16,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_FLD = 17,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_VALID_FLD = 18,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_FLD = 19,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_FLD = 20,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_FLD = 21,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_VALID_FLD = 22,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_FLD = 23,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_FLD = 24,
+ CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_FLD = 25,
+ CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_VALID_FLD = 26,
+ CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_ERROR_FLD = 27,
+ CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_TYPE_FLD = 28,
+ CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_FLAGS_FLD = 29,
+ CFA_BLD_PROF_PROFILE_TCAM_TL2_HDR_VALID_FLD = 30,
+ CFA_BLD_PROF_PROFILE_TCAM_TL2_HDR_TYPE_FLD = 31,
+ CFA_BLD_PROF_PROFILE_TCAM_TL2_UC_MC_BC_FLD = 32,
+ CFA_BLD_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_FLD = 33,
+ CFA_BLD_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_FLD = 34,
+ CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_VALID_FLD = 35,
+ CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_ERROR_FLD = 36,
+ CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_TYPE_FLD = 37,
+ CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_ISIP_FLD = 38,
+ CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_VALID_FLD = 39,
+ CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_ERROR_FLD = 40,
+ CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_TYPE_FLD = 41,
+ CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_FLD = 42,
+ CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_VALID_FLD = 43,
+ CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_ERROR_FLD = 44,
+ CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_TYPE_FLD = 45,
+ CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_FLD = 46,
+ CFA_BLD_PROF_PROFILE_TCAM_L2_HDR_VALID_FLD = 47,
+ CFA_BLD_PROF_PROFILE_TCAM_L2_HDR_ERROR_FLD = 48,
+ CFA_BLD_PROF_PROFILE_TCAM_L2_HDR_TYPE_FLD = 49,
+ CFA_BLD_PROF_PROFILE_TCAM_L2_UC_MC_BC_FLD = 50,
+ CFA_BLD_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_FLD = 51,
+ CFA_BLD_PROF_PROFILE_TCAM_L2_TWO_VTAGS_FLD = 52,
+ CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_VALID_FLD = 53,
+ CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_ERROR_FLD = 54,
+ CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_TYPE_FLD = 55,
+ CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_ISIP_FLD = 56,
+ CFA_BLD_PROF_PROFILE_TCAM_L3_PROT_FLD = 57,
+ CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_VALID_FLD = 58,
+ CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_ERROR_FLD = 59,
+ CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_TYPE_FLD = 60,
+ CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_FLD = 61,
+ CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_FLD = 62,
+ CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_FLAGS_FLD = 63,
+ CFA_BLD_PROF_PROFILE_TCAM_L4_DCN_PRESENT_FLD = 64,
+ CFA_BLD_PROF_PROFILE_TCAM_MAX_FLD
+};
+
+/**
+ * Action VEB TCAM. TX Fields (VEB Remap Mode):
+ */
+enum cfa_bld_act_veb_tcam_tx_flds {
+ CFA_BLD_ACT_VEB_TCAM_TX_VALID_FLD = 0,
+ CFA_BLD_ACT_VEB_TCAM_TX_PARIF_IN_FLD = 1,
+ CFA_BLD_ACT_VEB_TCAM_TX_NUM_VTAGS_FLD = 2,
+ CFA_BLD_ACT_VEB_TCAM_TX_DMAC_FLD = 3,
+ CFA_BLD_ACT_VEB_TCAM_TX_OVID_FLD = 4,
+ CFA_BLD_ACT_VEB_TCAM_TX_IVID_FLD = 5,
+ CFA_BLD_ACT_VEB_TCAM_TX_MAX_FLD
+};
+
+/**
+ * RX Fields (Source Knockout Mode):
+ */
+enum cfa_bld_act_veb_tcam_rx_flds {
+ CFA_BLD_ACT_VEB_TCAM_RX_VALID_FLD = 0,
+ CFA_BLD_ACT_VEB_TCAM_RX_SPARE_FLD = 1,
+ CFA_BLD_ACT_VEB_TCAM_RX_PADDING_FLD = 2,
+ CFA_BLD_ACT_VEB_TCAM_RX_UNICAST_FLD = 3,
+ CFA_BLD_ACT_VEB_TCAM_RX_MULTICAST_FLD = 4,
+ CFA_BLD_ACT_VEB_TCAM_RX_BROADCAST_FLD = 5,
+ CFA_BLD_ACT_VEB_TCAM_RX_PFID_FLD = 6,
+ CFA_BLD_ACT_VEB_TCAM_RX_VFID_FLD = 7,
+ CFA_BLD_ACT_VEB_TCAM_RX_SMAC_FLD = 8,
+ CFA_BLD_ACT_VEB_TCAM_RX_MAX_FLD
+};
+
+/**
+ * Action Feature Chaining TCAM.
+ */
+enum cfa_bld_act_fc_tcam_flds {
+ CFA_BLD_ACT_FC_TCAM_FC_VALID_FLD = 0,
+ CFA_BLD_ACT_FC_TCAM_FC_RSVD_FLD = 1,
+ CFA_BLD_ACT_FC_TCAM_FC_METADATA_FLD = 2,
+ CFA_BLD_ACT_FC_TCAM_MAX_FLD
+};
+
+/**
+ * Feature Chaining TCAM Remap Table Fields:
+ */
+enum cfa_bld_act_fc_rmp_dr_flds {
+ CFA_BLD_ACT_FC_RMP_DR_METADATA_FLD = 0,
+ CFA_BLD_ACT_FC_RMP_DR_METAMASK_FLD = 1,
+ CFA_BLD_ACT_FC_RMP_DR_L2_FUNC_FLD = 2,
+ CFA_BLD_ACT_FC_RMP_DR_RSVD_FLD = 3,
+ CFA_BLD_ACT_FC_RMP_DR_MAX_FLD
+};
+
+/**
+ * Profile Input Lookup Table Memory Fields:
+ */
+enum cfa_bld_prof_ilt_dr_flds {
+ CFA_BLD_PROF_ILT_DR_ILT_META_EN_FLD = 0,
+ CFA_BLD_PROF_ILT_DR_META_PROF_FLD = 1,
+ CFA_BLD_PROF_ILT_DR_METADATA_FLD = 2,
+ CFA_BLD_PROF_ILT_DR_PARIF_FLD = 3,
+ CFA_BLD_PROF_ILT_DR_L2_FUNC_FLD = 4,
+ CFA_BLD_PROF_ILT_DR_EN_BD_META_FLD = 5,
+ CFA_BLD_PROF_ILT_DR_EN_BD_ACTION_FLD = 6,
+ CFA_BLD_PROF_ILT_DR_EN_ILT_DEST_FLD = 7,
+ CFA_BLD_PROF_ILT_DR_ILT_FWD_OP_FLD = 8,
+ CFA_BLD_PROF_ILT_DR_ILT_ACT_HINT_FLD = 9,
+ CFA_BLD_PROF_ILT_DR_ILT_SCOPE_FLD = 10,
+ CFA_BLD_PROF_ILT_DR_ILT_ACT_REC_PTR_FLD = 11,
+ CFA_BLD_PROF_ILT_DR_ILT_DESTINATION_FLD = 12,
+ CFA_BLD_PROF_ILT_DR_MAX_FLD
+};
+
+/**
+ * Profile Lookup TCAM Remap Table Fields:
+ */
+enum cfa_bld_prof_profile_rmp_dr_flds {
+ CFA_BLD_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_FLD = 0,
+ CFA_BLD_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_FLD = 1,
+ CFA_BLD_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_FLD = 2,
+ CFA_BLD_PROF_PROFILE_RMP_DR_EM_KEY_ID_FLD = 3,
+ CFA_BLD_PROF_PROFILE_RMP_DR_EM_SCOPE_FLD = 4,
+ CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_FLD = 5,
+ CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_FLD = 6,
+ CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_FLD = 7,
+ CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_SCOPE_FLD = 8,
+ CFA_BLD_PROF_PROFILE_RMP_DR_MAX_FLD
+};
+
+/**
+ * PROF_PROFILE_RMP_DR_BYP
+ */
+enum cfa_bld_prof_profile_rmp_dr_byp_flds {
+ CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_FLD = 0,
+ CFA_BLD_PROF_PROFILE_RMP_DR_BYP_RESERVED_FLD = 1,
+ CFA_BLD_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_FLD = 2,
+ CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_FLD = 3,
+ CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_FLD = 4,
+ CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_FLD = 5,
+ CFA_BLD_PROF_PROFILE_RMP_DR_BYP_MAX_FLD
+};
+
+/**
+ * VNIC-SVIF Properties Table Fields: TX SVIF Properties Table
+ */
+enum cfa_bld_act_vspt_dr_tx_flds {
+ CFA_BLD_ACT_VSPT_DR_TX_TPID_AS_CTL_FLD = 0,
+ CFA_BLD_ACT_VSPT_DR_TX_ALWD_TPID_FLD = 1,
+ CFA_BLD_ACT_VSPT_DR_TX_DFLT_TPID_FLD = 2,
+ CFA_BLD_ACT_VSPT_DR_TX_PRI_AS_CTL_FLD = 3,
+ CFA_BLD_ACT_VSPT_DR_TX_ALWD_PRI_FLD = 4,
+ CFA_BLD_ACT_VSPT_DR_TX_DFLT_PRI_FLD = 5,
+ CFA_BLD_ACT_VSPT_DR_TX_MIR_FLD = 6,
+ CFA_BLD_ACT_VSPT_DR_TX_MAX_FLD
+};
+
+/**
+ * RX VNIC Properties Table
+ */
+enum cfa_bld_act_vspt_dr_rx_flds {
+ CFA_BLD_ACT_VSPT_DR_RX_RSVD_FLD = 0,
+ CFA_BLD_ACT_VSPT_DR_RX_METAFMT_FLD = 1,
+ CFA_BLD_ACT_VSPT_DR_RX_FID_FLD = 2,
+ CFA_BLD_ACT_VSPT_DR_RX_MIR_FLD = 3,
+ CFA_BLD_ACT_VSPT_DR_RX_MAX_FLD
+};
+
+/**
+ * LAG ID Balance Table Fields:
+ */
+enum cfa_bld_act_lbt_dr_flds {
+ CFA_BLD_ACT_LBT_DR_DST_BMP_FLD = 0,
+ CFA_BLD_ACT_LBT_DR_MAX_FLD
+};
+
+/**
+ * L2 Context Lookup Remap Table Fields:
+ */
+enum cfa_bld_prof_l2_ctxt_rmp_dr_flds {
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_FLD = 0,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_PARIF_FLD = 1,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_FLD = 2,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_FLD = 3,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_FLD = 4,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_PROF_FUNC_FLD = 5,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_FLD = 6,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_FLD = 7,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_META_FLD = 8,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_FLD = 9,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_FLD = 10,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_FLD = 11,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_FLD = 12,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_FLD = 13,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_FLD = 14,
+ CFA_BLD_PROF_L2_CTXT_RMP_DR_MAX_FLD
+};
+
+/**
+ * Multi Field Register.
+ */
+enum cfa_bld_act_fc_tcam_result_flds {
+ CFA_BLD_ACT_FC_TCAM_RESULT_SEARCH_RESULT_FLD = 0,
+ CFA_BLD_ACT_FC_TCAM_RESULT_UNUSED_0_FLD = 1,
+ CFA_BLD_ACT_FC_TCAM_RESULT_SEARCH_HIT_FLD = 2,
+ CFA_BLD_ACT_FC_TCAM_RESULT_MAX_FLD
+};
+
+/**
+ * Multi Field Register.
+ */
+enum cfa_bld_act_mirror_flds {
+ CFA_BLD_ACT_MIRROR_UNUSED_0_FLD = 0,
+ CFA_BLD_ACT_MIRROR_RELATIVE_FLD = 1,
+ CFA_BLD_ACT_MIRROR_HINT_FLD = 2,
+ CFA_BLD_ACT_MIRROR_SAMP_FLD = 3,
+ CFA_BLD_ACT_MIRROR_TRUNC_FLD = 4,
+ CFA_BLD_ACT_MIRROR_IGN_DROP_FLD = 5,
+ CFA_BLD_ACT_MIRROR_MODE_FLD = 6,
+ CFA_BLD_ACT_MIRROR_COND_FLD = 7,
+ CFA_BLD_ACT_MIRROR_AR_PTR_FLD = 8,
+ CFA_BLD_ACT_MIRROR_SAMP_CFG_FLD = 9,
+ CFA_BLD_ACT_MIRROR_MAX_FLD
+};
+
+/**
+ * WC LREC Lookup Record
+ */
+enum cfa_bld_wc_lrec_flds {
+ CFA_BLD_WC_LREC_METADATA_FLD = 0,
+ CFA_BLD_WC_LREC_META_PROF_FLD = 1,
+ CFA_BLD_WC_LREC_PROF_FUNC_FLD = 2,
+ CFA_BLD_WC_LREC_RECYCLE_DEST_FLD = 3,
+ CFA_BLD_WC_LREC_FC_PTR_FLD = 4,
+ CFA_BLD_WC_LREC_FC_TYPE_FLD = 5,
+ CFA_BLD_WC_LREC_FC_OP_FLD = 6,
+ CFA_BLD_WC_LREC_PATHS_M1_FLD = 7,
+ CFA_BLD_WC_LREC_ACT_REC_SIZE_FLD = 8,
+ CFA_BLD_WC_LREC_RING_TABLE_IDX_FLD = 9,
+ CFA_BLD_WC_LREC_DESTINATION_FLD = 10,
+ CFA_BLD_WC_LREC_ACT_REC_PTR_FLD = 11,
+ CFA_BLD_WC_LREC_ACT_HINT_FLD = 12,
+ CFA_BLD_WC_LREC_STRENGTH_FLD = 13,
+ CFA_BLD_WC_LREC_OPCODE_FLD = 14,
+ CFA_BLD_WC_LREC_EPOCH1_FLD = 15,
+ CFA_BLD_WC_LREC_EPOCH0_FLD = 16,
+ CFA_BLD_WC_LREC_REC_SIZE_FLD = 17,
+ CFA_BLD_WC_LREC_VALID_FLD = 18,
+ CFA_BLD_WC_LREC_MAX_FLD
+};
+
+/**
+ * EM LREC Lookup Record
+ */
+enum cfa_bld_em_lrec_flds {
+ CFA_BLD_EM_LREC_RANGE_IDX_FLD = 0,
+ CFA_BLD_EM_LREC_RANGE_PROFILE_FLD = 1,
+ CFA_BLD_EM_LREC_CREC_TIMER_VALUE_FLD = 2,
+ CFA_BLD_EM_LREC_CREC_STATE_FLD = 3,
+ CFA_BLD_EM_LREC_CREC_TCP_MSB_OPP_INIT_FLD = 4,
+ CFA_BLD_EM_LREC_CREC_TCP_MSB_OPP_FLD = 5,
+ CFA_BLD_EM_LREC_CREC_TCP_MSB_LOC_FLD = 6,
+ CFA_BLD_EM_LREC_CREC_TCP_WIN_FLD = 7,
+ CFA_BLD_EM_LREC_CREC_TCP_UPDT_EN_FLD = 8,
+ CFA_BLD_EM_LREC_CREC_TCP_DIR_FLD = 9,
+ CFA_BLD_EM_LREC_METADATA_FLD = 10,
+ CFA_BLD_EM_LREC_PROF_FUNC_FLD = 11,
+ CFA_BLD_EM_LREC_META_PROF_FLD = 12,
+ CFA_BLD_EM_LREC_RECYCLE_DEST_FLD = 13,
+ CFA_BLD_EM_LREC_FC_PTR_FLD = 14,
+ CFA_BLD_EM_LREC_FC_TYPE_FLD = 15,
+ CFA_BLD_EM_LREC_FC_OP_FLD = 16,
+ CFA_BLD_EM_LREC_PATHS_M1_FLD = 17,
+ CFA_BLD_EM_LREC_ACT_REC_SIZE_FLD = 18,
+ CFA_BLD_EM_LREC_RING_TABLE_IDX_FLD = 19,
+ CFA_BLD_EM_LREC_DESTINATION_FLD = 20,
+ CFA_BLD_EM_LREC_ACT_REC_PTR_FLD = 21,
+ CFA_BLD_EM_LREC_ACT_HINT_FLD = 22,
+ CFA_BLD_EM_LREC_STRENGTH_FLD = 23,
+ CFA_BLD_EM_LREC_OPCODE_FLD = 24,
+ CFA_BLD_EM_LREC_EPOCH1_FLD = 25,
+ CFA_BLD_EM_LREC_EPOCH0_FLD = 26,
+ CFA_BLD_EM_LREC_REC_SIZE_FLD = 27,
+ CFA_BLD_EM_LREC_VALID_FLD = 28,
+ CFA_BLD_EM_LREC_MAX_FLD
+};
+
+/**
+ * EM Lookup Bucket Format
+ */
+enum cfa_bld_em_bucket_flds {
+ CFA_BLD_EM_BUCKET_BIN0_ENTRY_FLD = 0,
+ CFA_BLD_EM_BUCKET_BIN0_HASH_MSBS_FLD = 1,
+ CFA_BLD_EM_BUCKET_BIN1_ENTRY_FLD = 2,
+ CFA_BLD_EM_BUCKET_BIN1_HASH_MSBS_FLD = 3,
+ CFA_BLD_EM_BUCKET_BIN2_ENTRY_FLD = 4,
+ CFA_BLD_EM_BUCKET_BIN2_HASH_MSBS_FLD = 5,
+ CFA_BLD_EM_BUCKET_BIN3_ENTRY_FLD = 6,
+ CFA_BLD_EM_BUCKET_BIN3_HASH_MSBS_FLD = 7,
+ CFA_BLD_EM_BUCKET_BIN4_ENTRY_FLD = 8,
+ CFA_BLD_EM_BUCKET_BIN4_HASH_MSBS_FLD = 9,
+ CFA_BLD_EM_BUCKET_BIN5_ENTRY_FLD = 10,
+ CFA_BLD_EM_BUCKET_BIN5_HASH_MSBS_FLD = 11,
+ CFA_BLD_EM_BUCKET_CHAIN_POINTER_FLD = 12,
+ CFA_BLD_EM_BUCKET_CHAIN_VALID_FLD = 13,
+ CFA_BLD_EM_BUCKET_MAX_FLD
+};
+
+/**
+ * Compact Action Record. The compact action record uses relative
+ * pointers to access needed data. This keeps the compact action record
+ * down to 64b.
+ */
+enum cfa_bld_compact_action_flds {
+ CFA_BLD_COMPACT_ACTION_TYPE_FLD = 0,
+ CFA_BLD_COMPACT_ACTION_DROP_FLD = 1,
+ CFA_BLD_COMPACT_ACTION_VLAN_DELETE_FLD = 2,
+ CFA_BLD_COMPACT_ACTION_DEST_FLD = 3,
+ CFA_BLD_COMPACT_ACTION_DEST_OP_FLD = 4,
+ CFA_BLD_COMPACT_ACTION_DECAP_FLD = 5,
+ CFA_BLD_COMPACT_ACTION_MIRRORING_FLD = 6,
+ CFA_BLD_COMPACT_ACTION_METER_PTR_FLD = 7,
+ CFA_BLD_COMPACT_ACTION_STAT0_OFF_FLD = 8,
+ CFA_BLD_COMPACT_ACTION_STAT0_OP_FLD = 9,
+ CFA_BLD_COMPACT_ACTION_STAT0_CTR_TYPE_FLD = 10,
+ CFA_BLD_COMPACT_ACTION_MOD_OFF_FLD = 11,
+ CFA_BLD_COMPACT_ACTION_ENC_OFF_FLD = 12,
+ CFA_BLD_COMPACT_ACTION_SRC_OFF_FLD = 13,
+ CFA_BLD_COMPACT_ACTION_UNUSED_0_FLD = 14,
+ CFA_BLD_COMPACT_ACTION_MAX_FLD
+};
+
+/**
+ * Full Action Record. The full action record uses full pointers to
+ * access needed data. It also allows access to all the action features.
+ * The Full Action record is 192b.
+ */
+enum cfa_bld_full_action_flds {
+ CFA_BLD_FULL_ACTION_TYPE_FLD = 0,
+ CFA_BLD_FULL_ACTION_DROP_FLD = 1,
+ CFA_BLD_FULL_ACTION_VLAN_DELETE_FLD = 2,
+ CFA_BLD_FULL_ACTION_DEST_FLD = 3,
+ CFA_BLD_FULL_ACTION_DEST_OP_FLD = 4,
+ CFA_BLD_FULL_ACTION_DECAP_FLD = 5,
+ CFA_BLD_FULL_ACTION_MIRRORING_FLD = 6,
+ CFA_BLD_FULL_ACTION_METER_PTR_FLD = 7,
+ CFA_BLD_FULL_ACTION_STAT0_PTR_FLD = 8,
+ CFA_BLD_FULL_ACTION_STAT0_OP_FLD = 9,
+ CFA_BLD_FULL_ACTION_STAT0_CTR_TYPE_FLD = 10,
+ CFA_BLD_FULL_ACTION_STAT1_PTR_FLD = 11,
+ CFA_BLD_FULL_ACTION_STAT1_OP_FLD = 12,
+ CFA_BLD_FULL_ACTION_STAT1_CTR_TYPE_FLD = 13,
+ CFA_BLD_FULL_ACTION_MOD_PTR_FLD = 14,
+ CFA_BLD_FULL_ACTION_ENC_PTR_FLD = 15,
+ CFA_BLD_FULL_ACTION_SRC_PTR_FLD = 16,
+ CFA_BLD_FULL_ACTION_UNUSED_0_FLD = 17,
+ CFA_BLD_FULL_ACTION_MAX_FLD
+};
+
+/**
+ * Multicast Group Action Record. This action is used to send the packet
+ * to multiple destinations. The MGC Action record is 256b.
+ */
+enum cfa_bld_mcg_action_flds {
+ CFA_BLD_MCG_ACTION_TYPE_FLD = 0,
+ CFA_BLD_MCG_ACTION_SRC_KO_EN_FLD = 1,
+ CFA_BLD_MCG_ACTION_UNUSED_0_FLD = 2,
+ CFA_BLD_MCG_ACTION_NEXT_PTR_FLD = 3,
+ CFA_BLD_MCG_ACTION_PTR0_ACT_HINT_FLD = 4,
+ CFA_BLD_MCG_ACTION_PTR0_ACT_REC_PTR_FLD = 5,
+ CFA_BLD_MCG_ACTION_PTR1_ACT_HINT_FLD = 6,
+ CFA_BLD_MCG_ACTION_PTR1_ACT_REC_PTR_FLD = 7,
+ CFA_BLD_MCG_ACTION_PTR2_ACT_HINT_FLD = 8,
+ CFA_BLD_MCG_ACTION_PTR2_ACT_REC_PTR_FLD = 9,
+ CFA_BLD_MCG_ACTION_PTR3_ACT_HINT_FLD = 10,
+ CFA_BLD_MCG_ACTION_PTR3_ACT_REC_PTR_FLD = 11,
+ CFA_BLD_MCG_ACTION_PTR4_ACT_HINT_FLD = 12,
+ CFA_BLD_MCG_ACTION_PTR4_ACT_REC_PTR_FLD = 13,
+ CFA_BLD_MCG_ACTION_PTR5_ACT_HINT_FLD = 14,
+ CFA_BLD_MCG_ACTION_PTR5_ACT_REC_PTR_FLD = 15,
+ CFA_BLD_MCG_ACTION_PTR6_ACT_HINT_FLD = 16,
+ CFA_BLD_MCG_ACTION_PTR6_ACT_REC_PTR_FLD = 17,
+ CFA_BLD_MCG_ACTION_PTR7_ACT_HINT_FLD = 18,
+ CFA_BLD_MCG_ACTION_PTR7_ACT_REC_PTR_FLD = 19,
+ CFA_BLD_MCG_ACTION_MAX_FLD
+};
+
+/**
+ * Multicast Group Action Record. This action is used to send the packet
+ * to multiple destinations. The MGC Action record is 256b.
+ */
+enum cfa_bld_mcg_subseq_action_flds {
+ CFA_BLD_MCG_SUBSEQ_ACTION_TYPE_FLD = 0,
+ CFA_BLD_MCG_SUBSEQ_ACTION_UNUSED_0_FLD = 1,
+ CFA_BLD_MCG_SUBSEQ_ACTION_NEXT_PTR_FLD = 2,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_FLD = 3,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_FLD = 4,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_FLD = 5,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_FLD = 6,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_FLD = 7,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_FLD = 8,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_FLD = 9,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_FLD = 10,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_FLD = 11,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_FLD = 12,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_FLD = 13,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_FLD = 14,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_FLD = 15,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_FLD = 16,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_FLD = 17,
+ CFA_BLD_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_FLD = 18,
+ CFA_BLD_MCG_SUBSEQ_ACTION_MAX_FLD
+};
+
+/**
+ * Action Meter Formats
+ */
+enum cfa_bld_meters_flds {
+ CFA_BLD_METERS_BKT_C_FLD = 0,
+ CFA_BLD_METERS_BKT_E_FLD = 1,
+ CFA_BLD_METERS_FLAGS_MTR_VAL_FLD = 2,
+ CFA_BLD_METERS_FLAGS_ECN_RMP_EN_FLD = 3,
+ CFA_BLD_METERS_FLAGS_CF_FLD = 4,
+ CFA_BLD_METERS_FLAGS_PM_FLD = 5,
+ CFA_BLD_METERS_FLAGS_RFC2698_FLD = 6,
+ CFA_BLD_METERS_FLAGS_CBSM_FLD = 7,
+ CFA_BLD_METERS_FLAGS_EBSM_FLD = 8,
+ CFA_BLD_METERS_FLAGS_CBND_FLD = 9,
+ CFA_BLD_METERS_FLAGS_EBND_FLD = 10,
+ CFA_BLD_METERS_CBS_FLD = 11,
+ CFA_BLD_METERS_EBS_FLD = 12,
+ CFA_BLD_METERS_CIR_FLD = 13,
+ CFA_BLD_METERS_EIR_FLD = 14,
+ CFA_BLD_METERS_PROTECTION_SCOPE_FLD = 15,
+ CFA_BLD_METERS_PROTECTION_RSVD_FLD = 16,
+ CFA_BLD_METERS_PROTECTION_ENABLE_FLD = 17,
+ CFA_BLD_METERS_MAX_FLD
+};
+
+/**
+ * Enumeration for fkb
+ */
+enum cfa_bld_fkb_flds {
+ CFA_BLD_FKB_PROF_ID_FLD = 0,
+ CFA_BLD_FKB_L2CTXT_FLD = 1,
+ CFA_BLD_FKB_L2FUNC_FLD = 2,
+ CFA_BLD_FKB_PARIF_FLD = 3,
+ CFA_BLD_FKB_SPIF_FLD = 4,
+ CFA_BLD_FKB_SVIF_FLD = 5,
+ CFA_BLD_FKB_LCOS_FLD = 6,
+ CFA_BLD_FKB_META_HI_FLD = 7,
+ CFA_BLD_FKB_META_LO_FLD = 8,
+ CFA_BLD_FKB_RCYC_CNT_FLD = 9,
+ CFA_BLD_FKB_LOOPBACK_FLD = 10,
+ CFA_BLD_FKB_OTL2_TYPE_FLD = 11,
+ CFA_BLD_FKB_OTL2_DMAC_FLD = 12,
+ CFA_BLD_FKB_OTL2_SMAC_FLD = 13,
+ CFA_BLD_FKB_OTL2_DT_FLD = 14,
+ CFA_BLD_FKB_OTL2_SA_FLD = 15,
+ CFA_BLD_FKB_OTL2_NVT_FLD = 16,
+ CFA_BLD_FKB_OTL2_OVP_FLD = 17,
+ CFA_BLD_FKB_OTL2_OVD_FLD = 18,
+ CFA_BLD_FKB_OTL2_OVV_FLD = 19,
+ CFA_BLD_FKB_OTL2_OVT_FLD = 20,
+ CFA_BLD_FKB_OTL2_IVP_FLD = 21,
+ CFA_BLD_FKB_OTL2_IVD_FLD = 22,
+ CFA_BLD_FKB_OTL2_IVV_FLD = 23,
+ CFA_BLD_FKB_OTL2_IVT_FLD = 24,
+ CFA_BLD_FKB_OTL2_ETYPE_FLD = 25,
+ CFA_BLD_FKB_OTL3_TYPE_FLD = 26,
+ CFA_BLD_FKB_OTL3_SIP3_FLD = 27,
+ CFA_BLD_FKB_OTL3_SIP2_FLD = 28,
+ CFA_BLD_FKB_OTL3_SIP1_FLD = 29,
+ CFA_BLD_FKB_OTL3_SIP0_FLD = 30,
+ CFA_BLD_FKB_OTL3_DIP3_FLD = 31,
+ CFA_BLD_FKB_OTL3_DIP2_FLD = 32,
+ CFA_BLD_FKB_OTL3_DIP1_FLD = 33,
+ CFA_BLD_FKB_OTL3_DIP0_FLD = 34,
+ CFA_BLD_FKB_OTL3_TTL_FLD = 35,
+ CFA_BLD_FKB_OTL3_PROT_FLD = 36,
+ CFA_BLD_FKB_OTL3_FID_FLD = 37,
+ CFA_BLD_FKB_OTL3_QOS_FLD = 38,
+ CFA_BLD_FKB_OTL3_IEH_NONEXT_FLD = 39,
+ CFA_BLD_FKB_OTL3_IEH_SEP_FLD = 40,
+ CFA_BLD_FKB_OTL3_IEH_AUTH_FLD = 41,
+ CFA_BLD_FKB_OTL3_IEH_DEST_FLD = 42,
+ CFA_BLD_FKB_OTL3_IEH_FRAG_FLD = 43,
+ CFA_BLD_FKB_OTL3_IEH_RTHDR_FLD = 44,
+ CFA_BLD_FKB_OTL3_IEH_HOP_FLD = 45,
+ CFA_BLD_FKB_OTL3_IEH_1FRAG_FLD = 46,
+ CFA_BLD_FKB_OTL3_DF_FLD = 47,
+ CFA_BLD_FKB_OTL3_L3ERR_FLD = 48,
+ CFA_BLD_FKB_OTL4_TYPE_FLD = 49,
+ CFA_BLD_FKB_OTL4_SRC_FLD = 50,
+ CFA_BLD_FKB_OTL4_DST_FLD = 51,
+ CFA_BLD_FKB_OTL4_FLAGS_FLD = 52,
+ CFA_BLD_FKB_OTL4_SEQ_FLD = 53,
+ CFA_BLD_FKB_OTL4_PA_FLD = 54,
+ CFA_BLD_FKB_OTL4_OPT_FLD = 55,
+ CFA_BLD_FKB_OTL4_TCPTS_FLD = 56,
+ CFA_BLD_FKB_OTL4_ERR_FLD = 57,
+ CFA_BLD_FKB_OT_TYPE_FLD = 58,
+ CFA_BLD_FKB_OT_FLAGS_FLD = 59,
+ CFA_BLD_FKB_OT_IDS_FLD = 60,
+ CFA_BLD_FKB_OT_ID_FLD = 61,
+ CFA_BLD_FKB_OT_CTXTS_FLD = 62,
+ CFA_BLD_FKB_OT_CTXT_FLD = 63,
+ CFA_BLD_FKB_OT_QOS_FLD = 64,
+ CFA_BLD_FKB_OT_ERR_FLD = 65,
+ CFA_BLD_FKB_TL2_TYPE_FLD = 66,
+ CFA_BLD_FKB_TL2_DMAC_FLD = 67,
+ CFA_BLD_FKB_TL2_SMAC_FLD = 68,
+ CFA_BLD_FKB_TL2_DT_FLD = 69,
+ CFA_BLD_FKB_TL2_SA_FLD = 70,
+ CFA_BLD_FKB_TL2_NVT_FLD = 71,
+ CFA_BLD_FKB_TL2_OVP_FLD = 72,
+ CFA_BLD_FKB_TL2_OVD_FLD = 73,
+ CFA_BLD_FKB_TL2_OVV_FLD = 74,
+ CFA_BLD_FKB_TL2_OVT_FLD = 75,
+ CFA_BLD_FKB_TL2_IVP_FLD = 76,
+ CFA_BLD_FKB_TL2_IVD_FLD = 77,
+ CFA_BLD_FKB_TL2_IVV_FLD = 78,
+ CFA_BLD_FKB_TL2_IVT_FLD = 79,
+ CFA_BLD_FKB_TL2_ETYPE_FLD = 80,
+ CFA_BLD_FKB_TL3_TYPE_FLD = 81,
+ CFA_BLD_FKB_TL3_SIP3_FLD = 82,
+ CFA_BLD_FKB_TL3_SIP2_FLD = 83,
+ CFA_BLD_FKB_TL3_SIP1_FLD = 84,
+ CFA_BLD_FKB_TL3_SIP0_FLD = 85,
+ CFA_BLD_FKB_TL3_DIP3_FLD = 86,
+ CFA_BLD_FKB_TL3_DIP2_FLD = 87,
+ CFA_BLD_FKB_TL3_DIP1_FLD = 88,
+ CFA_BLD_FKB_TL3_DIP0_FLD = 89,
+ CFA_BLD_FKB_TL3_TTL_FLD = 90,
+ CFA_BLD_FKB_TL3_PROT_FLD = 91,
+ CFA_BLD_FKB_TL3_FID_FLD = 92,
+ CFA_BLD_FKB_TL3_QOS_FLD = 93,
+ CFA_BLD_FKB_TL3_IEH_NONEXT_FLD = 94,
+ CFA_BLD_FKB_TL3_IEH_SEP_FLD = 95,
+ CFA_BLD_FKB_TL3_IEH_AUTH_FLD = 96,
+ CFA_BLD_FKB_TL3_IEH_DEST_FLD = 97,
+ CFA_BLD_FKB_TL3_IEH_FRAG_FLD = 98,
+ CFA_BLD_FKB_TL3_IEH_RTHDR_FLD = 99,
+ CFA_BLD_FKB_TL3_IEH_HOP_FLD = 100,
+ CFA_BLD_FKB_TL3_IEH_1FRAG_FLD = 101,
+ CFA_BLD_FKB_TL3_DF_FLD = 102,
+ CFA_BLD_FKB_TL3_L3ERR_FLD = 103,
+ CFA_BLD_FKB_TL4_TYPE_FLD = 104,
+ CFA_BLD_FKB_TL4_SRC_FLD = 105,
+ CFA_BLD_FKB_TL4_DST_FLD = 106,
+ CFA_BLD_FKB_TL4_FLAGS_FLD = 107,
+ CFA_BLD_FKB_TL4_SEQ_FLD = 108,
+ CFA_BLD_FKB_TL4_PA_FLD = 109,
+ CFA_BLD_FKB_TL4_OPT_FLD = 110,
+ CFA_BLD_FKB_TL4_TCPTS_FLD = 111,
+ CFA_BLD_FKB_TL4_ERR_FLD = 112,
+ CFA_BLD_FKB_T_TYPE_FLD = 113,
+ CFA_BLD_FKB_T_FLAGS_FLD = 114,
+ CFA_BLD_FKB_T_IDS_FLD = 115,
+ CFA_BLD_FKB_T_ID_FLD = 116,
+ CFA_BLD_FKB_T_CTXTS_FLD = 117,
+ CFA_BLD_FKB_T_CTXT_FLD = 118,
+ CFA_BLD_FKB_T_QOS_FLD = 119,
+ CFA_BLD_FKB_T_ERR_FLD = 120,
+ CFA_BLD_FKB_L2_TYPE_FLD = 121,
+ CFA_BLD_FKB_L2_DMAC_FLD = 122,
+ CFA_BLD_FKB_L2_SMAC_FLD = 123,
+ CFA_BLD_FKB_L2_DT_FLD = 124,
+ CFA_BLD_FKB_L2_SA_FLD = 125,
+ CFA_BLD_FKB_L2_NVT_FLD = 126,
+ CFA_BLD_FKB_L2_OVP_FLD = 127,
+ CFA_BLD_FKB_L2_OVD_FLD = 128,
+ CFA_BLD_FKB_L2_OVV_FLD = 129,
+ CFA_BLD_FKB_L2_OVT_FLD = 130,
+ CFA_BLD_FKB_L2_IVP_FLD = 131,
+ CFA_BLD_FKB_L2_IVD_FLD = 132,
+ CFA_BLD_FKB_L2_IVV_FLD = 133,
+ CFA_BLD_FKB_L2_IVT_FLD = 134,
+ CFA_BLD_FKB_L2_ETYPE_FLD = 135,
+ CFA_BLD_FKB_L3_TYPE_FLD = 136,
+ CFA_BLD_FKB_L3_SIP3_FLD = 137,
+ CFA_BLD_FKB_L3_SIP2_FLD = 138,
+ CFA_BLD_FKB_L3_SIP1_FLD = 139,
+ CFA_BLD_FKB_L3_SIP0_FLD = 140,
+ CFA_BLD_FKB_L3_DIP3_FLD = 141,
+ CFA_BLD_FKB_L3_DIP2_FLD = 142,
+ CFA_BLD_FKB_L3_DIP1_FLD = 143,
+ CFA_BLD_FKB_L3_DIP0_FLD = 144,
+ CFA_BLD_FKB_L3_TTL_FLD = 145,
+ CFA_BLD_FKB_L3_PROT_FLD = 146,
+ CFA_BLD_FKB_L3_FID_FLD = 147,
+ CFA_BLD_FKB_L3_QOS_FLD = 148,
+ CFA_BLD_FKB_L3_IEH_NONEXT_FLD = 149,
+ CFA_BLD_FKB_L3_IEH_SEP_FLD = 150,
+ CFA_BLD_FKB_L3_IEH_AUTH_FLD = 151,
+ CFA_BLD_FKB_L3_IEH_DEST_FLD = 152,
+ CFA_BLD_FKB_L3_IEH_FRAG_FLD = 153,
+ CFA_BLD_FKB_L3_IEH_RTHDR_FLD = 154,
+ CFA_BLD_FKB_L3_IEH_HOP_FLD = 155,
+ CFA_BLD_FKB_L3_IEH_1FRAG_FLD = 156,
+ CFA_BLD_FKB_L3_DF_FLD = 157,
+ CFA_BLD_FKB_L3_L3ERR_FLD = 158,
+ CFA_BLD_FKB_L4_TYPE_FLD = 159,
+ CFA_BLD_FKB_L4_SRC_FLD = 160,
+ CFA_BLD_FKB_L4_DST_FLD = 161,
+ CFA_BLD_FKB_L4_FLAGS_FLD = 162,
+ CFA_BLD_FKB_L4_SEQ_FLD = 163,
+ CFA_BLD_FKB_L4_ACK_FLD = 164,
+ CFA_BLD_FKB_L4_WIN_FLD = 165,
+ CFA_BLD_FKB_L4_PA_FLD = 166,
+ CFA_BLD_FKB_L4_OPT_FLD = 167,
+ CFA_BLD_FKB_L4_TCPTS_FLD = 168,
+ CFA_BLD_FKB_L4_TSVAL_FLD = 169,
+ CFA_BLD_FKB_L4_TXECR_FLD = 170,
+ CFA_BLD_FKB_L4_ERR_FLD = 171,
+ CFA_BLD_FKB_MAX_FLD
+};
+
+/**
+ * Enumeration for wc tcam fkb
+ */
+enum cfa_bld_wc_tcam_fkb_flds {
+ CFA_BLD_WC_TCAM_FKB_PROF_ID_FLD = 0,
+ CFA_BLD_WC_TCAM_FKB_L2CTXT_FLD = 1,
+ CFA_BLD_WC_TCAM_FKB_L2FUNC_FLD = 2,
+ CFA_BLD_WC_TCAM_FKB_PARIF_FLD = 3,
+ CFA_BLD_WC_TCAM_FKB_SPIF_FLD = 4,
+ CFA_BLD_WC_TCAM_FKB_SVIF_FLD = 5,
+ CFA_BLD_WC_TCAM_FKB_LCOS_FLD = 6,
+ CFA_BLD_WC_TCAM_FKB_META_HI_FLD = 7,
+ CFA_BLD_WC_TCAM_FKB_META_LO_FLD = 8,
+ CFA_BLD_WC_TCAM_FKB_RCYC_CNT_FLD = 9,
+ CFA_BLD_WC_TCAM_FKB_LOOPBACK_FLD = 10,
+ CFA_BLD_WC_TCAM_FKB_OTL2_TYPE_FLD = 11,
+ CFA_BLD_WC_TCAM_FKB_OTL2_DMAC_FLD = 12,
+ CFA_BLD_WC_TCAM_FKB_OTL2_SMAC_FLD = 13,
+ CFA_BLD_WC_TCAM_FKB_OTL2_DT_FLD = 14,
+ CFA_BLD_WC_TCAM_FKB_OTL2_SA_FLD = 15,
+ CFA_BLD_WC_TCAM_FKB_OTL2_NVT_FLD = 16,
+ CFA_BLD_WC_TCAM_FKB_OTL2_OVP_FLD = 17,
+ CFA_BLD_WC_TCAM_FKB_OTL2_OVD_FLD = 18,
+ CFA_BLD_WC_TCAM_FKB_OTL2_OVV_FLD = 19,
+ CFA_BLD_WC_TCAM_FKB_OTL2_OVT_FLD = 20,
+ CFA_BLD_WC_TCAM_FKB_OTL2_IVP_FLD = 21,
+ CFA_BLD_WC_TCAM_FKB_OTL2_IVD_FLD = 22,
+ CFA_BLD_WC_TCAM_FKB_OTL2_IVV_FLD = 23,
+ CFA_BLD_WC_TCAM_FKB_OTL2_IVT_FLD = 24,
+ CFA_BLD_WC_TCAM_FKB_OTL2_ETYPE_FLD = 25,
+ CFA_BLD_WC_TCAM_FKB_OTL3_TYPE_FLD = 26,
+ CFA_BLD_WC_TCAM_FKB_OTL3_SIP3_FLD = 27,
+ CFA_BLD_WC_TCAM_FKB_OTL3_SIP2_FLD = 28,
+ CFA_BLD_WC_TCAM_FKB_OTL3_SIP1_FLD = 29,
+ CFA_BLD_WC_TCAM_FKB_OTL3_SIP0_FLD = 30,
+ CFA_BLD_WC_TCAM_FKB_OTL3_DIP3_FLD = 31,
+ CFA_BLD_WC_TCAM_FKB_OTL3_DIP2_FLD = 32,
+ CFA_BLD_WC_TCAM_FKB_OTL3_DIP1_FLD = 33,
+ CFA_BLD_WC_TCAM_FKB_OTL3_DIP0_FLD = 34,
+ CFA_BLD_WC_TCAM_FKB_OTL3_TTL_FLD = 35,
+ CFA_BLD_WC_TCAM_FKB_OTL3_PROT_FLD = 36,
+ CFA_BLD_WC_TCAM_FKB_OTL3_FID_FLD = 37,
+ CFA_BLD_WC_TCAM_FKB_OTL3_QOS_FLD = 38,
+ CFA_BLD_WC_TCAM_FKB_OTL3_IEH_NONEXT_FLD = 39,
+ CFA_BLD_WC_TCAM_FKB_OTL3_IEH_SEP_FLD = 40,
+ CFA_BLD_WC_TCAM_FKB_OTL3_IEH_AUTH_FLD = 41,
+ CFA_BLD_WC_TCAM_FKB_OTL3_IEH_DEST_FLD = 42,
+ CFA_BLD_WC_TCAM_FKB_OTL3_IEH_FRAG_FLD = 43,
+ CFA_BLD_WC_TCAM_FKB_OTL3_IEH_RTHDR_FLD = 44,
+ CFA_BLD_WC_TCAM_FKB_OTL3_IEH_HOP_FLD = 45,
+ CFA_BLD_WC_TCAM_FKB_OTL3_IEH_1FRAG_FLD = 46,
+ CFA_BLD_WC_TCAM_FKB_OTL3_DF_FLD = 47,
+ CFA_BLD_WC_TCAM_FKB_OTL3_L3ERR_FLD = 48,
+ CFA_BLD_WC_TCAM_FKB_OTL4_TYPE_FLD = 49,
+ CFA_BLD_WC_TCAM_FKB_OTL4_SRC_FLD = 50,
+ CFA_BLD_WC_TCAM_FKB_OTL4_DST_FLD = 51,
+ CFA_BLD_WC_TCAM_FKB_OTL4_FLAGS_FLD = 52,
+ CFA_BLD_WC_TCAM_FKB_OTL4_SEQ_FLD = 53,
+ CFA_BLD_WC_TCAM_FKB_OTL4_PA_FLD = 54,
+ CFA_BLD_WC_TCAM_FKB_OTL4_OPT_FLD = 55,
+ CFA_BLD_WC_TCAM_FKB_OTL4_TCPTS_FLD = 56,
+ CFA_BLD_WC_TCAM_FKB_OTL4_ERR_FLD = 57,
+ CFA_BLD_WC_TCAM_FKB_OT_TYPE_FLD = 58,
+ CFA_BLD_WC_TCAM_FKB_OT_FLAGS_FLD = 59,
+ CFA_BLD_WC_TCAM_FKB_OT_IDS_FLD = 60,
+ CFA_BLD_WC_TCAM_FKB_OT_ID_FLD = 61,
+ CFA_BLD_WC_TCAM_FKB_OT_CTXTS_FLD = 62,
+ CFA_BLD_WC_TCAM_FKB_OT_CTXT_FLD = 63,
+ CFA_BLD_WC_TCAM_FKB_OT_QOS_FLD = 64,
+ CFA_BLD_WC_TCAM_FKB_OT_ERR_FLD = 65,
+ CFA_BLD_WC_TCAM_FKB_TL2_TYPE_FLD = 66,
+ CFA_BLD_WC_TCAM_FKB_TL2_DMAC_FLD = 67,
+ CFA_BLD_WC_TCAM_FKB_TL2_SMAC_FLD = 68,
+ CFA_BLD_WC_TCAM_FKB_TL2_DT_FLD = 69,
+ CFA_BLD_WC_TCAM_FKB_TL2_SA_FLD = 70,
+ CFA_BLD_WC_TCAM_FKB_TL2_NVT_FLD = 71,
+ CFA_BLD_WC_TCAM_FKB_TL2_OVP_FLD = 72,
+ CFA_BLD_WC_TCAM_FKB_TL2_OVD_FLD = 73,
+ CFA_BLD_WC_TCAM_FKB_TL2_OVV_FLD = 74,
+ CFA_BLD_WC_TCAM_FKB_TL2_OVT_FLD = 75,
+ CFA_BLD_WC_TCAM_FKB_TL2_IVP_FLD = 76,
+ CFA_BLD_WC_TCAM_FKB_TL2_IVD_FLD = 77,
+ CFA_BLD_WC_TCAM_FKB_TL2_IVV_FLD = 78,
+ CFA_BLD_WC_TCAM_FKB_TL2_IVT_FLD = 79,
+ CFA_BLD_WC_TCAM_FKB_TL2_ETYPE_FLD = 80,
+ CFA_BLD_WC_TCAM_FKB_TL3_TYPE_FLD = 81,
+ CFA_BLD_WC_TCAM_FKB_TL3_SIP3_FLD = 82,
+ CFA_BLD_WC_TCAM_FKB_TL3_SIP2_FLD = 83,
+ CFA_BLD_WC_TCAM_FKB_TL3_SIP1_FLD = 84,
+ CFA_BLD_WC_TCAM_FKB_TL3_SIP0_FLD = 85,
+ CFA_BLD_WC_TCAM_FKB_TL3_DIP3_FLD = 86,
+ CFA_BLD_WC_TCAM_FKB_TL3_DIP2_FLD = 87,
+ CFA_BLD_WC_TCAM_FKB_TL3_DIP1_FLD = 88,
+ CFA_BLD_WC_TCAM_FKB_TL3_DIP0_FLD = 89,
+ CFA_BLD_WC_TCAM_FKB_TL3_TTL_FLD = 90,
+ CFA_BLD_WC_TCAM_FKB_TL3_PROT_FLD = 91,
+ CFA_BLD_WC_TCAM_FKB_TL3_FID_FLD = 92,
+ CFA_BLD_WC_TCAM_FKB_TL3_QOS_FLD = 93,
+ CFA_BLD_WC_TCAM_FKB_TL3_IEH_NONEXT_FLD = 94,
+ CFA_BLD_WC_TCAM_FKB_TL3_IEH_SEP_FLD = 95,
+ CFA_BLD_WC_TCAM_FKB_TL3_IEH_AUTH_FLD = 96,
+ CFA_BLD_WC_TCAM_FKB_TL3_IEH_DEST_FLD = 97,
+ CFA_BLD_WC_TCAM_FKB_TL3_IEH_FRAG_FLD = 98,
+ CFA_BLD_WC_TCAM_FKB_TL3_IEH_RTHDR_FLD = 99,
+ CFA_BLD_WC_TCAM_FKB_TL3_IEH_HOP_FLD = 100,
+ CFA_BLD_WC_TCAM_FKB_TL3_IEH_1FRAG_FLD = 101,
+ CFA_BLD_WC_TCAM_FKB_TL3_DF_FLD = 102,
+ CFA_BLD_WC_TCAM_FKB_TL3_L3ERR_FLD = 103,
+ CFA_BLD_WC_TCAM_FKB_TL4_TYPE_FLD = 104,
+ CFA_BLD_WC_TCAM_FKB_TL4_SRC_FLD = 105,
+ CFA_BLD_WC_TCAM_FKB_TL4_DST_FLD = 106,
+ CFA_BLD_WC_TCAM_FKB_TL4_FLAGS_FLD = 107,
+ CFA_BLD_WC_TCAM_FKB_TL4_SEQ_FLD = 108,
+ CFA_BLD_WC_TCAM_FKB_TL4_PA_FLD = 109,
+ CFA_BLD_WC_TCAM_FKB_TL4_OPT_FLD = 110,
+ CFA_BLD_WC_TCAM_FKB_TL4_TCPTS_FLD = 111,
+ CFA_BLD_WC_TCAM_FKB_TL4_ERR_FLD = 112,
+ CFA_BLD_WC_TCAM_FKB_T_TYPE_FLD = 113,
+ CFA_BLD_WC_TCAM_FKB_T_FLAGS_FLD = 114,
+ CFA_BLD_WC_TCAM_FKB_T_IDS_FLD = 115,
+ CFA_BLD_WC_TCAM_FKB_T_ID_FLD = 116,
+ CFA_BLD_WC_TCAM_FKB_T_CTXTS_FLD = 117,
+ CFA_BLD_WC_TCAM_FKB_T_CTXT_FLD = 118,
+ CFA_BLD_WC_TCAM_FKB_T_QOS_FLD = 119,
+ CFA_BLD_WC_TCAM_FKB_T_ERR_FLD = 120,
+ CFA_BLD_WC_TCAM_FKB_L2_TYPE_FLD = 121,
+ CFA_BLD_WC_TCAM_FKB_L2_DMAC_FLD = 122,
+ CFA_BLD_WC_TCAM_FKB_L2_SMAC_FLD = 123,
+ CFA_BLD_WC_TCAM_FKB_L2_DT_FLD = 124,
+ CFA_BLD_WC_TCAM_FKB_L2_SA_FLD = 125,
+ CFA_BLD_WC_TCAM_FKB_L2_NVT_FLD = 126,
+ CFA_BLD_WC_TCAM_FKB_L2_OVP_FLD = 127,
+ CFA_BLD_WC_TCAM_FKB_L2_OVD_FLD = 128,
+ CFA_BLD_WC_TCAM_FKB_L2_OVV_FLD = 129,
+ CFA_BLD_WC_TCAM_FKB_L2_OVT_FLD = 130,
+ CFA_BLD_WC_TCAM_FKB_L2_IVP_FLD = 131,
+ CFA_BLD_WC_TCAM_FKB_L2_IVD_FLD = 132,
+ CFA_BLD_WC_TCAM_FKB_L2_IVV_FLD = 133,
+ CFA_BLD_WC_TCAM_FKB_L2_IVT_FLD = 134,
+ CFA_BLD_WC_TCAM_FKB_L2_ETYPE_FLD = 135,
+ CFA_BLD_WC_TCAM_FKB_L3_TYPE_FLD = 136,
+ CFA_BLD_WC_TCAM_FKB_L3_SIP3_FLD = 137,
+ CFA_BLD_WC_TCAM_FKB_L3_SIP2_FLD = 138,
+ CFA_BLD_WC_TCAM_FKB_L3_SIP1_FLD = 139,
+ CFA_BLD_WC_TCAM_FKB_L3_SIP0_FLD = 140,
+ CFA_BLD_WC_TCAM_FKB_L3_DIP3_FLD = 141,
+ CFA_BLD_WC_TCAM_FKB_L3_DIP2_FLD = 142,
+ CFA_BLD_WC_TCAM_FKB_L3_DIP1_FLD = 143,
+ CFA_BLD_WC_TCAM_FKB_L3_DIP0_FLD = 144,
+ CFA_BLD_WC_TCAM_FKB_L3_TTL_FLD = 145,
+ CFA_BLD_WC_TCAM_FKB_L3_PROT_FLD = 146,
+ CFA_BLD_WC_TCAM_FKB_L3_FID_FLD = 147,
+ CFA_BLD_WC_TCAM_FKB_L3_QOS_FLD = 148,
+ CFA_BLD_WC_TCAM_FKB_L3_IEH_NONEXT_FLD = 149,
+ CFA_BLD_WC_TCAM_FKB_L3_IEH_SEP_FLD = 150,
+ CFA_BLD_WC_TCAM_FKB_L3_IEH_AUTH_FLD = 151,
+ CFA_BLD_WC_TCAM_FKB_L3_IEH_DEST_FLD = 152,
+ CFA_BLD_WC_TCAM_FKB_L3_IEH_FRAG_FLD = 153,
+ CFA_BLD_WC_TCAM_FKB_L3_IEH_RTHDR_FLD = 154,
+ CFA_BLD_WC_TCAM_FKB_L3_IEH_HOP_FLD = 155,
+ CFA_BLD_WC_TCAM_FKB_L3_IEH_1FRAG_FLD = 156,
+ CFA_BLD_WC_TCAM_FKB_L3_DF_FLD = 157,
+ CFA_BLD_WC_TCAM_FKB_L3_L3ERR_FLD = 158,
+ CFA_BLD_WC_TCAM_FKB_L4_TYPE_FLD = 159,
+ CFA_BLD_WC_TCAM_FKB_L4_SRC_FLD = 160,
+ CFA_BLD_WC_TCAM_FKB_L4_DST_FLD = 161,
+ CFA_BLD_WC_TCAM_FKB_L4_FLAGS_FLD = 162,
+ CFA_BLD_WC_TCAM_FKB_L4_SEQ_FLD = 163,
+ CFA_BLD_WC_TCAM_FKB_L4_ACK_FLD = 164,
+ CFA_BLD_WC_TCAM_FKB_L4_WIN_FLD = 165,
+ CFA_BLD_WC_TCAM_FKB_L4_PA_FLD = 166,
+ CFA_BLD_WC_TCAM_FKB_L4_OPT_FLD = 167,
+ CFA_BLD_WC_TCAM_FKB_L4_TCPTS_FLD = 168,
+ CFA_BLD_WC_TCAM_FKB_L4_TSVAL_FLD = 169,
+ CFA_BLD_WC_TCAM_FKB_L4_TXECR_FLD = 170,
+ CFA_BLD_WC_TCAM_FKB_L4_ERR_FLD = 171,
+ CFA_BLD_WC_TCAM_FKB_MAX_FLD
+};
+
+/**
+ * Enumeration for em fkb
+ */
+enum cfa_bld_em_fkb_flds {
+ CFA_BLD_EM_FKB_PROF_ID_FLD = 0,
+ CFA_BLD_EM_FKB_L2CTXT_FLD = 1,
+ CFA_BLD_EM_FKB_L2FUNC_FLD = 2,
+ CFA_BLD_EM_FKB_PARIF_FLD = 3,
+ CFA_BLD_EM_FKB_SPIF_FLD = 4,
+ CFA_BLD_EM_FKB_SVIF_FLD = 5,
+ CFA_BLD_EM_FKB_LCOS_FLD = 6,
+ CFA_BLD_EM_FKB_META_HI_FLD = 7,
+ CFA_BLD_EM_FKB_META_LO_FLD = 8,
+ CFA_BLD_EM_FKB_RCYC_CNT_FLD = 9,
+ CFA_BLD_EM_FKB_LOOPBACK_FLD = 10,
+ CFA_BLD_EM_FKB_OTL2_TYPE_FLD = 11,
+ CFA_BLD_EM_FKB_OTL2_DMAC_FLD = 12,
+ CFA_BLD_EM_FKB_OTL2_SMAC_FLD = 13,
+ CFA_BLD_EM_FKB_OTL2_DT_FLD = 14,
+ CFA_BLD_EM_FKB_OTL2_SA_FLD = 15,
+ CFA_BLD_EM_FKB_OTL2_NVT_FLD = 16,
+ CFA_BLD_EM_FKB_OTL2_OVP_FLD = 17,
+ CFA_BLD_EM_FKB_OTL2_OVD_FLD = 18,
+ CFA_BLD_EM_FKB_OTL2_OVV_FLD = 19,
+ CFA_BLD_EM_FKB_OTL2_OVT_FLD = 20,
+ CFA_BLD_EM_FKB_OTL2_IVP_FLD = 21,
+ CFA_BLD_EM_FKB_OTL2_IVD_FLD = 22,
+ CFA_BLD_EM_FKB_OTL2_IVV_FLD = 23,
+ CFA_BLD_EM_FKB_OTL2_IVT_FLD = 24,
+ CFA_BLD_EM_FKB_OTL2_ETYPE_FLD = 25,
+ CFA_BLD_EM_FKB_OTL3_TYPE_FLD = 26,
+ CFA_BLD_EM_FKB_OTL3_SIP3_FLD = 27,
+ CFA_BLD_EM_FKB_OTL3_SIP2_FLD = 28,
+ CFA_BLD_EM_FKB_OTL3_SIP1_FLD = 29,
+ CFA_BLD_EM_FKB_OTL3_SIP0_FLD = 30,
+ CFA_BLD_EM_FKB_OTL3_DIP3_FLD = 31,
+ CFA_BLD_EM_FKB_OTL3_DIP2_FLD = 32,
+ CFA_BLD_EM_FKB_OTL3_DIP1_FLD = 33,
+ CFA_BLD_EM_FKB_OTL3_DIP0_FLD = 34,
+ CFA_BLD_EM_FKB_OTL3_TTL_FLD = 35,
+ CFA_BLD_EM_FKB_OTL3_PROT_FLD = 36,
+ CFA_BLD_EM_FKB_OTL3_FID_FLD = 37,
+ CFA_BLD_EM_FKB_OTL3_QOS_FLD = 38,
+ CFA_BLD_EM_FKB_OTL3_IEH_NONEXT_FLD = 39,
+ CFA_BLD_EM_FKB_OTL3_IEH_SEP_FLD = 40,
+ CFA_BLD_EM_FKB_OTL3_IEH_AUTH_FLD = 41,
+ CFA_BLD_EM_FKB_OTL3_IEH_DEST_FLD = 42,
+ CFA_BLD_EM_FKB_OTL3_IEH_FRAG_FLD = 43,
+ CFA_BLD_EM_FKB_OTL3_IEH_RTHDR_FLD = 44,
+ CFA_BLD_EM_FKB_OTL3_IEH_HOP_FLD = 45,
+ CFA_BLD_EM_FKB_OTL3_IEH_1FRAG_FLD = 46,
+ CFA_BLD_EM_FKB_OTL3_DF_FLD = 47,
+ CFA_BLD_EM_FKB_OTL3_L3ERR_FLD = 48,
+ CFA_BLD_EM_FKB_OTL4_TYPE_FLD = 49,
+ CFA_BLD_EM_FKB_OTL4_SRC_FLD = 50,
+ CFA_BLD_EM_FKB_OTL4_DST_FLD = 51,
+ CFA_BLD_EM_FKB_OTL4_FLAGS_FLD = 52,
+ CFA_BLD_EM_FKB_OTL4_SEQ_FLD = 53,
+ CFA_BLD_EM_FKB_OTL4_PA_FLD = 54,
+ CFA_BLD_EM_FKB_OTL4_OPT_FLD = 55,
+ CFA_BLD_EM_FKB_OTL4_TCPTS_FLD = 56,
+ CFA_BLD_EM_FKB_OTL4_ERR_FLD = 57,
+ CFA_BLD_EM_FKB_OT_TYPE_FLD = 58,
+ CFA_BLD_EM_FKB_OT_FLAGS_FLD = 59,
+ CFA_BLD_EM_FKB_OT_IDS_FLD = 60,
+ CFA_BLD_EM_FKB_OT_ID_FLD = 61,
+ CFA_BLD_EM_FKB_OT_CTXTS_FLD = 62,
+ CFA_BLD_EM_FKB_OT_CTXT_FLD = 63,
+ CFA_BLD_EM_FKB_OT_QOS_FLD = 64,
+ CFA_BLD_EM_FKB_OT_ERR_FLD = 65,
+ CFA_BLD_EM_FKB_TL2_TYPE_FLD = 66,
+ CFA_BLD_EM_FKB_TL2_DMAC_FLD = 67,
+ CFA_BLD_EM_FKB_TL2_SMAC_FLD = 68,
+ CFA_BLD_EM_FKB_TL2_DT_FLD = 69,
+ CFA_BLD_EM_FKB_TL2_SA_FLD = 70,
+ CFA_BLD_EM_FKB_TL2_NVT_FLD = 71,
+ CFA_BLD_EM_FKB_TL2_OVP_FLD = 72,
+ CFA_BLD_EM_FKB_TL2_OVD_FLD = 73,
+ CFA_BLD_EM_FKB_TL2_OVV_FLD = 74,
+ CFA_BLD_EM_FKB_TL2_OVT_FLD = 75,
+ CFA_BLD_EM_FKB_TL2_IVP_FLD = 76,
+ CFA_BLD_EM_FKB_TL2_IVD_FLD = 77,
+ CFA_BLD_EM_FKB_TL2_IVV_FLD = 78,
+ CFA_BLD_EM_FKB_TL2_IVT_FLD = 79,
+ CFA_BLD_EM_FKB_TL2_ETYPE_FLD = 80,
+ CFA_BLD_EM_FKB_TL3_TYPE_FLD = 81,
+ CFA_BLD_EM_FKB_TL3_SIP3_FLD = 82,
+ CFA_BLD_EM_FKB_TL3_SIP2_FLD = 83,
+ CFA_BLD_EM_FKB_TL3_SIP1_FLD = 84,
+ CFA_BLD_EM_FKB_TL3_SIP0_FLD = 85,
+ CFA_BLD_EM_FKB_TL3_DIP3_FLD = 86,
+ CFA_BLD_EM_FKB_TL3_DIP2_FLD = 87,
+ CFA_BLD_EM_FKB_TL3_DIP1_FLD = 88,
+ CFA_BLD_EM_FKB_TL3_DIP0_FLD = 89,
+ CFA_BLD_EM_FKB_TL3_TTL_FLD = 90,
+ CFA_BLD_EM_FKB_TL3_PROT_FLD = 91,
+ CFA_BLD_EM_FKB_TL3_FID_FLD = 92,
+ CFA_BLD_EM_FKB_TL3_QOS_FLD = 93,
+ CFA_BLD_EM_FKB_TL3_IEH_NONEXT_FLD = 94,
+ CFA_BLD_EM_FKB_TL3_IEH_SEP_FLD = 95,
+ CFA_BLD_EM_FKB_TL3_IEH_AUTH_FLD = 96,
+ CFA_BLD_EM_FKB_TL3_IEH_DEST_FLD = 97,
+ CFA_BLD_EM_FKB_TL3_IEH_FRAG_FLD = 98,
+ CFA_BLD_EM_FKB_TL3_IEH_RTHDR_FLD = 99,
+ CFA_BLD_EM_FKB_TL3_IEH_HOP_FLD = 100,
+ CFA_BLD_EM_FKB_TL3_IEH_1FRAG_FLD = 101,
+ CFA_BLD_EM_FKB_TL3_DF_FLD = 102,
+ CFA_BLD_EM_FKB_TL3_L3ERR_FLD = 103,
+ CFA_BLD_EM_FKB_TL4_TYPE_FLD = 104,
+ CFA_BLD_EM_FKB_TL4_SRC_FLD = 105,
+ CFA_BLD_EM_FKB_TL4_DST_FLD = 106,
+ CFA_BLD_EM_FKB_TL4_FLAGS_FLD = 107,
+ CFA_BLD_EM_FKB_TL4_SEQ_FLD = 108,
+ CFA_BLD_EM_FKB_TL4_PA_FLD = 109,
+ CFA_BLD_EM_FKB_TL4_OPT_FLD = 110,
+ CFA_BLD_EM_FKB_TL4_TCPTS_FLD = 111,
+ CFA_BLD_EM_FKB_TL4_ERR_FLD = 112,
+ CFA_BLD_EM_FKB_T_TYPE_FLD = 113,
+ CFA_BLD_EM_FKB_T_FLAGS_FLD = 114,
+ CFA_BLD_EM_FKB_T_IDS_FLD = 115,
+ CFA_BLD_EM_FKB_T_ID_FLD = 116,
+ CFA_BLD_EM_FKB_T_CTXTS_FLD = 117,
+ CFA_BLD_EM_FKB_T_CTXT_FLD = 118,
+ CFA_BLD_EM_FKB_T_QOS_FLD = 119,
+ CFA_BLD_EM_FKB_T_ERR_FLD = 120,
+ CFA_BLD_EM_FKB_L2_TYPE_FLD = 121,
+ CFA_BLD_EM_FKB_L2_DMAC_FLD = 122,
+ CFA_BLD_EM_FKB_L2_SMAC_FLD = 123,
+ CFA_BLD_EM_FKB_L2_DT_FLD = 124,
+ CFA_BLD_EM_FKB_L2_SA_FLD = 125,
+ CFA_BLD_EM_FKB_L2_NVT_FLD = 126,
+ CFA_BLD_EM_FKB_L2_OVP_FLD = 127,
+ CFA_BLD_EM_FKB_L2_OVD_FLD = 128,
+ CFA_BLD_EM_FKB_L2_OVV_FLD = 129,
+ CFA_BLD_EM_FKB_L2_OVT_FLD = 130,
+ CFA_BLD_EM_FKB_L2_IVP_FLD = 131,
+ CFA_BLD_EM_FKB_L2_IVD_FLD = 132,
+ CFA_BLD_EM_FKB_L2_IVV_FLD = 133,
+ CFA_BLD_EM_FKB_L2_IVT_FLD = 134,
+ CFA_BLD_EM_FKB_L2_ETYPE_FLD = 135,
+ CFA_BLD_EM_FKB_L3_TYPE_FLD = 136,
+ CFA_BLD_EM_FKB_L3_SIP3_FLD = 137,
+ CFA_BLD_EM_FKB_L3_SIP2_FLD = 138,
+ CFA_BLD_EM_FKB_L3_SIP1_FLD = 139,
+ CFA_BLD_EM_FKB_L3_SIP0_FLD = 140,
+ CFA_BLD_EM_FKB_L3_DIP3_FLD = 141,
+ CFA_BLD_EM_FKB_L3_DIP2_FLD = 142,
+ CFA_BLD_EM_FKB_L3_DIP1_FLD = 143,
+ CFA_BLD_EM_FKB_L3_DIP0_FLD = 144,
+ CFA_BLD_EM_FKB_L3_TTL_FLD = 145,
+ CFA_BLD_EM_FKB_L3_PROT_FLD = 146,
+ CFA_BLD_EM_FKB_L3_FID_FLD = 147,
+ CFA_BLD_EM_FKB_L3_QOS_FLD = 148,
+ CFA_BLD_EM_FKB_L3_IEH_NONEXT_FLD = 149,
+ CFA_BLD_EM_FKB_L3_IEH_SEP_FLD = 150,
+ CFA_BLD_EM_FKB_L3_IEH_AUTH_FLD = 151,
+ CFA_BLD_EM_FKB_L3_IEH_DEST_FLD = 152,
+ CFA_BLD_EM_FKB_L3_IEH_FRAG_FLD = 153,
+ CFA_BLD_EM_FKB_L3_IEH_RTHDR_FLD = 154,
+ CFA_BLD_EM_FKB_L3_IEH_HOP_FLD = 155,
+ CFA_BLD_EM_FKB_L3_IEH_1FRAG_FLD = 156,
+ CFA_BLD_EM_FKB_L3_DF_FLD = 157,
+ CFA_BLD_EM_FKB_L3_L3ERR_FLD = 158,
+ CFA_BLD_EM_FKB_L4_TYPE_FLD = 159,
+ CFA_BLD_EM_FKB_L4_SRC_FLD = 160,
+ CFA_BLD_EM_FKB_L4_DST_FLD = 161,
+ CFA_BLD_EM_FKB_L4_FLAGS_FLD = 162,
+ CFA_BLD_EM_FKB_L4_SEQ_FLD = 163,
+ CFA_BLD_EM_FKB_L4_ACK_FLD = 164,
+ CFA_BLD_EM_FKB_L4_WIN_FLD = 165,
+ CFA_BLD_EM_FKB_L4_PA_FLD = 166,
+ CFA_BLD_EM_FKB_L4_OPT_FLD = 167,
+ CFA_BLD_EM_FKB_L4_TCPTS_FLD = 168,
+ CFA_BLD_EM_FKB_L4_TSVAL_FLD = 169,
+ CFA_BLD_EM_FKB_L4_TXECR_FLD = 170,
+ CFA_BLD_EM_FKB_L4_ERR_FLD = 171,
+ CFA_BLD_EM_FKB_MAX_FLD
+};
+
+/**
+ * Enumeration for em key layout
+ */
+enum cfa_bld_em_key_layout_flds {
+ CFA_BLD_EM_KL_RANGE_IDX_FLD = 0,
+ CFA_BLD_EM_KL_RANGE_PROFILE_FLD = 1,
+ CFA_BLD_EM_KL_CREC_TIMER_VALUE_FLD = 2,
+ CFA_BLD_EM_KL_CREC_STATE_FLD = 3,
+ CFA_BLD_EM_KL_CREC_TCP_MSB_OPP_INIT_FLD = 4,
+ CFA_BLD_EM_KL_CREC_TCP_MSB_OPP_FLD = 5,
+ CFA_BLD_EM_KL_CREC_TCP_MSB_LOC_FLD = 6,
+ CFA_BLD_EM_KL_CREC_TCP_WIN_FLD = 7,
+ CFA_BLD_EM_KL_CREC_TCP_UPDT_EN_FLD = 8,
+ CFA_BLD_EM_KL_CREC_TCP_DIR_FLD = 9,
+ CFA_BLD_EM_KL_METADATA_FLD = 10,
+ CFA_BLD_EM_KL_PROF_FUNC_FLD = 11,
+ CFA_BLD_EM_KL_META_PROF_FLD = 12,
+ CFA_BLD_EM_KL_RECYCLE_DEST_FLD = 13,
+ CFA_BLD_EM_KL_FC_PTR_FLD = 14,
+ CFA_BLD_EM_KL_FC_TYPE_FLD = 15,
+ CFA_BLD_EM_KL_FC_OP_FLD = 16,
+ CFA_BLD_EM_KL_PATHS_M1_FLD = 17,
+ CFA_BLD_EM_KL_ACT_REC_SIZE_FLD = 18,
+ CFA_BLD_EM_KL_RING_TABLE_IDX_FLD = 19,
+ CFA_BLD_EM_KL_DESTINATION_FLD = 20,
+ CFA_BLD_EM_KL_ACT_REC_PTR_FLD = 21,
+ CFA_BLD_EM_KL_ACT_HINT_FLD = 22,
+ CFA_BLD_EM_KL_STRENGTH_FLD = 23,
+ CFA_BLD_EM_KL_OPCODE_FLD = 24,
+ CFA_BLD_EM_KL_EPOCH1_FLD = 25,
+ CFA_BLD_EM_KL_EPOCH0_FLD = 26,
+ CFA_BLD_EM_KL_REC_SIZE_FLD = 27,
+ CFA_BLD_EM_KL_VALID_FLD = 28,
+ CFA_BLD_EM_KL_PROF_ID_FLD = 29,
+ CFA_BLD_EM_KL_L2CTXT_FLD = 30,
+ CFA_BLD_EM_KL_L2FUNC_FLD = 31,
+ CFA_BLD_EM_KL_PARIF_FLD = 32,
+ CFA_BLD_EM_KL_SPIF_FLD = 33,
+ CFA_BLD_EM_KL_SVIF_FLD = 34,
+ CFA_BLD_EM_KL_LCOS_FLD = 35,
+ CFA_BLD_EM_KL_META_HI_FLD = 36,
+ CFA_BLD_EM_KL_META_LO_FLD = 37,
+ CFA_BLD_EM_KL_RCYC_CNT_FLD = 38,
+ CFA_BLD_EM_KL_LOOPBACK_FLD = 39,
+ CFA_BLD_EM_KL_OTL2_TYPE_FLD = 40,
+ CFA_BLD_EM_KL_OTL2_DMAC_FLD = 41,
+ CFA_BLD_EM_KL_OTL2_SMAC_FLD = 42,
+ CFA_BLD_EM_KL_OTL2_DT_FLD = 43,
+ CFA_BLD_EM_KL_OTL2_SA_FLD = 44,
+ CFA_BLD_EM_KL_OTL2_NVT_FLD = 45,
+ CFA_BLD_EM_KL_OTL2_OVP_FLD = 46,
+ CFA_BLD_EM_KL_OTL2_OVD_FLD = 47,
+ CFA_BLD_EM_KL_OTL2_OVV_FLD = 48,
+ CFA_BLD_EM_KL_OTL2_OVT_FLD = 49,
+ CFA_BLD_EM_KL_OTL2_IVP_FLD = 50,
+ CFA_BLD_EM_KL_OTL2_IVD_FLD = 51,
+ CFA_BLD_EM_KL_OTL2_IVV_FLD = 52,
+ CFA_BLD_EM_KL_OTL2_IVT_FLD = 53,
+ CFA_BLD_EM_KL_OTL2_ETYPE_FLD = 54,
+ CFA_BLD_EM_KL_OTL3_TYPE_FLD = 55,
+ CFA_BLD_EM_KL_OTL3_SIP3_FLD = 56,
+ CFA_BLD_EM_KL_OTL3_SIP2_FLD = 57,
+ CFA_BLD_EM_KL_OTL3_SIP1_FLD = 58,
+ CFA_BLD_EM_KL_OTL3_SIP0_FLD = 59,
+ CFA_BLD_EM_KL_OTL3_DIP3_FLD = 60,
+ CFA_BLD_EM_KL_OTL3_DIP2_FLD = 61,
+ CFA_BLD_EM_KL_OTL3_DIP1_FLD = 62,
+ CFA_BLD_EM_KL_OTL3_DIP0_FLD = 63,
+ CFA_BLD_EM_KL_OTL3_TTL_FLD = 64,
+ CFA_BLD_EM_KL_OTL3_PROT_FLD = 65,
+ CFA_BLD_EM_KL_OTL3_FID_FLD = 66,
+ CFA_BLD_EM_KL_OTL3_QOS_FLD = 67,
+ CFA_BLD_EM_KL_OTL3_IEH_NONEXT_FLD = 68,
+ CFA_BLD_EM_KL_OTL3_IEH_SEP_FLD = 69,
+ CFA_BLD_EM_KL_OTL3_IEH_AUTH_FLD = 70,
+ CFA_BLD_EM_KL_OTL3_IEH_DEST_FLD = 71,
+ CFA_BLD_EM_KL_OTL3_IEH_FRAG_FLD = 72,
+ CFA_BLD_EM_KL_OTL3_IEH_RTHDR_FLD = 73,
+ CFA_BLD_EM_KL_OTL3_IEH_HOP_FLD = 74,
+ CFA_BLD_EM_KL_OTL3_IEH_1FRAG_FLD = 75,
+ CFA_BLD_EM_KL_OTL3_DF_FLD = 76,
+ CFA_BLD_EM_KL_OTL3_L3ERR_FLD = 77,
+ CFA_BLD_EM_KL_OTL4_TYPE_FLD = 78,
+ CFA_BLD_EM_KL_OTL4_SRC_FLD = 79,
+ CFA_BLD_EM_KL_OTL4_DST_FLD = 80,
+ CFA_BLD_EM_KL_OTL4_FLAGS_FLD = 81,
+ CFA_BLD_EM_KL_OTL4_SEQ_FLD = 82,
+ CFA_BLD_EM_KL_OTL4_PA_FLD = 83,
+ CFA_BLD_EM_KL_OTL4_OPT_FLD = 84,
+ CFA_BLD_EM_KL_OTL4_TCPTS_FLD = 85,
+ CFA_BLD_EM_KL_OTL4_ERR_FLD = 86,
+ CFA_BLD_EM_KL_OT_TYPE_FLD = 87,
+ CFA_BLD_EM_KL_OT_FLAGS_FLD = 88,
+ CFA_BLD_EM_KL_OT_IDS_FLD = 89,
+ CFA_BLD_EM_KL_OT_ID_FLD = 90,
+ CFA_BLD_EM_KL_OT_CTXTS_FLD = 91,
+ CFA_BLD_EM_KL_OT_CTXT_FLD = 92,
+ CFA_BLD_EM_KL_OT_QOS_FLD = 93,
+ CFA_BLD_EM_KL_OT_ERR_FLD = 94,
+ CFA_BLD_EM_KL_TL2_TYPE_FLD = 95,
+ CFA_BLD_EM_KL_TL2_DMAC_FLD = 96,
+ CFA_BLD_EM_KL_TL2_SMAC_FLD = 97,
+ CFA_BLD_EM_KL_TL2_DT_FLD = 98,
+ CFA_BLD_EM_KL_TL2_SA_FLD = 99,
+ CFA_BLD_EM_KL_TL2_NVT_FLD = 100,
+ CFA_BLD_EM_KL_TL2_OVP_FLD = 101,
+ CFA_BLD_EM_KL_TL2_OVD_FLD = 102,
+ CFA_BLD_EM_KL_TL2_OVV_FLD = 103,
+ CFA_BLD_EM_KL_TL2_OVT_FLD = 104,
+ CFA_BLD_EM_KL_TL2_IVP_FLD = 105,
+ CFA_BLD_EM_KL_TL2_IVD_FLD = 106,
+ CFA_BLD_EM_KL_TL2_IVV_FLD = 107,
+ CFA_BLD_EM_KL_TL2_IVT_FLD = 108,
+ CFA_BLD_EM_KL_TL2_ETYPE_FLD = 109,
+ CFA_BLD_EM_KL_TL3_TYPE_FLD = 110,
+ CFA_BLD_EM_KL_TL3_SIP3_FLD = 111,
+ CFA_BLD_EM_KL_TL3_SIP2_FLD = 112,
+ CFA_BLD_EM_KL_TL3_SIP1_FLD = 113,
+ CFA_BLD_EM_KL_TL3_SIP0_FLD = 114,
+ CFA_BLD_EM_KL_TL3_DIP3_FLD = 115,
+ CFA_BLD_EM_KL_TL3_DIP2_FLD = 116,
+ CFA_BLD_EM_KL_TL3_DIP1_FLD = 117,
+ CFA_BLD_EM_KL_TL3_DIP0_FLD = 118,
+ CFA_BLD_EM_KL_TL3_TTL_FLD = 119,
+ CFA_BLD_EM_KL_TL3_PROT_FLD = 120,
+ CFA_BLD_EM_KL_TL3_FID_FLD = 121,
+ CFA_BLD_EM_KL_TL3_QOS_FLD = 122,
+ CFA_BLD_EM_KL_TL3_IEH_NONEXT_FLD = 123,
+ CFA_BLD_EM_KL_TL3_IEH_SEP_FLD = 124,
+ CFA_BLD_EM_KL_TL3_IEH_AUTH_FLD = 125,
+ CFA_BLD_EM_KL_TL3_IEH_DEST_FLD = 126,
+ CFA_BLD_EM_KL_TL3_IEH_FRAG_FLD = 127,
+ CFA_BLD_EM_KL_TL3_IEH_RTHDR_FLD = 128,
+ CFA_BLD_EM_KL_TL3_IEH_HOP_FLD = 129,
+ CFA_BLD_EM_KL_TL3_IEH_1FRAG_FLD = 130,
+ CFA_BLD_EM_KL_TL3_DF_FLD = 131,
+ CFA_BLD_EM_KL_TL3_L3ERR_FLD = 132,
+ CFA_BLD_EM_KL_TL4_TYPE_FLD = 133,
+ CFA_BLD_EM_KL_TL4_SRC_FLD = 134,
+ CFA_BLD_EM_KL_TL4_DST_FLD = 135,
+ CFA_BLD_EM_KL_TL4_FLAGS_FLD = 136,
+ CFA_BLD_EM_KL_TL4_SEQ_FLD = 137,
+ CFA_BLD_EM_KL_TL4_PA_FLD = 138,
+ CFA_BLD_EM_KL_TL4_OPT_FLD = 139,
+ CFA_BLD_EM_KL_TL4_TCPTS_FLD = 140,
+ CFA_BLD_EM_KL_TL4_ERR_FLD = 141,
+ CFA_BLD_EM_KL_T_TYPE_FLD = 142,
+ CFA_BLD_EM_KL_T_FLAGS_FLD = 143,
+ CFA_BLD_EM_KL_T_IDS_FLD = 144,
+ CFA_BLD_EM_KL_T_ID_FLD = 145,
+ CFA_BLD_EM_KL_T_CTXTS_FLD = 146,
+ CFA_BLD_EM_KL_T_CTXT_FLD = 147,
+ CFA_BLD_EM_KL_T_QOS_FLD = 148,
+ CFA_BLD_EM_KL_T_ERR_FLD = 149,
+ CFA_BLD_EM_KL_L2_TYPE_FLD = 150,
+ CFA_BLD_EM_KL_L2_DMAC_FLD = 151,
+ CFA_BLD_EM_KL_L2_SMAC_FLD = 152,
+ CFA_BLD_EM_KL_L2_DT_FLD = 153,
+ CFA_BLD_EM_KL_L2_SA_FLD = 154,
+ CFA_BLD_EM_KL_L2_NVT_FLD = 155,
+ CFA_BLD_EM_KL_L2_OVP_FLD = 156,
+ CFA_BLD_EM_KL_L2_OVD_FLD = 157,
+ CFA_BLD_EM_KL_L2_OVV_FLD = 158,
+ CFA_BLD_EM_KL_L2_OVT_FLD = 159,
+ CFA_BLD_EM_KL_L2_IVP_FLD = 160,
+ CFA_BLD_EM_KL_L2_IVD_FLD = 161,
+ CFA_BLD_EM_KL_L2_IVV_FLD = 162,
+ CFA_BLD_EM_KL_L2_IVT_FLD = 163,
+ CFA_BLD_EM_KL_L2_ETYPE_FLD = 164,
+ CFA_BLD_EM_KL_L3_TYPE_FLD = 165,
+ CFA_BLD_EM_KL_L3_SIP3_FLD = 166,
+ CFA_BLD_EM_KL_L3_SIP2_FLD = 167,
+ CFA_BLD_EM_KL_L3_SIP1_FLD = 168,
+ CFA_BLD_EM_KL_L3_SIP0_FLD = 169,
+ CFA_BLD_EM_KL_L3_DIP3_FLD = 170,
+ CFA_BLD_EM_KL_L3_DIP2_FLD = 171,
+ CFA_BLD_EM_KL_L3_DIP1_FLD = 172,
+ CFA_BLD_EM_KL_L3_DIP0_FLD = 173,
+ CFA_BLD_EM_KL_L3_TTL_FLD = 174,
+ CFA_BLD_EM_KL_L3_PROT_FLD = 175,
+ CFA_BLD_EM_KL_L3_FID_FLD = 176,
+ CFA_BLD_EM_KL_L3_QOS_FLD = 177,
+ CFA_BLD_EM_KL_L3_IEH_NONEXT_FLD = 178,
+ CFA_BLD_EM_KL_L3_IEH_SEP_FLD = 179,
+ CFA_BLD_EM_KL_L3_IEH_AUTH_FLD = 180,
+ CFA_BLD_EM_KL_L3_IEH_DEST_FLD = 181,
+ CFA_BLD_EM_KL_L3_IEH_FRAG_FLD = 182,
+ CFA_BLD_EM_KL_L3_IEH_RTHDR_FLD = 183,
+ CFA_BLD_EM_KL_L3_IEH_HOP_FLD = 184,
+ CFA_BLD_EM_KL_L3_IEH_1FRAG_FLD = 185,
+ CFA_BLD_EM_KL_L3_DF_FLD = 186,
+ CFA_BLD_EM_KL_L3_L3ERR_FLD = 187,
+ CFA_BLD_EM_KL_L4_TYPE_FLD = 188,
+ CFA_BLD_EM_KL_L4_SRC_FLD = 189,
+ CFA_BLD_EM_KL_L4_DST_FLD = 190,
+ CFA_BLD_EM_KL_L4_FLAGS_FLD = 191,
+ CFA_BLD_EM_KL_L4_SEQ_FLD = 192,
+ CFA_BLD_EM_KL_L4_ACK_FLD = 193,
+ CFA_BLD_EM_KL_L4_WIN_FLD = 194,
+ CFA_BLD_EM_KL_L4_PA_FLD = 195,
+ CFA_BLD_EM_KL_L4_OPT_FLD = 196,
+ CFA_BLD_EM_KL_L4_TCPTS_FLD = 197,
+ CFA_BLD_EM_KL_L4_TSVAL_FLD = 198,
+ CFA_BLD_EM_KL_L4_TXECR_FLD = 199,
+ CFA_BLD_EM_KL_L4_ERR_FLD = 200,
+ CFA_BLD_EM_KEY_LAYOUT_MAX_FLD = 201,
+};
+
+/**
+ * Enumeration for action
+ */
+enum cfa_bld_action_flds {
+ CFA_BLD_ACT_TYPE_FLD = 0,
+ CFA_BLD_ACT_DROP_FLD = 1,
+ CFA_BLD_ACT_VLAN_DELETE_FLD = 2,
+ CFA_BLD_ACT_DEST_FLD = 3,
+ CFA_BLD_ACT_DEST_OP_FLD = 4,
+ CFA_BLD_ACT_DECAP_FLD = 5,
+ CFA_BLD_ACT_MIRRORING_FLD = 6,
+ CFA_BLD_ACT_METER_PTR_FLD = 7,
+ CFA_BLD_ACT_STAT0_OFF_FLD = 8,
+ CFA_BLD_ACT_STAT0_OP_FLD = 9,
+ CFA_BLD_ACT_STAT0_CTR_TYPE_FLD = 10,
+ CFA_BLD_ACT_MOD_OFF_FLD = 11,
+ CFA_BLD_ACT_ENC_OFF_FLD = 12,
+ CFA_BLD_ACT_SRC_OFF_FLD = 13,
+ CFA_BLD_ACT_COMPACT_RSVD_0_FLD = 14,
+ CFA_BLD_ACT_STAT0_PTR_FLD = 15,
+ CFA_BLD_ACT_STAT1_PTR_FLD = 16,
+ CFA_BLD_ACT_STAT1_OP_FLD = 17,
+ CFA_BLD_ACT_STAT1_CTR_TYPE_FLD = 18,
+ CFA_BLD_ACT_MOD_PTR_FLD = 19,
+ CFA_BLD_ACT_ENC_PTR_FLD = 20,
+ CFA_BLD_ACT_SRC_PTR_FLD = 21,
+ CFA_BLD_ACT_FULL_RSVD_0_FLD = 22,
+ CFA_BLD_ACT_SRC_KO_EN_FLD = 23,
+ CFA_BLD_ACT_MCG_RSVD_0_FLD = 24,
+ CFA_BLD_ACT_NEXT_PTR_FLD = 25,
+ CFA_BLD_ACT_PTR0_ACT_HINT_FLD = 26,
+ CFA_BLD_ACT_PTR0_ACT_REC_PTR_FLD = 27,
+ CFA_BLD_ACT_PTR1_ACT_HINT_FLD = 28,
+ CFA_BLD_ACT_PTR1_ACT_REC_PTR_FLD = 29,
+ CFA_BLD_ACT_PTR2_ACT_HINT_FLD = 30,
+ CFA_BLD_ACT_PTR2_ACT_REC_PTR_FLD = 31,
+ CFA_BLD_ACT_PTR3_ACT_HINT_FLD = 32,
+ CFA_BLD_ACT_PTR3_ACT_REC_PTR_FLD = 33,
+ CFA_BLD_ACT_PTR4_ACT_HINT_FLD = 34,
+ CFA_BLD_ACT_PTR4_ACT_REC_PTR_FLD = 35,
+ CFA_BLD_ACT_PTR5_ACT_HINT_FLD = 36,
+ CFA_BLD_ACT_PTR5_ACT_REC_PTR_FLD = 37,
+ CFA_BLD_ACT_PTR6_ACT_HINT_FLD = 38,
+ CFA_BLD_ACT_PTR6_ACT_REC_PTR_FLD = 39,
+ CFA_BLD_ACT_PTR7_ACT_HINT_FLD = 40,
+ CFA_BLD_ACT_PTR7_ACT_REC_PTR_FLD = 41,
+ CFA_BLD_ACT_MCG_SUBSEQ_RSVD_0_FLD = 42,
+ CFA_BLD_ACT_MOD_MODIFY_ACT_HDR_FLD = 43,
+ CFA_BLD_ACT_MOD_MD_UPDT_DATA_FLD = 44,
+ CFA_BLD_ACT_MOD_MD_UPDT_PROF_FLD = 45,
+ CFA_BLD_ACT_MOD_MD_UPDT_OP_FLD = 46,
+ CFA_BLD_ACT_MOD_MD_UPDT_RSVD_0_FLD = 47,
+ CFA_BLD_ACT_MOD_MD_UPDT_TOP_FLD = 48,
+ CFA_BLD_ACT_MOD_RM_OVLAN_FLD = 49,
+ CFA_BLD_ACT_MOD_RM_IVLAN_FLD = 50,
+ CFA_BLD_ACT_MOD_RPL_IVLAN_FLD = 51,
+ CFA_BLD_ACT_MOD_RPL_OVLAN_FLD = 52,
+ CFA_BLD_ACT_MOD_TTL_UPDT_OP_FLD = 53,
+ CFA_BLD_ACT_MOD_TTL_UPDT_ALT_VID_FLD = 54,
+ CFA_BLD_ACT_MOD_TTL_UPDT_ALT_PFID_FLD = 55,
+ CFA_BLD_ACT_MOD_TTL_UPDT_TOP_FLD = 56,
+ CFA_BLD_ACT_MOD_TNL_MODIFY_DEL_FLD = 57,
+ CFA_BLD_ACT_MOD_TNL_MODIFY_8B_NEW_PROT_FLD = 58,
+ CFA_BLD_ACT_MOD_TNL_MODIFY_8B_EXIST_PROT_FLD = 59,
+ CFA_BLD_ACT_MOD_TNL_MODIFY_8B_VEC_FLD = 60,
+ CFA_BLD_ACT_MOD_TNL_MODIFY_8B_TOP_FLD = 61,
+ CFA_BLD_ACT_MOD_TNL_MODIFY_16B_NEW_PROT_FLD = 62,
+ CFA_BLD_ACT_MOD_TNL_MODIFY_16B_EXIST_PROT_FLD = 63,
+ CFA_BLD_ACT_MOD_TNL_MODIFY_16B_VEC_FLD = 64,
+ CFA_BLD_ACT_MOD_TNL_MODIFY_16B_TOP_FLD = 65,
+ CFA_BLD_ACT_MOD_UPDT_FIELD_DATA0_FLD = 66,
+ CFA_BLD_ACT_MOD_UPDT_FIELD_VEC_RSVD_FLD = 67,
+ CFA_BLD_ACT_MOD_UPDT_FIELD_VEC_KID_FLD = 68,
+ CFA_BLD_ACT_MOD_UPDT_FIELD_TOP_FLD = 69,
+ CFA_BLD_ACT_MOD_SMAC_FLD = 70,
+ CFA_BLD_ACT_MOD_DMAC_FLD = 71,
+ CFA_BLD_ACT_MOD_SIPV6_FLD = 72,
+ CFA_BLD_ACT_MOD_DIPV6_FLD = 73,
+ CFA_BLD_ACT_MOD_SIPV4_FLD = 74,
+ CFA_BLD_ACT_MOD_DIPV4_FLD = 75,
+ CFA_BLD_ACT_MOD_SPORT_FLD = 76,
+ CFA_BLD_ACT_MOD_DPORT_FLD = 77,
+ CFA_BLD_ACT_ENC_ECV_TNL_FLD = 78,
+ CFA_BLD_ACT_ENC_ECV_L4_FLD = 79,
+ CFA_BLD_ACT_ENC_ECV_L3_FLD = 80,
+ CFA_BLD_ACT_ENC_ECV_L2_FLD = 81,
+ CFA_BLD_ACT_ENC_ECV_VTAG_FLD = 82,
+ CFA_BLD_ACT_ENC_ECV_EC_FLD = 83,
+ CFA_BLD_ACT_ENC_ECV_VALID_FLD = 84,
+ CFA_BLD_ACT_ENC_EC_IP_TTL_IH_FLD = 85,
+ CFA_BLD_ACT_ENC_EC_IP_TOS_IH_FLD = 86,
+ CFA_BLD_ACT_ENC_EC_TUN_QOS_FLD = 87,
+ CFA_BLD_ACT_ENC_EC_GRE_SET_K_FLD = 88,
+ CFA_BLD_ACT_ENC_EC_DMAC_OVR_FLD = 89,
+ CFA_BLD_ACT_ENC_EC_VLAN_OVR_FLD = 90,
+ CFA_BLD_ACT_ENC_EC_SMAC_OVR_FLD = 91,
+ CFA_BLD_ACT_ENC_EC_IPV4_ID_CTRL_FLD = 92,
+ CFA_BLD_ACT_ENC_L2_DMAC_FLD = 93,
+ CFA_BLD_ACT_ENC_VLAN1_TAG_VID_FLD = 94,
+ CFA_BLD_ACT_ENC_VLAN1_TAG_DE_FLD = 95,
+ CFA_BLD_ACT_ENC_VLAN1_TAG_PRI_FLD = 96,
+ CFA_BLD_ACT_ENC_VLAN1_TAG_TPID_FLD = 97,
+ CFA_BLD_ACT_ENC_VLAN2_IT_VID_FLD = 98,
+ CFA_BLD_ACT_ENC_VLAN2_IT_DE_FLD = 99,
+ CFA_BLD_ACT_ENC_VLAN2_IT_PRI_FLD = 100,
+ CFA_BLD_ACT_ENC_VLAN2_IT_TPID_FLD = 101,
+ CFA_BLD_ACT_ENC_VLAN2_OT_VID_FLD = 102,
+ CFA_BLD_ACT_ENC_VLAN2_OT_DE_FLD = 103,
+ CFA_BLD_ACT_ENC_VLAN2_OT_PRI_FLD = 104,
+ CFA_BLD_ACT_ENC_VLAN2_OT_TPID_FLD = 105,
+ CFA_BLD_ACT_ENC_IPV4_ID_FLD = 106,
+ CFA_BLD_ACT_ENC_IPV4_TOS_FLD = 107,
+ CFA_BLD_ACT_ENC_IPV4_HLEN_FLD = 108,
+ CFA_BLD_ACT_ENC_IPV4_VER_FLD = 109,
+ CFA_BLD_ACT_ENC_IPV4_PROT_FLD = 110,
+ CFA_BLD_ACT_ENC_IPV4_TTL_FLD = 111,
+ CFA_BLD_ACT_ENC_IPV4_FRAG_FLD = 112,
+ CFA_BLD_ACT_ENC_IPV4_FLAGS_FLD = 113,
+ CFA_BLD_ACT_ENC_IPV4_DEST_FLD = 114,
+ CFA_BLD_ACT_ENC_IPV6_FLOW_LABEL_FLD = 115,
+ CFA_BLD_ACT_ENC_IPV6_TRAFFIC_CLASS_FLD = 116,
+ CFA_BLD_ACT_ENC_IPV6_VER_FLD = 117,
+ CFA_BLD_ACT_ENC_IPV6_HOP_LIMIT_FLD = 118,
+ CFA_BLD_ACT_ENC_IPV6_NEXT_HEADER_FLD = 119,
+ CFA_BLD_ACT_ENC_IPV6_PAYLOAD_LENGTH_FLD = 120,
+ CFA_BLD_ACT_ENC_IPV6_DEST_FLD = 121,
+ CFA_BLD_ACT_ENC_MPLS_TAG1_FLD = 122,
+ CFA_BLD_ACT_ENC_MPLS_TAG2_FLD = 123,
+ CFA_BLD_ACT_ENC_MPLS_TAG3_FLD = 124,
+ CFA_BLD_ACT_ENC_MPLS_TAG4_FLD = 125,
+ CFA_BLD_ACT_ENC_MPLS_TAG5_FLD = 126,
+ CFA_BLD_ACT_ENC_MPLS_TAG6_FLD = 127,
+ CFA_BLD_ACT_ENC_MPLS_TAG7_FLD = 128,
+ CFA_BLD_ACT_ENC_MPLS_TAG8_FLD = 129,
+ CFA_BLD_ACT_ENC_L4_DEST_PORT_FLD = 130,
+ CFA_BLD_ACT_ENC_L4_SRC_PORT_FLD = 131,
+ CFA_BLD_ACT_ENC_TNL_VXLAN_NEXT_PROT_FLD = 132,
+ CFA_BLD_ACT_ENC_TNL_VXLAN_RSVD_0_FLD = 133,
+ CFA_BLD_ACT_ENC_TNL_VXLAN_FLAGS_FLD = 134,
+ CFA_BLD_ACT_ENC_TNL_VXLAN_RSVD_1_FLD = 135,
+ CFA_BLD_ACT_ENC_TNL_VXLAN_VNI_FLD = 136,
+ CFA_BLD_ACT_ENC_TNL_NGE_PROT_TYPE_FLD = 137,
+ CFA_BLD_ACT_ENC_TNL_NGE_RSVD_0_FLD = 138,
+ CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_C_FLD = 139,
+ CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_O_FLD = 140,
+ CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_OPT_LEN_FLD = 141,
+ CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_VER_FLD = 142,
+ CFA_BLD_ACT_ENC_TNL_NGE_RSVD_1_FLD = 143,
+ CFA_BLD_ACT_ENC_TNL_NGE_VNI_FLD = 144,
+ CFA_BLD_ACT_ENC_TNL_NGE_OPTIONS_FLD = 145,
+ CFA_BLD_ACT_ENC_TNL_NVGRE_FLOW_ID_FLD = 146,
+ CFA_BLD_ACT_ENC_TNL_NVGRE_VSID_FLD = 147,
+ CFA_BLD_ACT_ENC_TNL_GRE_KEY_FLD = 148,
+ CFA_BLD_ACT_ENC_TNL_GENERIC_TID_FLD = 149,
+ CFA_BLD_ACT_ENC_TNL_GENERIC_LENGTH_FLD = 150,
+ CFA_BLD_ACT_ENC_TNL_GENERIC_HEADER_FLD = 151,
+ CFA_BLD_ACT_ENC_SPDNIC_SIZE_FLD = 152,
+ CFA_BLD_ACT_ENC_SPDNIC_TID_FLD = 153,
+ CFA_BLD_ACT_ENC_SPDNIC_FLAGS_FLD = 154,
+ CFA_BLD_ACT_ENC_SPDNIC_RSVD_FLD = 155,
+ CFA_BLD_ACT_SRC_MAC_FLD = 156,
+ CFA_BLD_ACT_SRC_IPV4_ADDR_FLD = 157,
+ CFA_BLD_ACT_SRC_IPV6_ADDR_FLD = 158,
+ CFA_BLD_ACT_STAT0_B16_FPC_FLD = 159,
+ CFA_BLD_ACT_STAT1_B16_FPC_FLD = 160,
+ CFA_BLD_ACT_STAT0_B16_FBC_FLD = 161,
+ CFA_BLD_ACT_STAT1_B16_FBC_FLD = 162,
+ CFA_BLD_ACT_STAT0_B24_FPC_FLD = 163,
+ CFA_BLD_ACT_STAT1_B24_FPC_FLD = 164,
+ CFA_BLD_ACT_STAT0_B24_FBC_FLD = 165,
+ CFA_BLD_ACT_STAT1_B24_FBC_FLD = 166,
+ CFA_BLD_ACT_STAT0_B24_TIMESTAMP_FLD = 167,
+ CFA_BLD_ACT_STAT1_B24_TIMESTAMP_FLD = 168,
+ CFA_BLD_ACT_STAT0_B24_TCP_FLAGS_FLD = 169,
+ CFA_BLD_ACT_STAT1_B24_TCP_FLAGS_FLD = 170,
+ CFA_BLD_ACT_STAT0_B24_UNUSED_0_FLD = 171,
+ CFA_BLD_ACT_STAT1_B24_UNUSED_0_FLD = 172,
+ CFA_BLD_ACT_STAT0_B32A_FPC_FLD = 173,
+ CFA_BLD_ACT_STAT1_B32A_FPC_FLD = 174,
+ CFA_BLD_ACT_STAT0_B32A_FBC_FLD = 175,
+ CFA_BLD_ACT_STAT1_B32A_FBC_FLD = 176,
+ CFA_BLD_ACT_STAT0_B32A_MPC_FLD = 177,
+ CFA_BLD_ACT_STAT1_B32A_MPC_FLD = 178,
+ CFA_BLD_ACT_STAT0_B32A_MBC_FLD = 179,
+ CFA_BLD_ACT_STAT1_B32A_MBC_FLD = 180,
+ CFA_BLD_ACT_STAT0_B32B_FPC_FLD = 181,
+ CFA_BLD_ACT_STAT1_B32B_FPC_FLD = 182,
+ CFA_BLD_ACT_STAT0_B32B_FBC_FLD = 183,
+ CFA_BLD_ACT_STAT1_B32B_FBC_FLD = 184,
+ CFA_BLD_ACT_STAT0_B32B_TIMESTAMP_FLD = 185,
+ CFA_BLD_ACT_STAT1_B32B_TIMESTAMP_FLD = 186,
+ CFA_BLD_ACT_STAT0_B32B_TCP_FLAGS_FLD = 187,
+ CFA_BLD_ACT_STAT1_B32B_TCP_FLAGS_FLD = 188,
+ CFA_BLD_ACT_STAT0_B32B_UNUSED_0_FLD = 189,
+ CFA_BLD_ACT_STAT1_B32B_UNUSED_0_FLD = 190,
+ CFA_BLD_ACT_STAT0_B32B_MPC15_0_FLD = 191,
+ CFA_BLD_ACT_STAT1_B32B_MPC15_0_FLD = 192,
+ CFA_BLD_ACT_STAT0_B32B_MPC37_16_FLD = 193,
+ CFA_BLD_ACT_STAT1_B32B_MPC37_16_FLD = 194,
+ CFA_BLD_ACT_STAT0_B32B_MBC_FLD = 195,
+ CFA_BLD_ACT_STAT1_B32B_MBC_FLD = 196,
+ CFA_BLD_ACTION_MAX_FLD = 197,
+};
+
+#endif /* _CFA_BLD_FIELD_IDS_H_ */
new file mode 100644
@@ -0,0 +1,1286 @@
+/****************************************************************************
+ * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * Name: cfa_bld_mpc_field_ids.h
+ *
+ * Description: Enumeration definitions for the MPC command/response fields
+ * across multiple hw versions of CFA.
+ *
+ * This file is independent of the CFA HW version and defines the
+ * superset of the enumeration values for MPC command/response
+ * structure fields. This file is meant for use by host applications
+ * that support multiple devices with different CFA Hw versions.
+ *
+ * These enum definitions should be updated whenever any of the
+ * definitions in the auto-generated header 'cfa_bld_pxx_field_ids.h'
+ * file gets any new enum values.
+ *
+ ****************************************************************************/
+#ifndef _CFA_BLD_MPC_FIELD_IDS_H_
+#define _CFA_BLD_MPC_FIELD_IDS_H_
+
+/**
+ * CFA Hardware Cache Table Type
+ */
+enum cfa_bld_mpc_hw_table_type {
+ CFA_BLD_MPC_HW_TABLE_TYPE_ACTION, /**< CFA Action Record Table */
+ CFA_BLD_MPC_HW_TABLE_TYPE_LOOKUP, /**< CFA EM Lookup Record Table */
+ CFA_BLD_MPC_HW_TABLE_TYPE_MAX
+};
+
+/*
+ * CFA MPC Cache access reading mode
+ * To be used as a value for CFA_BLD_MPC_READ_CMD_CACHE_OPTION_FLD
+ */
+enum cfa_bld_mpc_read_mode {
+ CFA_BLD_MPC_RD_NORMAL, /**< Normal read mode */
+ CFA_BLD_MPC_RD_EVICT, /**< Read the cache and evict the cache line */
+ CFA_BLD_MPC_RD_DEBUG_LINE, /**< Debug read line mode */
+ CFA_BLD_MPC_RD_DEBUG_TAG, /**< Debug read tag mode */
+ CFA_BLD_MPC_RD_MODE_MAX
+};
+
+/**
+ * CFA MPC Cache access writing mode
+ * To be used as a value for CFA_BLD_MPC_WRITE_CMD_CACHE_OPTION_FLD
+ */
+enum cfa_bld_mpc_write_mode {
+ CFA_BLD_MPC_WR_WRITE_THRU, /**< Write to cache in Write through mode */
+ CFA_BLD_MPC_WR_WRITE_BACK, /**< Write to cache in Write back mode */
+ CFA_BLD_MPC_WR_MODE_MAX
+};
+
+/**
+ * CFA MPC Cache access eviction mode
+ * To be used as a value for CFA_BLD_MPC_INVALIDATE_CMD_CACHE_OPTION_FLD
+ */
+enum cfa_bld_mpc_evict_mode {
+ /**
+ * Line evict: These modes evict a single cache line
+ * In these modes, the eviction occurs regardless of the cache line
+ * state (CLEAN/CLEAN_FAST_EVICT/DIRTY)
+ */
+ /* Cache line addressed by set/way is evicted */
+ CFA_BLD_MPC_EV_EVICT_LINE,
+ /* Cache line hit with the table scope/address tuple is evicted */
+ CFA_BLD_MPC_EV_EVICT_SCOPE_ADDRESS,
+
+ /**
+ * Set Evict: These modes evict cache lines that meet certain criteria
+ * from the entire cache set.
+ */
+ /*
+ * Cache lines only in CLEAN state are evicted from the set
+ * derived from the address
+ */
+ CFA_BLD_MPC_EV_EVICT_CLEAN_LINES,
+ /*
+ * Cache lines only in CLEAN_FAST_EVICT state are evicted from
+ * the set derived from the address
+ */
+ CFA_BLD_MPC_EV_EVICT_CLEAN_FAST_EVICT_LINES,
+ /*
+ * Cache lines in both CLEAN and CLEAN_FAST_EVICT states are
+ * evicted from the set derived from the address
+ */
+ CFA_BLD_MPC_EV_EVICT_CLEAN_AND_CLEAN_FAST_EVICT_LINES,
+ /*
+ * All Cache lines in the set identified by the address and
+ * belonging to the table scope are evicted.
+ */
+ CFA_BLD_MPC_EV_EVICT_TABLE_SCOPE,
+ CFA_BLD_MPC_EV_MODE_MAX,
+};
+
+/**
+ * MPC CFA Command completion status
+ */
+enum cfa_bld_mpc_cmpl_status {
+ /* Command success */
+ CFA_BLD_MPC_OK,
+ /* Unsupported CFA opcode */
+ CFA_BLD_MPC_UNSPRT_ERR,
+ /* CFA command format error */
+ CFA_BLD_MPC_FMT_ERR,
+ /* SVIF-Table Scope error */
+ CFA_BLD_MPC_SCOPE_ERR,
+ /* Address error: Only used if EM command or TABLE_TYPE=EM */
+ CFA_BLD_MPC_ADDR_ERR,
+ /* Cache operation error */
+ CFA_BLD_MPC_CACHE_ERR,
+ /* EM_SEARCH or EM_DELETE did not find a matching EM entry */
+ CFA_BLD_MPC_EM_MISS,
+ /* EM_INSERT found a matching EM entry and REPLACE=0 in the command */
+ CFA_BLD_MPC_EM_DUPLICATE,
+ /* EM_EVENT_COLLECTION_FAIL no events to return */
+ CFA_BLD_MPC_EM_EVENT_COLLECTION_FAIL,
+ /*
+ * EM_INSERT required a dynamic bucket to be added to the chain
+ * to successfully insert the EM entry, but the entry provided
+ * for use as dynamic bucket was invalid. (bucket_idx == 0)
+ */
+ CFA_BLD_MPC_EM_ABORT,
+};
+
+/**
+ * Field IDS for READ_CMD: This command reads 1-4 consecutive 32B words
+ * from the specified address within a table scope.
+ */
+enum cfa_bld_mpc_read_cmd_fields {
+ CFA_BLD_MPC_READ_CMD_OPAQUE_FLD = 0,
+ /* This value selects the table type to be acted upon. */
+ CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD = 1,
+ /* Table scope to access. */
+ CFA_BLD_MPC_READ_CMD_TABLE_SCOPE_FLD = 2,
+ /*
+ * Number of 32B units in access. If value is outside the range [1, 4],
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ CFA_BLD_MPC_READ_CMD_DATA_SIZE_FLD = 3,
+ /*
+ * Test field for CFA MPC builder validation, added to introduce
+ * a hold in the field mapping array
+ */
+ CFA_BLD_MPC_READ_CMD_RANDOM_TEST_FLD = 4,
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ CFA_BLD_MPC_READ_CMD_CACHE_OPTION_FLD = 5,
+ /*
+ * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE):
+ */
+ CFA_BLD_MPC_READ_CMD_TABLE_INDEX_FLD = 6,
+ /*
+ * The 64-bit host address to which to write the DMA data returned in
+ * the completion. The data will be written to the same function as the
+ * one that owns the SQ this command is read from. DATA_SIZE determines
+ * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0,
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ CFA_BLD_MPC_READ_CMD_HOST_ADDRESS_FLD = 7,
+ CFA_BLD_MPC_READ_CMD_MAX_FLD = 8,
+};
+
+/**
+ * Field IDS for WRITE_CMD: This command writes 1-4 consecutive 32B
+ * words to the specified address within a table scope.
+ */
+enum cfa_bld_mpc_write_cmd_fields {
+ CFA_BLD_MPC_WRITE_CMD_OPAQUE_FLD = 0,
+ /* This value selects the table type to be acted upon. */
+ CFA_BLD_MPC_WRITE_CMD_TABLE_TYPE_FLD = 1,
+ /*
+ * Sets the OPTION field on the cache interface to use write-through for
+ * EM entry writes while processing EM_INSERT commands. For all other
+ * cases (inluding EM_INSERT bucket writes), the OPTION field is set by
+ * the CACHE_OPTION and CACHE_OPTION2 fields.
+ */
+ CFA_BLD_MPC_WRITE_CMD_WRITE_THROUGH_FLD = 2,
+ /* Table scope to access. */
+ CFA_BLD_MPC_WRITE_CMD_TABLE_SCOPE_FLD = 3,
+ /*
+ * Number of 32B units in access. If value is outside the range [1, 4],
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ CFA_BLD_MPC_WRITE_CMD_DATA_SIZE_FLD = 4,
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ CFA_BLD_MPC_WRITE_CMD_CACHE_OPTION_FLD = 5,
+ /*
+ * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE):
+ */
+ CFA_BLD_MPC_WRITE_CMD_TABLE_INDEX_FLD = 6,
+ CFA_BLD_MPC_WRITE_CMD_MAX_FLD = 7,
+};
+
+/**
+ * Field IDS for READ_CLR_CMD: This command performs a read-modify-write
+ * to the specified 32B address using a 16b mask that specifies up to 16
+ * 16b words to clear before writing the data back. It returns the 32B
+ * data word read from cache (not the value written after the clear
+ * operation).
+ */
+enum cfa_bld_mpc_read_clr_cmd_fields {
+ CFA_BLD_MPC_READ_CLR_CMD_OPAQUE_FLD = 0,
+ /* This value selects the table type to be acted upon. */
+ CFA_BLD_MPC_READ_CLR_CMD_TABLE_TYPE_FLD = 1,
+ /* Table scope to access. */
+ CFA_BLD_MPC_READ_CLR_CMD_TABLE_SCOPE_FLD = 2,
+ /*
+ * This field is no longer used. The READ_CLR command always reads (and
+ * does a mask-clear) on a single cache line. This field was added for
+ * SR2 A0 to avoid an ADDR_ERR when TABLE_INDEX=0 and TABLE_TYPE=EM (see
+ * CUMULUS-17872). That issue was fixed in SR2 B0.
+ */
+ CFA_BLD_MPC_READ_CLR_CMD_DATA_SIZE_FLD = 3,
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ CFA_BLD_MPC_READ_CLR_CMD_CACHE_OPTION_FLD = 4,
+ /*
+ * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE):
+ */
+ CFA_BLD_MPC_READ_CLR_CMD_TABLE_INDEX_FLD = 5,
+ /*
+ * The 64-bit host address to which to write the DMA data returned in
+ * the completion. The data will be written to the same function as the
+ * one that owns the SQ this command is read from. DATA_SIZE determines
+ * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0,
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ CFA_BLD_MPC_READ_CLR_CMD_HOST_ADDRESS_FLD = 6,
+ /*
+ * Specifies bits in 32B data word to clear. For x=0..15, when
+ * clear_mask[x]=1, data[x*16+15:x*16] is set to 0.
+ */
+ CFA_BLD_MPC_READ_CLR_CMD_CLEAR_MASK_FLD = 7,
+ CFA_BLD_MPC_READ_CLR_CMD_MAX_FLD = 8,
+};
+
+/**
+ * Field IDS for INVALIDATE_CMD: This command forces an explicit evict
+ * of 1-4 consecutive cache lines such that the next time the structure
+ * is used it will be re-read from its backing store location.
+ */
+enum cfa_bld_mpc_invalidate_cmd_fields {
+ CFA_BLD_MPC_INVALIDATE_CMD_OPAQUE_FLD = 0,
+ /* This value selects the table type to be acted upon. */
+ CFA_BLD_MPC_INVALIDATE_CMD_TABLE_TYPE_FLD = 1,
+ /* Table scope to access. */
+ CFA_BLD_MPC_INVALIDATE_CMD_TABLE_SCOPE_FLD = 2,
+ /*
+ * This value identifies the number of cache lines to invalidate. A
+ * FMT_ERR is reported if the value is not in the range of [1, 4].
+ */
+ CFA_BLD_MPC_INVALIDATE_CMD_DATA_SIZE_FLD = 3,
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ CFA_BLD_MPC_INVALIDATE_CMD_CACHE_OPTION_FLD = 4,
+ /*
+ * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE):
+ */
+ CFA_BLD_MPC_INVALIDATE_CMD_TABLE_INDEX_FLD = 5,
+ CFA_BLD_MPC_INVALIDATE_CMD_MAX_FLD = 6,
+};
+
+/**
+ * Field IDS for EM_SEARCH_CMD: This command supplies an exact match
+ * entry of 1-4 32B words to search for in the exact match table. CFA
+ * first computes the hash value of the key in the entry, and determines
+ * the static bucket address to search from the hash and the
+ * (EM_BUCKETS, EM_SIZE) for TABLE_SCOPE. It then searches that static
+ * bucket chain for an entry with a matching key (the LREC in the
+ * command entry is ignored). If a matching entry is found, CFA reports
+ * OK status in the completion. Otherwise, assuming no errors abort the
+ * search before it completes, it reports EM_MISS status.
+ */
+enum cfa_bld_mpc_em_search_cmd_fields {
+ CFA_BLD_MPC_EM_SEARCH_CMD_OPAQUE_FLD = 0,
+ /* Table scope to access. */
+ CFA_BLD_MPC_EM_SEARCH_CMD_TABLE_SCOPE_FLD = 1,
+ /*
+ * Number of 32B units in access. If value is outside the range [1, 4],
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ CFA_BLD_MPC_EM_SEARCH_CMD_DATA_SIZE_FLD = 2,
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ CFA_BLD_MPC_EM_SEARCH_CMD_CACHE_OPTION_FLD = 3,
+ CFA_BLD_MPC_EM_SEARCH_CMD_MAX_FLD = 4,
+};
+
+/**
+ * Field IDS for EM_INSERT_CMD: This command supplies an exact match
+ * entry of 1-4 32B words to insert in the exact match table. CFA first
+ * computes the hash value of the key in the entry, and determines the
+ * static bucket address to search from the hash and the (EM_BUCKETS,
+ * EM_SIZE) for TABLE_SCOPE. It then writes the 1-4 32B words of the
+ * exact match entry starting at the TABLE_INDEX location in the
+ * command. When the entry write completes, it searches the static
+ * bucket chain for an existing entry with a key matching the key in the
+ * insert entry (the LREC does not need to match). If a matching entry
+ * is found: * If REPLACE=0, the CFA aborts the insert and returns
+ * EM_DUPLICATE status. * If REPLACE=1, the CFA overwrites the matching
+ * entry with the new entry. REPLACED_ENTRY=1 in the completion in this
+ * case to signal that an entry was replaced. The location of the entry
+ * is provided in the completion. If no match is found, CFA adds the new
+ * entry to the lowest unused entry in the tail bucket. If the current
+ * tail bucket is full, this requires adding a new bucket to the tail.
+ * Then entry is then inserted at entry number 0. TABLE_INDEX2 provides
+ * the address of the new tail bucket, if needed. If set to 0, the
+ * insert is aborted and returns EM_ABORT status instead of adding a new
+ * bucket to the tail. CHAIN_UPD in the completion indicates whether a
+ * new bucket was added (1) or not (0). For locked scopes, if the read
+ * of the static bucket gives a locked scope miss error, indicating that
+ * the address is not in the cache, the static bucket is assumed empty.
+ * In this case, TAI creates a new bucket, setting entry 0 to the new
+ * entry fields and initializing all other fields to 0. It writes this
+ * new bucket to the static bucket address, which installs it in the
+ * cache.
+ */
+enum cfa_bld_mpc_em_insert_cmd_fields {
+ CFA_BLD_MPC_EM_INSERT_CMD_OPAQUE_FLD = 0,
+ /*
+ * Sets the OPTION field on the cache interface to use write-through for
+ * EM entry writes while processing EM_INSERT commands. For all other
+ * cases (inluding EM_INSERT bucket writes), the OPTION field is set by
+ * the CACHE_OPTION and CACHE_OPTION2 fields.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMD_WRITE_THROUGH_FLD = 1,
+ /* Table scope to access. */
+ CFA_BLD_MPC_EM_INSERT_CMD_TABLE_SCOPE_FLD = 2,
+ /*
+ * Number of 32B units in access. If value is outside the range [1, 4],
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMD_DATA_SIZE_FLD = 3,
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMD_CACHE_OPTION_FLD = 4,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. Starting
+ * address to write exact match entry being inserted.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMD_TABLE_INDEX_FLD = 5,
+ /*
+ * Determines setting of OPTION field for all cache write requests for
+ * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support
+ * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMD_CACHE_OPTION2_FLD = 6,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. Only used
+ * when no duplicate entry is found and the tail bucket in the chain
+ * searched has no unused entries. In this case, TABLE_INDEX2 provides
+ * the index to the 32B dynamic bucket to add to the tail of the chain
+ * (it is the new tail bucket). In this case, the CFA first writes
+ * TABLE_INDEX2 with a new bucket: * Entry 0 of the bucket sets the
+ * HASH_MSBS computed from the hash and ENTRY_PTR to TABLE_INDEX. *
+ * Entries 1-5 of the bucket set HASH_MSBS and ENTRY_PTR to 0. * CHAIN=0
+ * and CHAIN_PTR is set to CHAIN_PTR from to original tail bucket to
+ * maintain the background chaining. CFA then sets CHAIN=1 and
+ * CHAIN_PTR=TABLE_INDEX2 in the original tail bucket to link the new
+ * bucket to the chain. CHAIN_UPD=1 in the completion to signal that the
+ * new bucket at TABLE_INDEX2 was added to the tail of the chain.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMD_TABLE_INDEX2_FLD = 7,
+ /*
+ * Only used if an entry is found whose key matches the exact match
+ * entry key in the command: * REPLACE=0: The insert is aborted and
+ * EM_DUPLICATE status is returned, signaling that the insert failed.
+ * The index of the matching entry that blocked the insertion is
+ * returned in the completion. * REPLACE=1: The matching entry is
+ * replaced with that from the command (ENTRY_PTR in the bucket is
+ * overwritten with TABLE_INDEX from the command). HASH_MSBS for the
+ * entry number never changes in this case since it had to match the new
+ * entry key HASH_MSBS to match. When an entry is replaced,
+ * REPLACED_ENTRY=1 in the completion and the index of the matching
+ * entry is returned in the completion so that software can de-allocate
+ * the entry.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMD_REPLACE_FLD = 8,
+ CFA_BLD_MPC_EM_INSERT_CMD_MAX_FLD = 9,
+};
+
+/**
+ * Field IDS for EM_DELETE_CMD: This command searches for an exact match
+ * entry index in the static bucket chain and deletes it if found.
+ * TABLE_INDEX give the entry index to delete and TABLE_INDEX2 gives the
+ * static bucket index. If a matching entry is found: * If the matching
+ * entry is the last valid entry in the tail bucket, its entry fields
+ * (HASH_MSBS and ENTRY_PTR) are set to 0 to delete the entry. * If the
+ * matching entry is not the last valid entry in the tail bucket, the
+ * entry fields from that last entry are moved to the matching entry,
+ * and the fields of that last entry are set to 0. * If any of the
+ * previous processing results in the tail bucket not having any valid
+ * entries, the tail bucket is the static bucket, the scope is a locked
+ * scope, and CHAIN_PTR=0, hardware evicts the static bucket from the
+ * cache and the completion signals this case with CHAIN_UPD=1. * If any
+ * of the previous processing results in the tail bucket not having any
+ * valid entries, and the tail bucket is not the static bucket, the tail
+ * bucket is removed from the chain. In this case, the penultimate
+ * bucket in the chain becomes the tail bucket. It has CHAIN set to 0 to
+ * unlink the tail bucket, and CHAIN_PTR set to that from the original
+ * tail bucket to preserve background chaining. The completion signals
+ * this case with CHAIN_UPD=1 and returns the index to the bucket
+ * removed so that software can de-allocate it. CFA returns OK status if
+ * the entry was successfully deleted. Otherwise, it returns EM_MISS
+ * status assuming there were no errors that caused processing to be
+ * aborted.
+ */
+enum cfa_bld_mpc_em_delete_cmd_fields {
+ CFA_BLD_MPC_EM_DELETE_CMD_OPAQUE_FLD = 0,
+ /*
+ * Sets the OPTION field on the cache interface to use write-through for
+ * EM entry writes while processing EM_INSERT commands. For all other
+ * cases (inluding EM_INSERT bucket writes), the OPTION field is set by
+ * the CACHE_OPTION and CACHE_OPTION2 fields.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMD_WRITE_THROUGH_FLD = 1,
+ /* Table scope to access. */
+ CFA_BLD_MPC_EM_DELETE_CMD_TABLE_SCOPE_FLD = 2,
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMD_CACHE_OPTION_FLD = 3,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. Entry index
+ * to delete.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMD_TABLE_INDEX_FLD = 4,
+ /*
+ * Determines setting of OPTION field for all cache write requests for
+ * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support
+ * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMD_CACHE_OPTION2_FLD = 5,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. Static
+ * bucket address for bucket chain.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMD_TABLE_INDEX2_FLD = 6,
+ CFA_BLD_MPC_EM_DELETE_CMD_MAX_FLD = 7,
+};
+
+/**
+ * Field IDS for EM_CHAIN_CMD: This command updates CHAIN_PTR in the
+ * tail bucket of a static bucket chain, supplying both the static
+ * bucket and the new CHAIN_PTR value. TABLE_INDEX is the new CHAIN_PTR
+ * value and TABLE_INDEX2[23:0] is the static bucket. This command
+ * provides software a means to update background chaining coherently
+ * with other bucket updates. The value of CHAIN is unaffected (stays at
+ * 0). For locked scopes, if the static bucket is the tail bucket, it is
+ * empty (all of its ENTRY_PTR values are 0), and TABLE_INDEX=0 (the
+ * CHAIN_PTR is being set to 0), instead of updating the static bucket
+ * it is evicted from the cache. In this case, CHAIN_UPD=1 in the
+ * completion.
+ */
+enum cfa_bld_mpc_em_chain_cmd_fields {
+ CFA_BLD_MPC_EM_CHAIN_CMD_OPAQUE_FLD = 0,
+ /*
+ * Sets the OPTION field on the cache interface to use write-through for
+ * EM entry writes while processing EM_INSERT commands. For all other
+ * cases (inluding EM_INSERT bucket writes), the OPTION field is set by
+ * the CACHE_OPTION and CACHE_OPTION2 fields.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMD_WRITE_THROUGH_FLD = 1,
+ /* Table scope to access. */
+ CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_SCOPE_FLD = 2,
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMD_CACHE_OPTION_FLD = 3,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. New
+ * CHAIN_PTR to write to tail bucket.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_INDEX_FLD = 4,
+ /*
+ * Determines setting of OPTION field for all cache write requests for
+ * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support
+ * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMD_CACHE_OPTION2_FLD = 5,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. Static
+ * bucket address for bucket chain.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_INDEX2_FLD = 6,
+ CFA_BLD_MPC_EM_CHAIN_CMD_MAX_FLD = 7,
+};
+
+/**
+ * Field IDS for READ_CMP: When no errors, teturns 1-4 consecutive 32B
+ * words from the TABLE_INDEX within the TABLE_SCOPE specified in the
+ * command, writing them to HOST_ADDRESS from the command.
+ */
+enum cfa_bld_mpc_read_cmp_fields {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ CFA_BLD_MPC_READ_CMP_TYPE_FLD = 0,
+ /* The command processing status. */
+ CFA_BLD_MPC_READ_CMP_STATUS_FLD = 1,
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ CFA_BLD_MPC_READ_CMP_MP_CLIENT_FLD = 2,
+ /* OPCODE from the command. */
+ CFA_BLD_MPC_READ_CMP_OPCODE_FLD = 3,
+ /*
+ * The length of the DMA that accompanies the completion in units of
+ * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates
+ * that there is no DMA that accompanies the completion.
+ */
+ CFA_BLD_MPC_READ_CMP_DMA_LENGTH_FLD = 4,
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ CFA_BLD_MPC_READ_CMP_OPAQUE_FLD = 5,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_READ_CMP_V_FLD = 6,
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ CFA_BLD_MPC_READ_CMP_HASH_MSB_FLD = 7,
+ /* TABLE_TYPE from the command. */
+ CFA_BLD_MPC_READ_CMP_TABLE_TYPE_FLD = 8,
+ /* TABLE_SCOPE from the command. */
+ CFA_BLD_MPC_READ_CMP_TABLE_SCOPE_FLD = 9,
+ /* TABLE_INDEX from the command. */
+ CFA_BLD_MPC_READ_CMP_TABLE_INDEX_FLD = 10,
+ CFA_BLD_MPC_READ_CMP_MAX_FLD = 11,
+};
+
+/**
+ * Field IDS for WRITE_CMP: Returns status of the write of 1-4
+ * consecutive 32B words starting at TABLE_INDEX in the table specified
+ * by (TABLE_TYPE, TABLE_SCOPE).
+ */
+enum cfa_bld_mpc_write_cmp_fields {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ CFA_BLD_MPC_WRITE_CMP_TYPE_FLD = 0,
+ /* The command processing status. */
+ CFA_BLD_MPC_WRITE_CMP_STATUS_FLD = 1,
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ CFA_BLD_MPC_WRITE_CMP_MP_CLIENT_FLD = 2,
+ /* OPCODE from the command. */
+ CFA_BLD_MPC_WRITE_CMP_OPCODE_FLD = 3,
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ CFA_BLD_MPC_WRITE_CMP_OPAQUE_FLD = 4,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_WRITE_CMP_V_FLD = 5,
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ CFA_BLD_MPC_WRITE_CMP_HASH_MSB_FLD = 6,
+ /* TABLE_TYPE from the command. */
+ CFA_BLD_MPC_WRITE_CMP_TABLE_TYPE_FLD = 7,
+ /* TABLE_SCOPE from the command. */
+ CFA_BLD_MPC_WRITE_CMP_TABLE_SCOPE_FLD = 8,
+ /* TABLE_INDEX from the command. */
+ CFA_BLD_MPC_WRITE_CMP_TABLE_INDEX_FLD = 9,
+ CFA_BLD_MPC_WRITE_CMP_MAX_FLD = 10,
+};
+
+/**
+ * Field IDS for READ_CLR_CMP: When no errors, returns 1 32B word from
+ * TABLE_INDEX in the table specified by (TABLE_TYPE, TABLE_SCOPE). The
+ * data returned is the value prior to the clear.
+ */
+enum cfa_bld_mpc_read_clr_cmp_fields {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ CFA_BLD_MPC_READ_CLR_CMP_TYPE_FLD = 0,
+ /* The command processing status. */
+ CFA_BLD_MPC_READ_CLR_CMP_STATUS_FLD = 1,
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ CFA_BLD_MPC_READ_CLR_CMP_MP_CLIENT_FLD = 2,
+ /* OPCODE from the command. */
+ CFA_BLD_MPC_READ_CLR_CMP_OPCODE_FLD = 3,
+ /*
+ * The length of the DMA that accompanies the completion in units of
+ * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates
+ * that there is no DMA that accompanies the completion.
+ */
+ CFA_BLD_MPC_READ_CLR_CMP_DMA_LENGTH_FLD = 4,
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ CFA_BLD_MPC_READ_CLR_CMP_OPAQUE_FLD = 5,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_READ_CLR_CMP_V_FLD = 6,
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ CFA_BLD_MPC_READ_CLR_CMP_HASH_MSB_FLD = 7,
+ /* TABLE_TYPE from the command. */
+ CFA_BLD_MPC_READ_CLR_CMP_TABLE_TYPE_FLD = 8,
+ /* TABLE_SCOPE from the command. */
+ CFA_BLD_MPC_READ_CLR_CMP_TABLE_SCOPE_FLD = 9,
+ /* TABLE_INDEX from the command. */
+ CFA_BLD_MPC_READ_CLR_CMP_TABLE_INDEX_FLD = 10,
+ CFA_BLD_MPC_READ_CLR_CMP_MAX_FLD = 11,
+};
+
+/**
+ * Field IDS for INVALIDATE_CMP: Returns status for INVALIDATE commands.
+ */
+enum cfa_bld_mpc_invalidate_cmp_fields {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ CFA_BLD_MPC_INVALIDATE_CMP_TYPE_FLD = 0,
+ /* The command processing status. */
+ CFA_BLD_MPC_INVALIDATE_CMP_STATUS_FLD = 1,
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ CFA_BLD_MPC_INVALIDATE_CMP_MP_CLIENT_FLD = 2,
+ /* OPCODE from the command. */
+ CFA_BLD_MPC_INVALIDATE_CMP_OPCODE_FLD = 3,
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ CFA_BLD_MPC_INVALIDATE_CMP_OPAQUE_FLD = 4,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_INVALIDATE_CMP_V_FLD = 5,
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ CFA_BLD_MPC_INVALIDATE_CMP_HASH_MSB_FLD = 6,
+ /* TABLE_TYPE from the command. */
+ CFA_BLD_MPC_INVALIDATE_CMP_TABLE_TYPE_FLD = 7,
+ /* TABLE_SCOPE from the command. */
+ CFA_BLD_MPC_INVALIDATE_CMP_TABLE_SCOPE_FLD = 8,
+ /* TABLE_INDEX from the command. */
+ CFA_BLD_MPC_INVALIDATE_CMP_TABLE_INDEX_FLD = 9,
+ CFA_BLD_MPC_INVALIDATE_CMP_MAX_FLD = 10,
+};
+
+/**
+ * Field IDS for EM_SEARCH_CMP: For OK status, returns the index of the
+ * matching entry found for the EM key supplied in the command. Returns
+ * EM_MISS status if no match was found.
+ */
+enum cfa_bld_mpc_em_search_cmp_fields {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ CFA_BLD_MPC_EM_SEARCH_CMP_TYPE_FLD = 0,
+ /* The command processing status. */
+ CFA_BLD_MPC_EM_SEARCH_CMP_STATUS_FLD = 1,
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ CFA_BLD_MPC_EM_SEARCH_CMP_MP_CLIENT_FLD = 2,
+ /* OPCODE from the command. */
+ CFA_BLD_MPC_EM_SEARCH_CMP_OPCODE_FLD = 3,
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ CFA_BLD_MPC_EM_SEARCH_CMP_OPAQUE_FLD = 4,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_EM_SEARCH_CMP_V1_FLD = 5,
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ CFA_BLD_MPC_EM_SEARCH_CMP_HASH_MSB_FLD = 6,
+ /* TABLE_SCOPE from the command. */
+ CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_SCOPE_FLD = 7,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. For OK
+ * status, gives ENTRY_PTR[25:0] of the matching entry found. Otherwise,
+ * set to 0.
+ */
+ CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_INDEX_FLD = 8,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. If the hash
+ * is computed (no errors during initial processing of the command),
+ * TABLE_INDEX2[23:0] is the static bucket address determined from the
+ * hash of the exact match entry key in the command and the (EM_SIZE,
+ * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24
+ * in this case are set to 0. For any other status, it is always 0.
+ */
+ CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_INDEX2_FLD = 9,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_EM_SEARCH_CMP_V2_FLD = 10,
+ /*
+ * BKT_NUM is the bucket number in chain of the tail bucket after
+ * finishing processing the command, except when the command stops
+ * processing before the tail bucket. NUM_ENTRIES is the number of valid
+ * entries in the BKT_NUM bucket. The following describes the cases
+ * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after
+ * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR,
+ * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. *
+ * For CACHE_ERR completion status, BKT_NUM will be set to the bucket
+ * number that was last read without error. If ERR=1 in the response to
+ * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The
+ * static bucket is number 0, BKT_NUM increments for each new bucket in
+ * the chain, and saturates at 255. Therefore, if the value is 255,
+ * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES
+ * will still be the correct value as described above for the bucket.
+ */
+ CFA_BLD_MPC_EM_SEARCH_CMP_BKT_NUM_FLD = 11,
+ /* See BKT_NUM description. */
+ CFA_BLD_MPC_EM_SEARCH_CMP_NUM_ENTRIES_FLD = 12,
+ CFA_BLD_MPC_EM_SEARCH_CMP_MAX_FLD = 13,
+};
+
+/**
+ * Field IDS for EM_INSERT_CMP: OK status indicates that the exact match
+ * entry from the command was successfully inserted. EM_DUPLICATE status
+ * indicates that the insert was aborted because an entry with the same
+ * exact match key was found and REPLACE=0 in the command. EM_ABORT
+ * status indicates that no duplicate was found, the tail bucket in the
+ * chain was full, and TABLE_INDEX2=0. No changes are made to the
+ * database in this case. TABLE_INDEX is the starting address at which
+ * to insert the exact match entry (from the command). TABLE_INDEX2 is
+ * the address at which to insert a new bucket at the tail of the static
+ * bucket chain if needed (from the command). CHAIN_UPD=1 if a new
+ * bucket was added at this address. TABLE_INDEX3 is the static bucket
+ * address for the chain, determined from hashing the exact match entry.
+ * Software needs this address and TABLE_INDEX in order to delete the
+ * entry using an EM_DELETE command. TABLE_INDEX4 is the index of an
+ * entry found that had a matching exact match key to the command entry
+ * key. If no matching entry was found, it is set to 0. There are two
+ * cases when there is a matching entry, depending on REPLACE from the
+ * command: * REPLACE=0: EM_DUPLICATE status is reported and the insert
+ * is aborted. Software can use the static bucket address
+ * (TABLE_INDEX3[23:0]) and the matching entry (TABLE_INDEX4) in an
+ * EM_DELETE command if it wishes to explicity delete the matching
+ * entry. * REPLACE=1: REPLACED_ENTRY=1 to signal that the entry at
+ * TABLE_INDEX4 was replaced by the insert entry. REPLACED_ENTRY will
+ * only be 1 if reporting OK status in this case. Software can de-
+ * allocate the entry at TABLE_INDEX4.
+ */
+enum cfa_bld_mpc_em_insert_cmp_fields {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_TYPE_FLD = 0,
+ /* The command processing status. */
+ CFA_BLD_MPC_EM_INSERT_CMP_STATUS_FLD = 1,
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_MP_CLIENT_FLD = 2,
+ /* OPCODE from the command. */
+ CFA_BLD_MPC_EM_INSERT_CMP_OPCODE_FLD = 3,
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_OPAQUE_FLD = 4,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_V1_FLD = 5,
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_HASH_MSB_FLD = 6,
+ /* TABLE_SCOPE from the command. */
+ CFA_BLD_MPC_EM_INSERT_CMP_TABLE_SCOPE_FLD = 7,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX
+ * from the command, which is the starting address at which to insert
+ * the exact match entry.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX_FLD = 8,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2
+ * from the command, which is the index for the new tail bucket to add
+ * if needed (CHAIN_UPD=1 if it was used).
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX2_FLD = 9,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. If the hash
+ * is computed (no errors during initial processing of the command),
+ * TABLE_INDEX2[23:0] is the static bucket address determined from the
+ * hash of the exact match entry key in the command and the (EM_SIZE,
+ * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24
+ * in this case are set to 0. For any other status, it is always 0.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX3_FLD = 10,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_V2_FLD = 11,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. ENTRY_PTR of
+ * matching entry found. Set to 0 if no matching entry found. If
+ * REPLACED_ENTRY=1, that indicates a matching entry was found and
+ * REPLACE=1 in the command. In this case, the matching entry was
+ * replaced by the new entry in the command and this index can therefore
+ * by de-allocated.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX4_FLD = 12,
+ /*
+ * BKT_NUM is the bucket number in chain of the tail bucket after
+ * finishing processing the command, except when the command stops
+ * processing before the tail bucket. NUM_ENTRIES is the number of valid
+ * entries in the BKT_NUM bucket. The following describes the cases
+ * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after
+ * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR,
+ * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. *
+ * For CACHE_ERR completion status, BKT_NUM will be set to the bucket
+ * number that was last read without error. If ERR=1 in the response to
+ * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The
+ * static bucket is number 0, BKT_NUM increments for each new bucket in
+ * the chain, and saturates at 255. Therefore, if the value is 255,
+ * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES
+ * will still be the correct value as described above for the bucket.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_BKT_NUM_FLD = 13,
+ /* See BKT_NUM description. */
+ CFA_BLD_MPC_EM_INSERT_CMP_NUM_ENTRIES_FLD = 14,
+ /*
+ * Specifies if the chain was updated while processing the command: Set
+ * to 1 when a new bucket is added to the tail of the static bucket
+ * chain at TABLE_INDEX2. This occurs if and only if the insert requires
+ * adding a new entry and the tail bucket is full. If set to 0,
+ * TABLE_INDEX2 was not used and is therefore still free.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_CHAIN_UPD_FLD = 15,
+ /*
+ * Set to 1 if a matching entry was found and REPLACE=1 in command. In
+ * the case, the entry starting at TABLE_INDEX4 was replaced and can
+ * therefore be de-allocated. Otherwise, this flag is set to 0.
+ */
+ CFA_BLD_MPC_EM_INSERT_CMP_REPLACED_ENTRY_FLD = 16,
+ CFA_BLD_MPC_EM_INSERT_CMP_MAX_FLD = 17,
+};
+
+/**
+ * Field IDS for EM_DELETE_CMP: OK status indicates that an ENTRY_PTR
+ * matching TABLE_INDEX was found in the static bucket chain specified
+ * and was therefore deleted. EM_MISS status indicates that no match was
+ * found. TABLE_INDEX is from the command. It is the index of the entry
+ * to delete. TABLE_INDEX2 is from the command. It is the static bucket
+ * address. TABLE_INDEX3 is the index of the tail bucket of the static
+ * bucket chain prior to processing the command. TABLE_INDEX4 is the
+ * index of the tail bucket of the static bucket chain after processing
+ * the command. If CHAIN_UPD=1 and TABLE_INDEX4==TABLE_INDEX2, the
+ * static bucket was the tail bucket, it became empty after the delete,
+ * the scope is a locked scope, and CHAIN_PTR was 0. In this case, the
+ * static bucket has been evicted from the cache. Otherwise, if
+ * CHAIN_UPD=1, the original tail bucket given by TABLE_INDEX3 was
+ * removed from the chain because it went empty. It can therefore be de-
+ * allocated.
+ */
+enum cfa_bld_mpc_em_delete_cmp_fields {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_TYPE_FLD = 0,
+ /* The command processing status. */
+ CFA_BLD_MPC_EM_DELETE_CMP_STATUS_FLD = 1,
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_MP_CLIENT_FLD = 2,
+ /* OPCODE from the command. */
+ CFA_BLD_MPC_EM_DELETE_CMP_OPCODE_FLD = 3,
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_OPAQUE_FLD = 4,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_V1_FLD = 5,
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_HASH_MSB_FLD = 6,
+ /* TABLE_SCOPE from the command. */
+ CFA_BLD_MPC_EM_DELETE_CMP_TABLE_SCOPE_FLD = 7,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX
+ * from the command, which is the index of the entry to delete.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX_FLD = 8,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2
+ * from the command.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX2_FLD = 9,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. For OK or
+ * EM_MISS status, the index of the tail bucket of the chain prior to
+ * processing the command. If CHAIN_UPD=1, the bucket was removed and
+ * this index can be de-allocated. For other status values, it is set to
+ * 0.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX3_FLD = 10,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_V2_FLD = 11,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. For OK or
+ * EM_MISS status, the index of the tail bucket of the chain prior to
+ * after the command. If CHAIN_UPD=0 (always for EM_MISS status), it is
+ * always equal to TABLE_INDEX3 as the chain was not updated. For other
+ * status values, it is set to 0.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX4_FLD = 12,
+ /*
+ * BKT_NUM is the bucket number in chain of the tail bucket after
+ * finishing processing the command, except when the command stops
+ * processing before the tail bucket. NUM_ENTRIES is the number of valid
+ * entries in the BKT_NUM bucket. The following describes the cases
+ * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after
+ * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR,
+ * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. *
+ * For CACHE_ERR completion status, BKT_NUM will be set to the bucket
+ * number that was last read without error. If ERR=1 in the response to
+ * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The
+ * static bucket is number 0, BKT_NUM increments for each new bucket in
+ * the chain, and saturates at 255. Therefore, if the value is 255,
+ * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES
+ * will still be the correct value as described above for the bucket.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_BKT_NUM_FLD = 13,
+ /* See BKT_NUM description. */
+ CFA_BLD_MPC_EM_DELETE_CMP_NUM_ENTRIES_FLD = 14,
+ /*
+ * Specifies if the chain was updated while processing the command: Set
+ * to 1 when a bucket is removed from the static bucket chain. This
+ * occurs if after the delete, the tail bucket is a dynamic bucket and
+ * no longer has any valid entries. In this case, software should de-
+ * allocate the dynamic bucket at TABLE_INDEX3. It is also set to 1 when
+ * the static bucket is evicted, which only occurs for locked scopes.
+ * See the EM_DELETE command description for details.
+ */
+ CFA_BLD_MPC_EM_DELETE_CMP_CHAIN_UPD_FLD = 15,
+ CFA_BLD_MPC_EM_DELETE_CMP_MAX_FLD = 16,
+};
+
+/**
+ * Field IDS for EM_CHAIN_CMP: OK status indicates that the CHAIN_PTR of
+ * the tail bucket was successfully updated. TABLE_INDEX is from the
+ * command. It is the value of the new CHAIN_PTR. TABLE_INDEX2 is from
+ * the command. TABLE_INDEX3 is the index of the tail bucket of the
+ * static bucket chain.
+ */
+enum cfa_bld_mpc_em_chain_cmp_fields {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMP_TYPE_FLD = 0,
+ /* The command processing status. */
+ CFA_BLD_MPC_EM_CHAIN_CMP_STATUS_FLD = 1,
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMP_MP_CLIENT_FLD = 2,
+ /* OPCODE from the command. */
+ CFA_BLD_MPC_EM_CHAIN_CMP_OPCODE_FLD = 3,
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMP_OPAQUE_FLD = 4,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMP_V1_FLD = 5,
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMP_HASH_MSB_FLD = 6,
+ /* TABLE_SCOPE from the command. */
+ CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_SCOPE_FLD = 7,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX
+ * from the command, which is the new CHAIN_PTR for the tail bucket of
+ * the static bucket chain.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX_FLD = 8,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2
+ * from the command.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX2_FLD = 9,
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. For OK
+ * status, the index of the tail bucket of the chain. Otherwise, set to
+ * 0.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX3_FLD = 10,
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMP_V2_FLD = 11,
+ /*
+ * BKT_NUM is the bucket number in chain of the tail bucket after
+ * finishing processing the command, except when the command stops
+ * processing before the tail bucket. NUM_ENTRIES is the number of valid
+ * entries in the BKT_NUM bucket. The following describes the cases
+ * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after
+ * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR,
+ * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. *
+ * For CACHE_ERR completion status, BKT_NUM will be set to the bucket
+ * number that was last read without error. If ERR=1 in the response to
+ * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The
+ * static bucket is number 0, BKT_NUM increments for each new bucket in
+ * the chain, and saturates at 255. Therefore, if the value is 255,
+ * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES
+ * will still be the correct value as described above for the bucket.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMP_BKT_NUM_FLD = 12,
+ /* See BKT_NUM description. */
+ CFA_BLD_MPC_EM_CHAIN_CMP_NUM_ENTRIES_FLD = 13,
+ /*
+ * Set to 1 when the scope is a locked scope, the tail bucket is the
+ * static bucket, the bucket is empty (all of its ENTRY_PTR values are
+ * 0), and TABLE_INDEX=0 in the command. In this case, the static bucket
+ * is evicted. For all other cases, it is set to 0.
+ */
+ CFA_BLD_MPC_EM_CHAIN_CMP_CHAIN_UPD_FLD = 14,
+ CFA_BLD_MPC_EM_CHAIN_CMP_MAX_FLD = 15,
+};
+
+#endif /* _CFA_BLD_MPC_FIELD_IDS_H_ */
new file mode 100644
@@ -0,0 +1,598 @@
+/****************************************************************************
+ * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * @file cfa_bld_mpcops.h
+ *
+ * @brief CFA Builder MPC ops interface for host applications
+ */
+
+#ifndef _CFA_BLD_MPCOPS_H_
+#define _CFA_BLD_MPCOPS_H_
+
+#include <stdio.h>
+#include "cfa_types.h"
+
+/**
+ * CFA HW data object definition
+ */
+struct cfa_mpc_data_obj {
+ /** [in] MPC field identifier */
+ uint16_t field_id;
+ /** [in] Value of the HW field */
+ uint64_t val;
+};
+
+struct cfa_bld_mpcops;
+
+/**
+ * @addtogroup CFA_BLD CFA Builder Library
+ * \ingroup CFA_V3
+ * @{
+ */
+
+/**
+ * CFA MPC ops interface
+ */
+struct cfa_bld_mpcinfo {
+ /** [out] CFA MPC Builder operations function pointer table */
+ const struct cfa_bld_mpcops *mpcops;
+};
+
+/**
+ * @name CFA_BLD_MPC CFA Builder Host MPC OPS API
+ * CFA builder host specific API used by host CFA application to bind
+ * to different CFA devices and access device by using MPC OPS.
+ */
+
+/**@{*/
+/** CFA builder MPC bind API
+ *
+ * This API retrieves the CFA global MPC configuration.
+ *
+ * @param[in] hw_ver
+ * hardware version of the CFA
+ *
+ * @param[out] mpc_info
+ * CFA MPC interface
+ *
+ * @return
+ * 0 for SUCCESS, negative value for FAILURE
+ */
+int cfa_bld_mpc_bind(enum cfa_ver hw_ver, struct cfa_bld_mpcinfo *mpc_info);
+
+/** CFA device specific function hooks for CFA MPC command composition
+ * and response parsing
+ *
+ * The following device hooks can be defined; unless noted otherwise, they are
+ * optional and can be filled with a null pointer. The pupose of these hooks
+ * to support CFA device operations for different device variants.
+ */
+struct cfa_bld_mpcops {
+ /** Build MPC Cache read command
+ *
+ * This API composes the MPC cache read command given the list
+ * of read parameters specified as an array of cfa_mpc_data_obj objects.
+ *
+ * @param[in] cmd
+ * MPC command buffer to compose the cache read command into.
+ *
+ * @param[in,out] cmd_buff_len
+ * Pointer to command buffer length variable. The caller sets this
+ * to the size of the 'cmd' buffer in byes. The api updates this to
+ * the actual size of the composed command. If the buffer length
+ * passed is not large enough to hold the composed command, an error
+ * is returned by the api.
+ *
+ * @param[in] fields
+ * Array of CFA data objects indexed by CFA_BLD_MPC_READ_CMD_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_READ_CMD_MAX_FLD. If the caller intends to set a
+ * specific field in the MPC command, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself (See example
+ * below). Otherwise set the field_id to INVALID_U16. If the caller
+ * sets the field_id for a field that is not valid for the device
+ * an error is returned.
+ *
+ * To set the table type to EM:
+ * fields[CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD].field_id =
+ * CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD;
+ * fields[CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD].val =
+ * CFA_HW_TABLE_LOOKUP;
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_build_cache_read)(uint8_t *cmd,
+ uint32_t *cmd_buff_len,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Build MPC Cache Write command
+ *
+ * This API composes the MPC cache write command given the list
+ * of write parameters specified as an array of cfa_mpc_data_obj
+ * objects.
+ *
+ * @param[in] cmd
+ * MPC command buffer to compose the cache write command into.
+ *
+ * @param[in,out] cmd_buff_len
+ * Pointer to command buffer length variable. The caller sets this
+ * to the size of the 'cmd' buffer in byes. The api updates this to
+ * the actual size of the composed command. If the buffer length
+ * passed is not large enough to hold the composed command, an error
+ * is returned by the api.
+ *
+ * @param[in] data
+ * Pointer to the data to be written. Note that this data is just
+ * copied at the right offset into the command buffer. The actual MPC
+ * write happens when the command is issued over the MPC interface.
+ *
+ * @param[in] fields
+ * Array of CFA data objects indexed by CFA_BLD_MPC_WRITE_CMD_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_WRITE_CMD_MAX_FLD. If the caller intends to set a
+ * specific field in the MPC command, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise
+ * set the field_id to INVALID_U16. If the caller sets the field_id for
+ * a field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_build_cache_write)(uint8_t *cmd,
+ uint32_t *cmd_buff_len,
+ const uint8_t *data,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Build MPC Cache Invalidate (Evict) command
+ *
+ * This API composes the MPC cache evict command given the list
+ * of evict parameters specified as an array of cfa_mpc_data_obj
+ * objects.
+ *
+ * @param[in] cmd
+ * MPC command buffer to compose the cache evict command into.
+ *
+ * @param[in,out] cmd_buff_len
+ * Pointer to command buffer length variable. The caller sets this
+ * to the size of the 'cmd' buffer in byes. The api updates this to
+ * the actual size of the composed command. If the buffer length
+ * passed is not large enough to hold the composed command, an error
+ * is returned by the api.
+ *
+ * @param[in] fields
+ * Array of cfa_mpc_data_obj indexed by
+ * CFA_BLD_MPC_INVALIDATE_CMD_XXX_FLD enum values. The size of this
+ * array shall be CFA_BLD_MPC_INVALIDATE_CMD_MAX_FLD. If the caller
+ * intends to set a specific field in the MPC command, the caller
+ * should set the field_id in cfa_mpc_data_obj to the array index
+ * itself. Otherwise set the field_id to INVALID_U16. If the caller
+ * sets the field_id for a field that is not valid for the device an
+ * error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_build_cache_evict)(uint8_t *cmd,
+ uint32_t *cmd_buff_len,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Build MPC Cache read and clear command
+ *
+ * This API composes the MPC cache read-n-clear command given the list
+ * of read parameters specified as an array of cfa_mpc_data_obj objects.
+ *
+ * @param[in] cmd
+ * MPC command buffer to compose the cache read-n-clear command into.
+ *
+ * @param[in,out] cmd_buff_len
+ * Pointer to command buffer length variable. The caller sets this
+ * to the size of the 'cmd' buffer in byes. The api updates this to
+ * the actual size of the composed command. If the buffer length
+ * passed is not large enough to hold the composed command, an error
+ * is returned by the api.
+ *
+ * @param[in] fields
+ * Array of cfa_mpc_data_obj indexed by
+ * CFA_BLD_MPC_READ_CLR_CMD_XXX_FLD enum values. The size of this
+ * array shall be CFA_BLD_MPC_READ_CLR_CMD_MAX_FLD. If the caller
+ * intends to set a specific field in the MPC command, the caller
+ * should set the field_id in cfa_mpc_data_obj to the array index
+ * itself. Otherwise set the field_id to INVALID_U16. If the caller
+ * sets the field_id for a field that is not valid for the device
+ * an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_build_cache_read_clr)(uint8_t *cmd,
+ uint32_t *cmd_buff_len,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Build MPC EM search command
+ *
+ * This API composes the MPC EM search command given the list
+ * of EM search parameters specified as an array of cfa_mpc_data_obj
+ * objects
+ *
+ * @param[in] cmd
+ * MPC command buffer to compose the EM search command into.
+ *
+ * @param[in,out] cmd_buff_len
+ * Pointer to command buffer length variable. The caller sets this
+ * to the size of the 'cmd' buffer in byes. The api updates this to
+ * the actual size of the composed command. If the buffer length
+ * passed is not large enough to hold the composed command, an error
+ * is returned by the api.
+ *
+ * @param[in] em_entry
+ * Pointer to the em_entry to be searched.
+ *
+ * @param[in] fields
+ * Array of cfa_mpc_data_obj indexed by
+ * CFA_BLD_MPC_EM_SEARCH_CMD_XXX_FLD enum values. The size of this
+ * array shall be CFA_BLD_MPC_EM_SEARCH_CMD_MAX_FLD. If the caller
+ * intends to set a specific field in the MPC command, the caller
+ * should set the field_id in cfa_mpc_data_obj to the array index
+ * itself. Otherwise set the field_id to INVALID_U16. If the caller
+ * sets the field_id for a field that is not valid for the device an
+ * error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_build_em_search)(uint8_t *cmd, uint32_t *cmd_buff_len,
+ uint8_t *em_entry,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Build MPC EM insert command
+ *
+ * This API composes the MPC EM insert command given the list
+ * of EM insert parameters specified as an array of cfa_mpc_data_obj objects
+ *
+ * @param[in] cmd
+ * MPC command buffer to compose the EM insert command into.
+ *
+ * @param[in,out] cmd_buff_len
+ * Pointer to command buffer length variable. The caller sets this
+ * to the size of the 'cmd' buffer in bytes. The api updates this to
+ * the actual size of the composed command. If the buffer length
+ * passed is not large enough to hold the composed command, an error
+ * is returned by the api.
+ *
+ * @param[in] em_entry
+ * Pointer to the em_entry to be inserted.
+ *
+ * @param[in] fields
+ * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_INSERT_CMD_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_EM_INSERT_CMD_MAX_FLD. If the caller intends to set a
+ * specific field in the MPC command, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set
+ * the field_id to INVALID_U16. If the caller sets the field_id for a
+ * field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_build_em_insert)(uint8_t *cmd, uint32_t *cmd_buff_len,
+ const uint8_t *em_entry,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Build MPC EM delete command
+ *
+ * This API composes the MPC EM delete command given the list
+ * of EM delete parameters specified as an array of cfa_mpc_data_obj objects
+ *
+ * @param[in] cmd
+ * MPC command buffer to compose the EM delete command into.
+ *
+ * @param[in,out] cmd_buff_len
+ * Pointer to command buffer length variable. The caller sets this
+ * to the size of the 'cmd' buffer in byes. The api updates this to
+ * the actual size of the composed command. If the buffer length
+ * passed is not large enough to hold the composed command, an error
+ * is returned by the api.
+ *
+ * @param[in] fields
+ * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_DELETE_CMD_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_EM_DELETE_CMD_MAX_FLD. If the caller intends to set a
+ * specific field in the MPC command, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set
+ * the field_id to INVALID_U16. If the caller sets the field_id for a
+ * field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_build_em_delete)(uint8_t *cmd, uint32_t *cmd_buff_len,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Build MPC EM chain command
+ *
+ * This API composes the MPC EM chain command given the list
+ * of EM chain parameters specified as an array of cfa_mpc_data_obj objects
+ *
+ * @param[in] cmd
+ * MPC command buffer to compose the EM chain command into.
+ *
+ * @param[in,out] cmd_buff_len
+ * Pointer to command buffer length variable. The caller sets this
+ * to the size of the 'cmd' buffer in byes. The api updates this to
+ * the actual size of the composed command. If the buffer length
+ * passed is not large enough to hold the composed command, an error
+ * is returned by the api.
+ *
+ * @param[in] fields
+ * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_CHAIN_CMD_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_EM_CHAIN_CMD_MAX_FLD. If the caller intends to set a
+ * specific field in the MPC command, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set
+ * the field_id to INVALID_U16. If the caller sets the field_id for a
+ * field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_build_em_chain)(uint8_t *cmd, uint32_t *cmd_buff_len,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Parse MPC Cache read response
+ *
+ * This API parses the MPC cache read response message and returns
+ * the read parameters as an array of cfa_mpc_data_obj objects.
+ *
+ * @param[in] resp
+ * MPC response buffer containing the cache read response.
+ *
+ * @param[in] resp_buff_len
+ * Response buffer length in bytes
+ *
+ * @param[in] rd_data
+ * Buffer to copy the MPC read data into
+ *
+ * @param[in] rd_data_len
+ * Size of the rd_data buffer in bytes
+ *
+ * @param[out] fields
+ * Array of CFA data objects indexed by CFA_BLD_MPC_READ_CMP_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_READ_CMP_MAX_FLD. If the caller intends to retrieve a
+ * specific field in the MPC response, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set
+ * the field_id to INVALID_U16. If the caller sets the field_id for a
+ * field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_parse_cache_read)(uint8_t *resp,
+ uint32_t resp_buff_len,
+ uint8_t *rd_data,
+ uint32_t rd_data_len,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Parse MPC Cache Write response
+ *
+ * This API parses the MPC cache write response message and returns
+ * the write response fields as an array of cfa_mpc_data_obj objects.
+ *
+ * @param[in] resp
+ * MPC response buffer containing the cache write response.
+ *
+ * @param[in] resp_buff_len
+ * Response buffer length in bytes
+ *
+ * @param[out] fields
+ * Array of CFA data objects indexed by CFA_BLD_MPC_WRITE_CMP_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_WRITE_CMP_MAX_FLD. If the caller intends to retrieve a
+ * specific field in the MPC response, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set
+ * the field_id to INVALID_U16. If the caller sets the field_id for a
+ * field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_parse_cache_write)(uint8_t *resp,
+ uint32_t resp_buff_len,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Parse MPC Cache Invalidate (Evict) response
+ *
+ * This API parses the MPC cache evict response message and returns
+ * the evict response fields as an array of cfa_mpc_data_obj objects.
+ *
+ * @param[in] resp
+ * MPC response buffer containing the cache evict response.
+ *
+ * @param[in] resp_buff_len
+ * Response buffer length in bytes
+ *
+ * @param[out] fields
+ * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_INVALIDATE_CMP_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_INVALIDATE_CMP_MAX_FLD. If the caller intends to get a
+ * specific field in the MPC response, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set
+ * the field_id to INVALID_U16. If the caller sets the field_id for a
+ * field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_parse_cache_evict)(uint8_t *resp,
+ uint32_t resp_buff_len,
+ struct cfa_mpc_data_obj *fields);
+
+ /* clang-format off */
+ /** Parse MPC Cache read and clear response
+ *
+ * This API parses the MPC cache read-n-clear response message and
+ * returns the read response fields as an array of cfa_mpc_data_obj objects.
+ *
+ * @param[in] resp
+ * MPC response buffer containing the cache read-n-clear response.
+ *
+ * @param[in] resp_buff_len
+ * Response buffer length in bytes
+ *
+ * @param[in] rd_data
+ * Buffer to copy the MPC read data into
+ *
+ * @param[in] rd_data_len
+ * Size of the rd_data buffer in bytes
+ *
+ * @param[out] fields
+ * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_READ_CLR_CMP_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_READ_CLR_CMP_MAX_FLD. If the caller intends to get a
+ * specific field in the MPC response, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set
+ * the field_id to INVALID_U16. If the caller sets the field_id for a
+ * field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_parse_cache_read_clr)(uint8_t *resp,
+ uint32_t resp_buff_len, uint8_t *rd_data,
+ uint32_t rd_data_len, struct cfa_mpc_data_obj *fields);
+
+ /* clang-format on */
+ /** Parse MPC EM search response
+ *
+ * This API parses the MPC EM search response message and returns
+ * the EM search response fields as an array of cfa_mpc_data_obj objects
+ *
+ * @param[in] resp
+ * MPC response buffer containing the EM search response.
+ *
+ * @param[in] resp_buff_len
+ * Response buffer length in bytes
+ *
+ * @param[out] fields
+ * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_SEARCH_CMP_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_EM_SEARCH_CMP_MAX_FLD. If the caller intends to get a
+ * specific field in the MPC response, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set
+ * the field_id to INVALID_U16. If the caller sets the field_id for a
+ * field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_parse_em_search)(uint8_t *resp,
+ uint32_t resp_buff_len,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Parse MPC EM insert response
+ *
+ * This API parses the MPC EM insert response message and returns
+ * the EM insert response fields as an array of cfa_mpc_data_obj objects
+ *
+ * @param[in] resp
+ * MPC response buffer containing the EM insert response.
+ *
+ * @param[in] resp_buff_len
+ * Response buffer length in bytes
+ *
+ * @param[out] fields
+ * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_INSERT_CMP_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_EM_INSERT_CMP_MAX_FLD. If the caller intends to get a
+ * specific field in the MPC response, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set
+ * the field_id to INVALID_U16. If the caller sets the field_id for a
+ * field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_parse_em_insert)(uint8_t *resp,
+ uint32_t resp_buff_len,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Parse MPC EM delete response
+ *
+ * This API parses the MPC EM delete response message and returns
+ * the EM delete response fields as an array of cfa_mpc_data_obj objects
+ *
+ * @param[in] resp
+ * MPC response buffer containing the EM delete response.
+ *
+ * @param[in] resp_buff_len
+ * Response buffer length in bytes
+ *
+ * @param[out] fields
+ * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_DELETE_CMP_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_EM_DELETE_CMP_MAX_FLD. If the caller intends to get a
+ * specific field in the MPC response, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set
+ * the field_id to INVALID_U16. If the caller sets the field_id for a
+ * field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_parse_em_delete)(uint8_t *resp,
+ uint32_t resp_buff_len,
+ struct cfa_mpc_data_obj *fields);
+
+ /** Parse MPC EM chain response
+ *
+ * This API parses the MPC EM chain response message and returns
+ * the EM chain response fields as an array of cfa_mpc_data_obj objects
+ *
+ * @param[in] resp
+ * MPC response buffer containing the EM chain response.
+ *
+ * @param[in] resp_buff_len
+ * Response buffer length in bytes
+ *
+ * @param[out] fields
+ * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_CHAIN_CMP_XXX_FLD
+ * enum values. The size of this array shall be
+ * CFA_BLD_MPC_EM_CHAIN_CMP_MAX_FLD. If the caller intends to get a
+ * specific field in the MPC response, the caller should set the
+ * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set
+ * the field_id to INVALID_U16. If the caller sets the field_id for a
+ * field that is not valid for the device an error is returned.
+ *
+ * @return
+ * 0 for SUCCESS, negative errno for FAILURE
+ *
+ */
+ int (*cfa_bld_mpc_parse_em_chain)(uint8_t *resp, uint32_t resp_buff_len,
+ struct cfa_mpc_data_obj *fields);
+};
+
+/**@}*/
+
+/**@}*/
+#endif /* _CFA_BLD_DEVOPS_H_ */
new file mode 100644
@@ -0,0 +1,543 @@
+/****************************************************************************
+ * Copyright(c) 2021 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * @file cfa_bld_p70.h
+ *
+ * @brief CFA Phase 7.0 specific Builder public definitions
+ */
+
+#ifndef _CFA_BLD_P70_H_
+#define _CFA_BLD_P70_H_
+
+#include "sys_util.h"
+#include "cfa_bld_defs.h"
+#include "cfa_bld_p70_field_ids.h"
+
+/**
+ * Maximum key array size
+ */
+#define CFA_P70_KEY_MAX_FIELD_CNT \
+ MAX((uint16_t)CFA_P70_EM_KEY_LAYOUT_MAX_FLD, \
+ (uint16_t)CFA_P70_WC_TCAM_FKB_MAX_FLD)
+#define CFA_P70_ACT_MAX_TEMPLATE_SZ sizeof(struct cfa_bld_p70_action_template)
+
+#define CFA_P70_PROF_MAX_KEYS 4
+enum cfa_p70_mac_sel_mode {
+ CFA_P70_MAC_SEL_MODE_FIRST = 0,
+ CFA_P70_MAC_SEL_MODE_LOWEST = 1
+};
+
+struct cfa_p70_prof_key_cfg {
+ uint8_t mac_sel[CFA_P70_PROF_MAX_KEYS];
+#define CFA_PROF_P70_MAC_SEL_DMAC0 (1 << 0)
+#define CFA_PROF_P70_MAC_SEL_T_MAC0 (1 << 1)
+#define CFA_PROF_P70_MAC_SEL_OUTERMOST_MAC0 (1 << 2)
+#define CFA_PROF_P70_MAC_SEL_DMAC1 (1 << 3)
+#define CFA_PROF_P70_MAC_SEL_T_MAC1 (1 << 4)
+#define CFA_PROF_P70_MAC_OUTERMOST_MAC1 (1 << 5)
+ uint8_t vlan_sel[CFA_P70_PROF_MAX_KEYS];
+#define CFA_PROF_P70_VLAN_SEL_INNER_HDR 0
+#define CFA_PROF_P70_VLAN_SEL_TUNNEL_HDR 1
+#define CFA_PROF_P70_VLAN_SEL_OUTERMOST_HDR 2
+ uint8_t pass_cnt;
+ enum cfa_p70_mac_sel_mode mode;
+};
+
+/*
+ * Field id remap function pointer. Passed by cfa-v3 caller
+ * to builder apis if the caller requires the apis to remap
+ * the field ids before using them to update key/action layout
+ * objects. An example of one such api is action_compute_ptr()
+ * which updates the offsets for the modify/encap/source/stat
+ * records in the action record. If the caller is remapping
+ * the field ids (to save memory in fw builds for example), then
+ * this remap api is required to be passed. If passed as NULL,
+ * the field ids are not remapped and used directly to index
+ * into the layout.
+ *
+ * @param Input field id
+ *
+ * @return Remapped field id on success, UNIT16_MAX on failure.
+ */
+typedef uint16_t(cfa_fld_remap)(uint16_t);
+
+/**
+ * CFA P70 action layout definition
+ */
+
+enum action_type_p70 {
+ /** Select this type to build an Full Action Record Object
+ */
+ CFA_P70_ACT_OBJ_TYPE_FULL_ACT,
+ /** Select this type to build an Compact Action Record Object
+ */
+ CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT,
+ /** Select this type to build an MCG Action Record Object
+ */
+ CFA_P70_ACT_OBJ_TYPE_MCG_ACT,
+ /** Select this type to build Standalone Modify Action Record Object */
+ CFA_P70_ACT_OBJ_TYPE_MODIFY,
+ /** Select this type to build Standalone Stat Action Record Object */
+ CFA_P70_ACT_OBJ_TYPE_STAT,
+ /** Select this type to build Standalone Source Action Record Object */
+ CFA_P70_ACT_OBJ_TYPE_SRC_PROP,
+ /** Select this type to build Standalone Encap Action Record Object */
+ CFA_P70_ACT_OBJ_TYPE_ENCAP,
+};
+
+enum stat_op_p70 {
+ /** Set to statistic to ingress to CFA
+ */
+ CFA_P70_STAT_OP_INGRESS = 0,
+ /** Set to statistic to egress from CFA
+ */
+ CFA_P70_STAT_OP_EGRESS = 1,
+};
+
+enum stat_type_p70 {
+ /** Set to statistic to Foward packet count(64b)/Foward byte
+ * count(64b)
+ */
+ CFA_P70_STAT_COUNTER_SIZE_16B = 0,
+ /** Set to statistic to Forward packet count(64b)/Forward byte
+ * count(64b)/ TCP Flags(16b)/Timestamp(32b)
+ */
+ CFA_P70_STAT_COUNTER_SIZE_24B = 1,
+ /** Set to statistic to Forward packet count(64b)/Forward byte
+ * count(64b)/Meter(drop or red) packet count(64b)/Meter(drop
+ * or red) byte count(64b)
+ */
+ CFA_P70_STAT_COUNTER_SIZE_32B = 2,
+ /** Set to statistic to Forward packet count(64b)/Forward byte
+ * count(64b)/Meter(drop or red) packet count(38b)/Meter(drop
+ * or red) byte count(42b)/TCP Flags(16b)/Timestamp(32b)
+ */
+ CFA_P70_STAT_COUNTER_SIZE_32B_ALL = 3,
+};
+
+enum encap_vtag_p70 {
+ CFA_P70_ACT_ENCAP_VTAGS_PUSH_0 = 0,
+ CFA_P70_ACT_ENCAP_VTAGS_PUSH_1,
+ CFA_P70_ACT_ENCAP_VTAGS_PUSH_2
+};
+
+enum encap_l3_p70 {
+ /** Set to disable any L3 encapsulation
+ * processing, default
+ */
+ CFA_P70_ACT_ENCAP_L3_NONE = 0,
+ /** Set to enable L3 IPv4 encapsulation
+ */
+ CFA_P70_ACT_ENCAP_L3_IPV4 = 4,
+ /** Set to enable L3 IPv6 encapsulation
+ */
+ CFA_P70_ACT_ENCAP_L3_IPV6 = 5,
+ /** Set to enable L3 MPLS 8847 encapsulation
+ */
+ CFA_P70_ACT_ENCAP_L3_MPLS_8847 = 6,
+ /** Set to enable L3 MPLS 8848 encapsulation
+ */
+ CFA_P70_ACT_ENCAP_L3_MPLS_8848 = 7
+};
+
+enum encap_tunnel_p70 {
+ /** Set to disable Tunnel header encapsulation
+ * processing, default
+ */
+ CFA_P70_ACT_ENCAP_TNL_NONE = 0,
+ /** Set to enable Tunnel Generic Full header
+ * encapsulation
+ */
+ CFA_P70_ACT_ENCAP_TNL_GENERIC_FULL,
+ /** Set to enable VXLAN header encapsulation
+ */
+ CFA_P70_ACT_ENCAP_TNL_VXLAN,
+ /** Set to enable NGE (VXLAN2) header encapsulation
+ */
+ CFA_P70_ACT_ENCAP_TNL_NGE,
+ /** Set to enable NVGRE header encapsulation
+ */
+ CFA_P70_ACT_ENCAP_TNL_NVGRE,
+ /** Set to enable GRE header encapsulation
+ */
+ CFA_P70_ACT_ENCAP_TNL_GRE,
+ /** Set to enable Generic header after Tunnel
+ * L4 encapsulation
+ */
+ CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TL4,
+ /** Set to enable Generic header after Tunnel
+ * encapsulation
+ */
+ CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TNL
+};
+
+enum source_rec_type_p70 {
+ /** Set to Source MAC Address
+ */
+ CFA_P70_SOURCE_MAC = 0,
+ /** Set to Source MAC and IPv4 Addresses
+ */
+ CFA_P70_SOURCE_MAC_IPV4 = 1,
+ /** Set to Source MAC and IPv6 Addresses
+ */
+ CFA_P70_SOURCE_MAC_IPV6 = 2,
+};
+
+/**
+ * From CFA phase 7.0 onwards, setting the modify vector bit
+ * 'ACT_MODIFY_TUNNEL_MODIFY' requires corresponding data fields to be
+ * set. This enum defines the parameters that determine the
+ * layout of this associated data fields. This structure
+ * is not used for versions older than CFA Phase 7.0 and setting
+ * the 'ACT_MODIFY_TUNNEL_MODIFY' bit will just delete the internal tunnel
+ */
+enum tunnel_modify_mode_p70 {
+ /* No change to tunnel protocol */
+ CFA_P70_ACT_MOD_TNL_NO_PROTO_CHANGE = 0,
+ /* 8-bit tunnel protocol change */
+ CFA_P70_ACT_MOD_TNL_8B_PROTO_CHANGE = 1,
+ /* 16-bit tunnel protocol change */
+ CFA_P70_ACT_MOD_TNL_16B_PROTO_CHANGE = 2,
+ CFA_P70_ACT_MOD_TNL_MAX
+};
+
+/**
+ * Action object template structure
+ *
+ * Template structure presents data fields that are necessary to know
+ * at the beginning of Action Builder (AB) processing. Like before the
+ * AB compilation. One such example could be a template that is
+ * flexible in size (Encap Record) and the presence of these fields
+ * allows for determining the template size as well as where the
+ * fields are located in the record.
+ *
+ * The template may also present fields that are not made visible to
+ * the caller by way of the action fields.
+ *
+ * Template fields also allow for additional checking on user visible
+ * fields. One such example could be the encap pointer behavior on a
+ * CFA_P70_ACT_OBJ_TYPE_ACT or CFA_P70_ACT_OBJ_TYPE_ACT_SRAM.
+ */
+struct cfa_bld_p70_action_template {
+ /** Action Object type
+ *
+ * Controls the type of the Action Template
+ */
+ enum action_type_p70 obj_type;
+
+ /** Action Control
+ *
+ * Controls the internals of the Action Template
+ *
+ * act is valid when:
+ * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT)
+ * ||
+ * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT))
+ *
+ * Specifies whether each action is to be in-line or not.
+ */
+ struct {
+ /** Set to true to enable statistics
+ */
+ uint8_t stat_enable;
+ /** Set to true to enable statistics to be inlined
+ */
+ uint8_t stat_inline;
+ /** Set to true to enable statistics 1
+ */
+ uint8_t stat1_enable;
+ /** Set to true to enable statistics 1 to be inlined
+ */
+ uint8_t stat1_inline;
+ /** Set to true to enable encapsulation
+ */
+ uint8_t encap_enable;
+ /** Set to true to enable encapsulation to be inlined
+ */
+ uint8_t encap_inline;
+ /** Set to true to align the encap record to cache
+ * line
+ */
+ uint8_t encap_align;
+ /** Set to true to source
+ */
+ uint8_t source_enable;
+ /** Set to true to enable source to be inlined
+ */
+ uint8_t source_inline;
+ /** Set to true to enable modfication
+ */
+ uint8_t mod_enable;
+ /** Set to true to enable modify to be inlined
+ */
+ uint8_t mod_inline;
+ /** Set to true to enable subsequent MCGs
+ */
+ uint8_t mcg_subseq_enable;
+ } act;
+
+ /** Statistic Control
+ * Controls the type of statistic the template is describing
+ *
+ * stat is valid when:
+ * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) ||
+ * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT)) &&
+ * act.stat_enable || act.stat_inline)
+ */
+ struct {
+ enum stat_op_p70 op;
+ enum stat_type_p70 type;
+ } stat;
+
+ /** Encap Control
+ * Controls the type of encapsulation the template is
+ * describing
+ *
+ * encap is valid when:
+ * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) ||
+ * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT) &&
+ * act.encap_enable || act.encap_inline)
+ */
+ struct {
+ /** Set to true to enable L2 capability in the
+ * template
+ */
+ uint8_t l2_enable;
+ /** vtag controls the Encap Vector - VTAG Encoding, 4 bits
+ *
+ * <ul>
+ * <li> CFA_P70_ACT_ENCAP_VTAGS_PUSH_0, default, no VLAN
+ * Tags applied
+ * <li> CFA_P70_ACT_ENCAP_VTAGS_PUSH_1, adds capability to
+ * set 1 VLAN Tag. Action Template compile adds
+ * the following field to the action object
+ * TF_ER_VLAN1
+ * <li> CFA_P70_ACT_ENCAP_VTAGS_PUSH_2, adds capability to
+ * set 2 VLAN Tags. Action Template compile adds
+ * the following fields to the action object
+ * TF_ER_VLAN1 and TF_ER_VLAN2
+ * </ul>
+ */
+ enum encap_vtag_p70 vtag;
+
+ /*
+ * The remaining fields are NOT supported when
+ * direction is RX and ((obj_type ==
+ * CFA_P70_ACT_OBJ_TYPE_ACT) && act.encap_enable).
+ * cfa_bld_p70_action_compile_layout will perform the
+ * checking and skip remaining fields.
+ */
+ /** L3 Encap controls the Encap Vector - L3 Encoding,
+ * 3 bits. Defines the type of L3 Encapsulation the
+ * template is describing.
+ * <ul>
+ * <li> CFA_P70_ACT_ENCAP_L3_NONE, default, no L3
+ * Encapsulation processing.
+ * <li> CFA_P70_ACT_ENCAP_L3_IPV4, enables L3 IPv4
+ * Encapsulation.
+ * <li> CFA_P70_ACT_ENCAP_L3_IPV6, enables L3 IPv6
+ * Encapsulation.
+ * <li> CFA_P70_ACT_ENCAP_L3_MPLS_8847, enables L3 MPLS
+ * 8847 Encapsulation.
+ * <li> CFA_P70_ACT_ENCAP_L3_MPLS_8848, enables L3 MPLS
+ * 8848 Encapsulation.
+ * </ul>
+ */
+ enum encap_l3_p70 l3;
+
+#define CFA_P70_ACT_ENCAP_MAX_MPLS_LABELS 8
+ /** 1-8 labels, valid when
+ * (l3 == CFA_P70_ACT_ENCAP_L3_MPLS_8847) ||
+ * (l3 == CFA_P70_ACT_ENCAP_L3_MPLS_8848)
+ *
+ * MAX number of MPLS Labels 8.
+ */
+ uint8_t l3_num_mpls_labels;
+
+ /** Set to true to enable L4 capability in the
+ * template.
+ *
+ * true adds TF_EN_UDP_SRC_PORT and
+ * TF_EN_UDP_DST_PORT to the template.
+ */
+ uint8_t l4_enable;
+
+ /** Tunnel Encap controls the Encap Vector - Tunnel
+ * Encap, 3 bits. Defines the type of Tunnel
+ * encapsulation the template is describing
+ * <ul>
+ * <li> CFA_P70_ACT_ENCAP_TNL_NONE, default, no Tunnel
+ * Encapsulation processing.
+ * <li> CFA_P70_ACT_ENCAP_TNL_GENERIC_FULL
+ * <li> CFA_P70_ACT_ENCAP_TNL_VXLAN. NOTE: Expects
+ * l4_enable set to true;
+ * <li> CFA_P70_ACT_ENCAP_TNL_NGE. NOTE: Expects l4_enable
+ * set to true;
+ * <li> CFA_P70_ACT_ENCAP_TNL_NVGRE. NOTE: only valid if
+ * l4_enable set to false.
+ * <li> CFA_P70_ACT_ENCAP_TNL_GRE.NOTE: only valid if
+ * l4_enable set to false.
+ * <li> CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TL4
+ * <li> CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TNL
+ * </ul>
+ */
+ enum encap_tunnel_p70 tnl;
+
+#define CFA_P70_ACT_ENCAP_MAX_TUNNEL_GENERIC_SIZE 128
+ /** Number of bytes of generic tunnel header,
+ * valid when
+ * (tnl == CFA_P70_ACT_ENCAP_TNL_GENERIC_FULL) ||
+ * (tnl == CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TL4) ||
+ * (tnl == CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TNL)
+ */
+ uint8_t tnl_generic_size;
+
+#define CFA_P70_ACT_ENCAP_MAX_OPLEN 15
+ /** Number of 32b words of nge options,
+ * valid when
+ * (tnl == CFA_P70_ACT_ENCAP_TNL_NGE)
+ */
+ uint8_t tnl_nge_op_len;
+
+ /** Set to true to enable MAC/VLAN/IP/TNL overrides in the
+ * template
+ */
+ bool encap_override;
+ /* Currently not planned */
+ /* Custom Header */
+ /* uint8_t custom_enable; */
+ } encap;
+
+ /** Modify Control
+ *
+ * Controls the type of the Modify Action the template is
+ * describing
+ *
+ * modify is valid when:
+ * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) ||
+ * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT) &&
+ * act.modify_enable || act.modify_inline)
+ */
+/** Set to enable Modify of Metadata
+ */
+#define CFA_P70_ACT_MODIFY_META 0x1
+/** Set to enable Delete of Outer VLAN
+ */
+#define CFA_P70_ACT_MODIFY_DEL_OVLAN 0x2
+/** Set to enable Delete of Inner VLAN
+ */
+#define CFA_P70_ACT_MODIFY_DEL_IVLAN 0x4
+/** Set to enable Replace or Add of Outer VLAN
+ */
+#define CFA_P70_ACT_MODIFY_REPL_ADD_OVLAN 0x8
+/** Set to enable Replace or Add of Inner VLAN
+ */
+#define CFA_P70_ACT_MODIFY_REPL_ADD_IVLAN 0x10
+/** Set to enable Modify of TTL
+ */
+#define CFA_P70_ACT_MODIFY_TTL_UPDATE 0x20
+/** Set to enable delete of INT Tunnel
+ */
+#define CFA_P70_ACT_MODIFY_DEL_INT_TNL 0x40
+/** For phase 7.0 this bit can be used to modify the
+ * tunnel protocol in addition to deleting internal
+ * or outer tunnel
+ */
+#define CFA_P70_ACT_MODIFY_TUNNEL_MODIFY CFA_P70_ACT_MODIFY_DEL_INT_TNL
+/** Set to enable Modify of Field
+ */
+#define CFA_P70_ACT_MODIFY_FIELD 0x80
+/** Set to enable Modify of Destination MAC
+ */
+#define CFA_P70_ACT_MODIFY_DMAC 0x100
+/** Set to enable Modify of Source MAC
+ */
+#define CFA_P70_ACT_MODIFY_SMAC 0x200
+/** Set to enable Modify of Source IPv6 Address
+ */
+#define CFA_P70_ACT_MODIFY_SRC_IPV6 0x400
+/** Set to enable Modify of Destination IPv6 Address
+ */
+#define CFA_P70_ACT_MODIFY_DST_IPV6 0x800
+/** Set to enable Modify of Source IPv4 Address
+ */
+#define CFA_P70_ACT_MODIFY_SRC_IPV4 0x1000
+/** Set to enable Modify of Destination IPv4 Address
+ */
+#define CFA_P70_ACT_MODIFY_DST_IPV4 0x2000
+/** Set to enable Modify of L4 Source Port
+ */
+#define CFA_P70_ACT_MODIFY_SRC_PORT 0x4000
+/** Set to enable Modify of L4 Destination Port
+ */
+#define CFA_P70_ACT_MODIFY_DST_PORT 0x8000
+ uint16_t modify;
+
+/** Set to enable Modify of KID
+ */
+#define CFA_P70_ACT_MODIFY_FIELD_KID 0x1
+ uint16_t field_modify;
+
+ /* Valid for phase 7.0 or higher */
+ enum tunnel_modify_mode_p70 tnl_mod_mode;
+
+ /** Source Control
+ *
+ * Controls the type of the Source Action the template is
+ * describing
+ *
+ * source is valid when:
+ * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) ||
+ * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT) &&
+ * act.source_enable || act.source_inline)
+ */
+ enum source_rec_type_p70 source;
+};
+
+/**
+ * Key template consists of key fields that can be enabled/disabled
+ * individually.
+ */
+struct cfa_p70_key_template {
+ /** [in] Identify if the key template is for TCAM. If false, the
+ * key template is for EM. This field is mandantory for device that
+ * only support fix key formats.
+ */
+ bool is_wc_tcam_key;
+ /** [in] Identify if the key template will be use for IPv6 Keys.
+ *
+ * Note: This is important for SR2 as the field length for the Flow Id
+ * is dependent on the L3 flow type. For SR2 for IPv4 Keys, the Flow
+ * Id field is 16 bits, for all other types (IPv6, ARP, PTP, EAP, RoCE,
+ * FCoE, UPAR), the Flow Id field length is 20 bits.
+ */
+ bool is_ipv6_key;
+ /** [in] key field enable field array, set 1 to the correspeonding
+ * field enable to make a field valid
+ */
+ uint8_t field_en[CFA_P70_KEY_MAX_FIELD_CNT];
+};
+
+/**
+ * Action template consists of action fields that can be enabled/disabled
+ * individually.
+ */
+struct cfa_p70_action_template {
+ /** [in] CFA version for the action template */
+ enum cfa_ver hw_ver;
+ /** [in] action field enable field array, set 1 to the correspeonding
+ * field enable to make a field valid
+ */
+ uint8_t data[CFA_P70_ACT_MAX_TEMPLATE_SZ];
+};
+
+#define CFA_PROF_L2CTXT_TCAM_MAX_FIELD_CNT CFA_P70_PROF_L2_CTXT_TCAM_MAX_FLD
+#define CFA_PROF_L2CTXT_REMAP_MAX_FIELD_CNT CFA_P70_PROF_L2_CTXT_RMP_DR_MAX_FLD
+#define CFA_PROF_MAX_KEY_CFG_SZ sizeof(struct cfa_p70_prof_key_cfg)
+
+#endif /* _CFA_BLD_P70_H_ */
new file mode 100644
@@ -0,0 +1,1542 @@
+/****************************************************************************
+ * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * Name: cfa_bld_p70_field_ids.h
+ *
+ * Description: Enumerations definitions for CFA phase 7.0 HW table fields
+ * Action record fields and Lookup Key (EM/WC-TCAM) fields.
+ *
+ * Date: 09/29/22 11:50:37
+ *
+ * Note: This file is scripted generated by ./cfa_header_gen.py.
+ * DO NOT modify this file manually !!!!
+ *
+ ****************************************************************************/
+#ifndef _CFA_BLD_P70_FIELD_IDS_H_
+#define _CFA_BLD_P70_FIELD_IDS_H_
+
+/* clang-format off */
+
+/**
+ * Lookup Field Range Check Range Memory Fields:
+ */
+enum cfa_p70_lkup_frc_profile_flds {
+ CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_1_FLD = 0,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_1_FLD = 1,
+ CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_0_FLD = 2,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_FLD = 3,
+ CFA_P70_LKUP_FRC_PROFILE_MAX_FLD
+};
+
+/**
+ * Lookup Connection Tracking State Memory Fields:
+ */
+enum cfa_p70_lkup_ct_state_flds {
+ CFA_P70_LKUP_CT_STATE_NOTIFY_FLD = 0,
+ CFA_P70_LKUP_CT_STATE_NOTIFY_STATE_FLD = 1,
+ CFA_P70_LKUP_CT_STATE_ACTION_FLD = 2,
+ CFA_P70_LKUP_CT_STATE_TIMER_SELECT_FLD = 3,
+ CFA_P70_LKUP_CT_STATE_TIMER_PRELOAD_FLD = 4,
+ CFA_P70_LKUP_CT_STATE_MAX_FLD
+};
+
+/**
+ * Lookup Connection Tracking State Machine Rule Memory Fields:
+ */
+enum cfa_p70_lkup_ct_rule_flds {
+ CFA_P70_LKUP_CT_RULE_VALID_FLD = 0,
+ CFA_P70_LKUP_CT_RULE_MASK_FLD = 1,
+ CFA_P70_LKUP_CT_RULE_PKT_NOT_BG_FLD = 2,
+ CFA_P70_LKUP_CT_RULE_STATE_FLD = 3,
+ CFA_P70_LKUP_CT_RULE_TCP_FLAGS_FLD = 4,
+ CFA_P70_LKUP_CT_RULE_PROT_IS_TCP_FLD = 5,
+ CFA_P70_LKUP_CT_RULE_MSB_UPDT_FLD = 6,
+ CFA_P70_LKUP_CT_RULE_FLAGS_FAILED_FLD = 7,
+ CFA_P70_LKUP_CT_RULE_WIN_FAILED_FLD = 8,
+ CFA_P70_LKUP_CT_RULE_MAX_FLD
+};
+
+/**
+ * Lookup Connection Tracking State Machine Rule Record Memory Fields:
+ */
+enum cfa_p70_lkup_ct_rule_record_flds {
+ CFA_P70_LKUP_CT_RULE_RECORD_ACTION_FLD = 0,
+ CFA_P70_LKUP_CT_RULE_RECORD_NEXT_STATE_FLD = 1,
+ CFA_P70_LKUP_CT_RULE_RECORD_SEND_FLD = 2,
+ CFA_P70_LKUP_CT_RULE_RECORD_MAX_FLD
+};
+
+/**
+ * VEB Destination Bitmap Remap Table. Fields:
+ */
+enum cfa_p70_act_veb_rmp_flds {
+ CFA_P70_ACT_VEB_RMP_MODE_FLD = 0,
+ CFA_P70_ACT_VEB_RMP_ENABLE_FLD = 1,
+ CFA_P70_ACT_VEB_RMP_BITMAP_FLD = 2,
+ CFA_P70_ACT_VEB_RMP_MAX_FLD
+};
+
+/**
+ * Lookup Field Range Check Range Memory Fields:
+ */
+enum cfa_p70_lkup_frc_range_flds {
+ CFA_P70_LKUP_FRC_RANGE_RANGE_LO_FLD = 0,
+ CFA_P70_LKUP_FRC_RANGE_RANGE_HI_FLD = 1,
+ CFA_P70_LKUP_FRC_RANGE_MAX_FLD
+};
+
+/**
+ * L2 Context TCAM. Fields:
+ */
+enum cfa_p70_prof_l2_ctxt_tcam_flds {
+ CFA_P70_PROF_L2_CTXT_TCAM_VALID_FLD = 0,
+ CFA_P70_PROF_L2_CTXT_TCAM_SPARE_FLD = 1,
+ CFA_P70_PROF_L2_CTXT_TCAM_MPASS_CNT_FLD = 2,
+ CFA_P70_PROF_L2_CTXT_TCAM_RCYC_FLD = 3,
+ CFA_P70_PROF_L2_CTXT_TCAM_LOOPBACK_FLD = 4,
+ CFA_P70_PROF_L2_CTXT_TCAM_SPIF_FLD = 5,
+ CFA_P70_PROF_L2_CTXT_TCAM_PARIF_FLD = 6,
+ CFA_P70_PROF_L2_CTXT_TCAM_SVIF_FLD = 7,
+ CFA_P70_PROF_L2_CTXT_TCAM_METADATA_FLD = 8,
+ CFA_P70_PROF_L2_CTXT_TCAM_L2_FUNC_FLD = 9,
+ CFA_P70_PROF_L2_CTXT_TCAM_ROCE_FLD = 10,
+ CFA_P70_PROF_L2_CTXT_TCAM_PURE_LLC_FLD = 11,
+ CFA_P70_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_FLD = 12,
+ CFA_P70_PROF_L2_CTXT_TCAM_T_HDR_TYPE_FLD = 13,
+ CFA_P70_PROF_L2_CTXT_TCAM_ID_CTXT_FLD = 14,
+ CFA_P70_PROF_L2_CTXT_TCAM_MAC0_FLD = 15,
+ CFA_P70_PROF_L2_CTXT_TCAM_MAC1_FLD = 16,
+ CFA_P70_PROF_L2_CTXT_TCAM_VTAG_PRESENT_FLD = 17,
+ CFA_P70_PROF_L2_CTXT_TCAM_TWO_VTAGS_FLD = 18,
+ CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_VID_FLD = 19,
+ CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_FLD = 20,
+ CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_VID_FLD = 21,
+ CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_FLD = 22,
+ CFA_P70_PROF_L2_CTXT_TCAM_ETYPE_FLD = 23,
+ CFA_P70_PROF_L2_CTXT_TCAM_MAX_FLD
+};
+
+/**
+ * Profiler Profile Lookup TCAM Fields:
+ */
+enum cfa_p70_prof_profile_tcam_flds {
+ CFA_P70_PROF_PROFILE_TCAM_VALID_FLD = 0,
+ CFA_P70_PROF_PROFILE_TCAM_SPARE_FLD = 1,
+ CFA_P70_PROF_PROFILE_TCAM_LOOPBACK_FLD = 2,
+ CFA_P70_PROF_PROFILE_TCAM_PKT_TYPE_FLD = 3,
+ CFA_P70_PROF_PROFILE_TCAM_RCYC_FLD = 4,
+ CFA_P70_PROF_PROFILE_TCAM_METADATA_FLD = 5,
+ CFA_P70_PROF_PROFILE_TCAM_AGG_ERROR_FLD = 6,
+ CFA_P70_PROF_PROFILE_TCAM_L2_FUNC_FLD = 7,
+ CFA_P70_PROF_PROFILE_TCAM_PROF_FUNC_FLD = 8,
+ CFA_P70_PROF_PROFILE_TCAM_HREC_NEXT_FLD = 9,
+ CFA_P70_PROF_PROFILE_TCAM_INT_HDR_TYPE_FLD = 10,
+ CFA_P70_PROF_PROFILE_TCAM_INT_HDR_GROUP_FLD = 11,
+ CFA_P70_PROF_PROFILE_TCAM_INT_IFA_TAIL_FLD = 12,
+ CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_VALID_FLD = 13,
+ CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_FLD = 14,
+ CFA_P70_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_FLD = 15,
+ CFA_P70_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_FLD = 16,
+ CFA_P70_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_FLD = 17,
+ CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_VALID_FLD = 18,
+ CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_FLD = 19,
+ CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_FLD = 20,
+ CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_FLD = 21,
+ CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_VALID_FLD = 22,
+ CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_FLD = 23,
+ CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_FLD = 24,
+ CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_FLD = 25,
+ CFA_P70_PROF_PROFILE_TCAM_OT_HDR_VALID_FLD = 26,
+ CFA_P70_PROF_PROFILE_TCAM_OT_HDR_ERROR_FLD = 27,
+ CFA_P70_PROF_PROFILE_TCAM_OT_HDR_TYPE_FLD = 28,
+ CFA_P70_PROF_PROFILE_TCAM_OT_HDR_FLAGS_FLD = 29,
+ CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_VALID_FLD = 30,
+ CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_TYPE_FLD = 31,
+ CFA_P70_PROF_PROFILE_TCAM_TL2_UC_MC_BC_FLD = 32,
+ CFA_P70_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_FLD = 33,
+ CFA_P70_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_FLD = 34,
+ CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_VALID_FLD = 35,
+ CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ERROR_FLD = 36,
+ CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_TYPE_FLD = 37,
+ CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ISIP_FLD = 38,
+ CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_VALID_FLD = 39,
+ CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_ERROR_FLD = 40,
+ CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_TYPE_FLD = 41,
+ CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_FLD = 42,
+ CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_VALID_FLD = 43,
+ CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_ERROR_FLD = 44,
+ CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_TYPE_FLD = 45,
+ CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_FLD = 46,
+ CFA_P70_PROF_PROFILE_TCAM_L2_HDR_VALID_FLD = 47,
+ CFA_P70_PROF_PROFILE_TCAM_L2_HDR_ERROR_FLD = 48,
+ CFA_P70_PROF_PROFILE_TCAM_L2_HDR_TYPE_FLD = 49,
+ CFA_P70_PROF_PROFILE_TCAM_L2_UC_MC_BC_FLD = 50,
+ CFA_P70_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_FLD = 51,
+ CFA_P70_PROF_PROFILE_TCAM_L2_TWO_VTAGS_FLD = 52,
+ CFA_P70_PROF_PROFILE_TCAM_L3_HDR_VALID_FLD = 53,
+ CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ERROR_FLD = 54,
+ CFA_P70_PROF_PROFILE_TCAM_L3_HDR_TYPE_FLD = 55,
+ CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ISIP_FLD = 56,
+ CFA_P70_PROF_PROFILE_TCAM_L3_PROT_FLD = 57,
+ CFA_P70_PROF_PROFILE_TCAM_L4_HDR_VALID_FLD = 58,
+ CFA_P70_PROF_PROFILE_TCAM_L4_HDR_ERROR_FLD = 59,
+ CFA_P70_PROF_PROFILE_TCAM_L4_HDR_TYPE_FLD = 60,
+ CFA_P70_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_FLD = 61,
+ CFA_P70_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_FLD = 62,
+ CFA_P70_PROF_PROFILE_TCAM_L4_HDR_FLAGS_FLD = 63,
+ CFA_P70_PROF_PROFILE_TCAM_L4_DCN_PRESENT_FLD = 64,
+ CFA_P70_PROF_PROFILE_TCAM_MAX_FLD
+};
+
+/**
+ * Action VEB TCAM. TX Fields (VEB Remap Mode):
+ */
+enum cfa_p70_act_veb_tcam_tx_flds {
+ CFA_P70_ACT_VEB_TCAM_TX_VALID_FLD = 0,
+ CFA_P70_ACT_VEB_TCAM_TX_PARIF_IN_FLD = 1,
+ CFA_P70_ACT_VEB_TCAM_TX_NUM_VTAGS_FLD = 2,
+ CFA_P70_ACT_VEB_TCAM_TX_DMAC_FLD = 3,
+ CFA_P70_ACT_VEB_TCAM_TX_OVID_FLD = 4,
+ CFA_P70_ACT_VEB_TCAM_TX_IVID_FLD = 5,
+ CFA_P70_ACT_VEB_TCAM_TX_MAX_FLD
+};
+
+/**
+ * RX Fields (Source Knockout Mode):
+ */
+enum cfa_p70_act_veb_tcam_rx_flds {
+ CFA_P70_ACT_VEB_TCAM_RX_VALID_FLD = 0,
+ CFA_P70_ACT_VEB_TCAM_RX_SPARE_FLD = 1,
+ CFA_P70_ACT_VEB_TCAM_RX_PADDING_FLD = 2,
+ CFA_P70_ACT_VEB_TCAM_RX_UNICAST_FLD = 3,
+ CFA_P70_ACT_VEB_TCAM_RX_MULTICAST_FLD = 4,
+ CFA_P70_ACT_VEB_TCAM_RX_BROADCAST_FLD = 5,
+ CFA_P70_ACT_VEB_TCAM_RX_PFID_FLD = 6,
+ CFA_P70_ACT_VEB_TCAM_RX_VFID_FLD = 7,
+ CFA_P70_ACT_VEB_TCAM_RX_SMAC_FLD = 8,
+ CFA_P70_ACT_VEB_TCAM_RX_MAX_FLD
+};
+
+/**
+ * Action Feature Chaining TCAM.
+ */
+enum cfa_p70_act_fc_tcam_flds {
+ CFA_P70_ACT_FC_TCAM_FC_VALID_FLD = 0,
+ CFA_P70_ACT_FC_TCAM_FC_RSVD_FLD = 1,
+ CFA_P70_ACT_FC_TCAM_FC_METADATA_FLD = 2,
+ CFA_P70_ACT_FC_TCAM_MAX_FLD
+};
+
+/**
+ * Feature Chaining TCAM Remap Table Fields:
+ */
+enum cfa_p70_act_fc_rmp_dr_flds {
+ CFA_P70_ACT_FC_RMP_DR_METADATA_FLD = 0,
+ CFA_P70_ACT_FC_RMP_DR_METAMASK_FLD = 1,
+ CFA_P70_ACT_FC_RMP_DR_L2_FUNC_FLD = 2,
+ CFA_P70_ACT_FC_RMP_DR_MAX_FLD
+};
+
+/**
+ * Profile Input Lookup Table Memory Fields:
+ */
+enum cfa_p70_prof_ilt_dr_flds {
+ CFA_P70_PROF_ILT_DR_ILT_META_EN_FLD = 0,
+ CFA_P70_PROF_ILT_DR_META_PROF_FLD = 1,
+ CFA_P70_PROF_ILT_DR_METADATA_FLD = 2,
+ CFA_P70_PROF_ILT_DR_PARIF_FLD = 3,
+ CFA_P70_PROF_ILT_DR_L2_FUNC_FLD = 4,
+ CFA_P70_PROF_ILT_DR_EN_BD_META_FLD = 5,
+ CFA_P70_PROF_ILT_DR_EN_BD_ACTION_FLD = 6,
+ CFA_P70_PROF_ILT_DR_EN_ILT_DEST_FLD = 7,
+ CFA_P70_PROF_ILT_DR_ILT_FWD_OP_FLD = 8,
+ CFA_P70_PROF_ILT_DR_ILT_ACT_HINT_FLD = 9,
+ CFA_P70_PROF_ILT_DR_ILT_SCOPE_FLD = 10,
+ CFA_P70_PROF_ILT_DR_ILT_ACT_REC_PTR_FLD = 11,
+ CFA_P70_PROF_ILT_DR_ILT_DESTINATION_FLD = 12,
+ CFA_P70_PROF_ILT_DR_MAX_FLD
+};
+
+/**
+ * Profile Lookup TCAM Remap Table Fields:
+ */
+enum cfa_p70_prof_profile_rmp_dr_flds {
+ CFA_P70_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_FLD = 0,
+ CFA_P70_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_FLD = 1,
+ CFA_P70_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_FLD = 2,
+ CFA_P70_PROF_PROFILE_RMP_DR_EM_KEY_ID_FLD = 3,
+ CFA_P70_PROF_PROFILE_RMP_DR_EM_SCOPE_FLD = 4,
+ CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_FLD = 5,
+ CFA_P70_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_FLD = 6,
+ CFA_P70_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_FLD = 7,
+ CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SCOPE_FLD = 8,
+ CFA_P70_PROF_PROFILE_RMP_DR_MAX_FLD
+};
+
+/**
+ * PROF_PROFILE_RMP_DR_BYP
+ */
+enum cfa_p70_prof_profile_rmp_dr_byp_flds {
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_FLD = 0,
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_RESERVED_FLD = 1,
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_FLD = 2,
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_FLD = 3,
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_FLD = 4,
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_FLD = 5,
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_MAX_FLD
+};
+
+/**
+ * VNIC-SVIF Properties Table Fields: TX SVIF Properties Table
+ */
+enum cfa_p70_act_vspt_dr_tx_flds {
+ CFA_P70_ACT_VSPT_DR_TX_TPID_AS_CTL_FLD = 0,
+ CFA_P70_ACT_VSPT_DR_TX_ALWD_TPID_FLD = 1,
+ CFA_P70_ACT_VSPT_DR_TX_DFLT_TPID_FLD = 2,
+ CFA_P70_ACT_VSPT_DR_TX_PRI_AS_CTL_FLD = 3,
+ CFA_P70_ACT_VSPT_DR_TX_ALWD_PRI_FLD = 4,
+ CFA_P70_ACT_VSPT_DR_TX_DFLT_PRI_FLD = 5,
+ CFA_P70_ACT_VSPT_DR_TX_MIR_FLD = 6,
+ CFA_P70_ACT_VSPT_DR_TX_MAX_FLD
+};
+
+/**
+ * RX VNIC Properties Table
+ */
+enum cfa_p70_act_vspt_dr_rx_flds {
+ CFA_P70_ACT_VSPT_DR_RX_RSVD_FLD = 0,
+ CFA_P70_ACT_VSPT_DR_RX_METAFMT_FLD = 1,
+ CFA_P70_ACT_VSPT_DR_RX_FID_FLD = 2,
+ CFA_P70_ACT_VSPT_DR_RX_MIR_FLD = 3,
+ CFA_P70_ACT_VSPT_DR_RX_MAX_FLD
+};
+
+/**
+ * LAG ID Balance Table Fields:
+ */
+enum cfa_p70_act_lbt_dr_flds {
+ CFA_P70_ACT_LBT_DR_DST_BMP_FLD = 0,
+ CFA_P70_ACT_LBT_DR_MAX_FLD
+};
+
+/**
+ * L2 Context Lookup Remap Table Fields:
+ */
+enum cfa_p70_prof_l2_ctxt_rmp_dr_flds {
+ CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_FLD = 0,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_PARIF_FLD = 1,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_FLD = 2,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_FLD = 3,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_FLD = 4,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_PROF_FUNC_FLD = 5,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_FLD = 6,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_FLD = 7,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_FLD = 8,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_FLD = 9,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_FLD = 10,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_FLD = 11,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_FLD = 12,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_FLD = 13,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_FLD = 14,
+ CFA_P70_PROF_L2_CTXT_RMP_DR_MAX_FLD
+};
+
+/**
+ * Multi Field Register.
+ */
+enum cfa_p70_act_fc_tcam_result_flds {
+ CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_RESULT_FLD = 0,
+ CFA_P70_ACT_FC_TCAM_RESULT_UNUSED_0_FLD = 1,
+ CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_HIT_FLD = 2,
+ CFA_P70_ACT_FC_TCAM_RESULT_MAX_FLD
+};
+
+/**
+ * Multi Field Register.
+ */
+enum cfa_p70_act_mirror_flds {
+ CFA_P70_ACT_MIRROR_UNUSED_0_FLD = 0,
+ CFA_P70_ACT_MIRROR_RELATIVE_FLD = 1,
+ CFA_P70_ACT_MIRROR_HINT_FLD = 2,
+ CFA_P70_ACT_MIRROR_SAMP_FLD = 3,
+ CFA_P70_ACT_MIRROR_TRUNC_FLD = 4,
+ CFA_P70_ACT_MIRROR_IGN_DROP_FLD = 5,
+ CFA_P70_ACT_MIRROR_MODE_FLD = 6,
+ CFA_P70_ACT_MIRROR_COND_FLD = 7,
+ CFA_P70_ACT_MIRROR_AR_PTR_FLD = 8,
+ CFA_P70_ACT_MIRROR_SAMP_CFG_FLD = 9,
+ CFA_P70_ACT_MIRROR_MAX_FLD
+};
+
+/**
+ * WC LREC Lookup Record
+ */
+enum cfa_p70_wc_lrec_flds {
+ CFA_P70_WC_LREC_METADATA_FLD = 0,
+ CFA_P70_WC_LREC_META_PROF_FLD = 1,
+ CFA_P70_WC_LREC_PROF_FUNC_FLD = 2,
+ CFA_P70_WC_LREC_RECYCLE_DEST_FLD = 3,
+ CFA_P70_WC_LREC_FC_PTR_FLD = 4,
+ CFA_P70_WC_LREC_FC_TYPE_FLD = 5,
+ CFA_P70_WC_LREC_FC_OP_FLD = 6,
+ CFA_P70_WC_LREC_PATHS_M1_FLD = 7,
+ CFA_P70_WC_LREC_ACT_REC_SIZE_FLD = 8,
+ CFA_P70_WC_LREC_RING_TABLE_IDX_FLD = 9,
+ CFA_P70_WC_LREC_DESTINATION_FLD = 10,
+ CFA_P70_WC_LREC_ACT_REC_PTR_FLD = 11,
+ CFA_P70_WC_LREC_ACT_HINT_FLD = 12,
+ CFA_P70_WC_LREC_STRENGTH_FLD = 13,
+ CFA_P70_WC_LREC_OPCODE_FLD = 14,
+ CFA_P70_WC_LREC_EPOCH1_FLD = 15,
+ CFA_P70_WC_LREC_EPOCH0_FLD = 16,
+ CFA_P70_WC_LREC_REC_SIZE_FLD = 17,
+ CFA_P70_WC_LREC_VALID_FLD = 18,
+ CFA_P70_WC_LREC_MAX_FLD
+};
+
+/**
+ * EM LREC Lookup Record
+ */
+enum cfa_p70_em_lrec_flds {
+ CFA_P70_EM_LREC_RANGE_IDX_FLD = 0,
+ CFA_P70_EM_LREC_RANGE_PROFILE_FLD = 1,
+ CFA_P70_EM_LREC_CREC_TIMER_VALUE_FLD = 2,
+ CFA_P70_EM_LREC_CREC_STATE_FLD = 3,
+ CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_INIT_FLD = 4,
+ CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_FLD = 5,
+ CFA_P70_EM_LREC_CREC_TCP_MSB_LOC_FLD = 6,
+ CFA_P70_EM_LREC_CREC_TCP_WIN_FLD = 7,
+ CFA_P70_EM_LREC_CREC_TCP_UPDT_EN_FLD = 8,
+ CFA_P70_EM_LREC_CREC_TCP_DIR_FLD = 9,
+ CFA_P70_EM_LREC_METADATA_FLD = 10,
+ CFA_P70_EM_LREC_PROF_FUNC_FLD = 11,
+ CFA_P70_EM_LREC_META_PROF_FLD = 12,
+ CFA_P70_EM_LREC_RECYCLE_DEST_FLD = 13,
+ CFA_P70_EM_LREC_FC_PTR_FLD = 14,
+ CFA_P70_EM_LREC_FC_TYPE_FLD = 15,
+ CFA_P70_EM_LREC_FC_OP_FLD = 16,
+ CFA_P70_EM_LREC_PATHS_M1_FLD = 17,
+ CFA_P70_EM_LREC_ACT_REC_SIZE_FLD = 18,
+ CFA_P70_EM_LREC_RING_TABLE_IDX_FLD = 19,
+ CFA_P70_EM_LREC_DESTINATION_FLD = 20,
+ CFA_P70_EM_LREC_ACT_REC_PTR_FLD = 21,
+ CFA_P70_EM_LREC_ACT_HINT_FLD = 22,
+ CFA_P70_EM_LREC_STRENGTH_FLD = 23,
+ CFA_P70_EM_LREC_OPCODE_FLD = 24,
+ CFA_P70_EM_LREC_EPOCH1_FLD = 25,
+ CFA_P70_EM_LREC_EPOCH0_FLD = 26,
+ CFA_P70_EM_LREC_REC_SIZE_FLD = 27,
+ CFA_P70_EM_LREC_VALID_FLD = 28,
+ CFA_P70_EM_LREC_MAX_FLD
+};
+
+/**
+ * EM Lookup Bucket Format
+ */
+enum cfa_p70_em_bucket_flds {
+ CFA_P70_EM_BUCKET_BIN0_ENTRY_FLD = 0,
+ CFA_P70_EM_BUCKET_BIN0_HASH_MSBS_FLD = 1,
+ CFA_P70_EM_BUCKET_BIN1_ENTRY_FLD = 2,
+ CFA_P70_EM_BUCKET_BIN1_HASH_MSBS_FLD = 3,
+ CFA_P70_EM_BUCKET_BIN2_ENTRY_FLD = 4,
+ CFA_P70_EM_BUCKET_BIN2_HASH_MSBS_FLD = 5,
+ CFA_P70_EM_BUCKET_BIN3_ENTRY_FLD = 6,
+ CFA_P70_EM_BUCKET_BIN3_HASH_MSBS_FLD = 7,
+ CFA_P70_EM_BUCKET_BIN4_ENTRY_FLD = 8,
+ CFA_P70_EM_BUCKET_BIN4_HASH_MSBS_FLD = 9,
+ CFA_P70_EM_BUCKET_BIN5_ENTRY_FLD = 10,
+ CFA_P70_EM_BUCKET_BIN5_HASH_MSBS_FLD = 11,
+ CFA_P70_EM_BUCKET_CHAIN_POINTER_FLD = 12,
+ CFA_P70_EM_BUCKET_CHAIN_VALID_FLD = 13,
+ CFA_P70_EM_BUCKET_MAX_FLD
+};
+
+/**
+ * Compact Action Record. The compact action record uses relative
+ * pointers to access needed data. This keeps the compact action record
+ * down to 64b.
+ */
+enum cfa_p70_compact_action_flds {
+ CFA_P70_COMPACT_ACTION_TYPE_FLD = 0,
+ CFA_P70_COMPACT_ACTION_DROP_FLD = 1,
+ CFA_P70_COMPACT_ACTION_VLAN_DELETE_FLD = 2,
+ CFA_P70_COMPACT_ACTION_DEST_FLD = 3,
+ CFA_P70_COMPACT_ACTION_DEST_OP_FLD = 4,
+ CFA_P70_COMPACT_ACTION_DECAP_FLD = 5,
+ CFA_P70_COMPACT_ACTION_MIRRORING_FLD = 6,
+ CFA_P70_COMPACT_ACTION_METER_PTR_FLD = 7,
+ CFA_P70_COMPACT_ACTION_STAT0_OFF_FLD = 8,
+ CFA_P70_COMPACT_ACTION_STAT0_OP_FLD = 9,
+ CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_FLD = 10,
+ CFA_P70_COMPACT_ACTION_MOD_OFF_FLD = 11,
+ CFA_P70_COMPACT_ACTION_ENC_OFF_FLD = 12,
+ CFA_P70_COMPACT_ACTION_SRC_OFF_FLD = 13,
+ CFA_P70_COMPACT_ACTION_UNUSED_0_FLD = 14,
+ CFA_P70_COMPACT_ACTION_MAX_FLD
+};
+
+/**
+ * Full Action Record. The full action record uses full pointers to
+ * access needed data. It also allows access to all the action features.
+ * The Full Action record is 192b.
+ */
+enum cfa_p70_full_action_flds {
+ CFA_P70_FULL_ACTION_TYPE_FLD = 0,
+ CFA_P70_FULL_ACTION_DROP_FLD = 1,
+ CFA_P70_FULL_ACTION_VLAN_DELETE_FLD = 2,
+ CFA_P70_FULL_ACTION_DEST_FLD = 3,
+ CFA_P70_FULL_ACTION_DEST_OP_FLD = 4,
+ CFA_P70_FULL_ACTION_DECAP_FLD = 5,
+ CFA_P70_FULL_ACTION_MIRRORING_FLD = 6,
+ CFA_P70_FULL_ACTION_METER_PTR_FLD = 7,
+ CFA_P70_FULL_ACTION_STAT0_PTR_FLD = 8,
+ CFA_P70_FULL_ACTION_STAT0_OP_FLD = 9,
+ CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_FLD = 10,
+ CFA_P70_FULL_ACTION_STAT1_PTR_FLD = 11,
+ CFA_P70_FULL_ACTION_STAT1_OP_FLD = 12,
+ CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_FLD = 13,
+ CFA_P70_FULL_ACTION_MOD_PTR_FLD = 14,
+ CFA_P70_FULL_ACTION_ENC_PTR_FLD = 15,
+ CFA_P70_FULL_ACTION_SRC_PTR_FLD = 16,
+ CFA_P70_FULL_ACTION_UNUSED_0_FLD = 17,
+ CFA_P70_FULL_ACTION_MAX_FLD
+};
+
+/**
+ * Multicast Group Action Record. This action is used to send the packet
+ * to multiple destinations. The MGC Action record is 256b.
+ */
+enum cfa_p70_mcg_action_flds {
+ CFA_P70_MCG_ACTION_TYPE_FLD = 0,
+ CFA_P70_MCG_ACTION_SRC_KO_EN_FLD = 1,
+ CFA_P70_MCG_ACTION_UNUSED_0_FLD = 2,
+ CFA_P70_MCG_ACTION_NEXT_PTR_FLD = 3,
+ CFA_P70_MCG_ACTION_PTR0_ACT_HINT_FLD = 4,
+ CFA_P70_MCG_ACTION_PTR0_ACT_REC_PTR_FLD = 5,
+ CFA_P70_MCG_ACTION_PTR1_ACT_HINT_FLD = 6,
+ CFA_P70_MCG_ACTION_PTR1_ACT_REC_PTR_FLD = 7,
+ CFA_P70_MCG_ACTION_PTR2_ACT_HINT_FLD = 8,
+ CFA_P70_MCG_ACTION_PTR2_ACT_REC_PTR_FLD = 9,
+ CFA_P70_MCG_ACTION_PTR3_ACT_HINT_FLD = 10,
+ CFA_P70_MCG_ACTION_PTR3_ACT_REC_PTR_FLD = 11,
+ CFA_P70_MCG_ACTION_PTR4_ACT_HINT_FLD = 12,
+ CFA_P70_MCG_ACTION_PTR4_ACT_REC_PTR_FLD = 13,
+ CFA_P70_MCG_ACTION_PTR5_ACT_HINT_FLD = 14,
+ CFA_P70_MCG_ACTION_PTR5_ACT_REC_PTR_FLD = 15,
+ CFA_P70_MCG_ACTION_PTR6_ACT_HINT_FLD = 16,
+ CFA_P70_MCG_ACTION_PTR6_ACT_REC_PTR_FLD = 17,
+ CFA_P70_MCG_ACTION_PTR7_ACT_HINT_FLD = 18,
+ CFA_P70_MCG_ACTION_PTR7_ACT_REC_PTR_FLD = 19,
+ CFA_P70_MCG_ACTION_MAX_FLD
+};
+
+/**
+ * Multicast Group Action Record. This action is used to send the packet
+ * to multiple destinations. The MGC Action record is 256b.
+ */
+enum cfa_p70_mcg_subseq_action_flds {
+ CFA_P70_MCG_SUBSEQ_ACTION_TYPE_FLD = 0,
+ CFA_P70_MCG_SUBSEQ_ACTION_UNUSED_0_FLD = 1,
+ CFA_P70_MCG_SUBSEQ_ACTION_NEXT_PTR_FLD = 2,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_FLD = 3,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_FLD = 4,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_FLD = 5,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_FLD = 6,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_FLD = 7,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_FLD = 8,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_FLD = 9,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_FLD = 10,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_FLD = 11,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_FLD = 12,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_FLD = 13,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_FLD = 14,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_FLD = 15,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_FLD = 16,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_FLD = 17,
+ CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_FLD = 18,
+ CFA_P70_MCG_SUBSEQ_ACTION_MAX_FLD
+};
+
+/**
+ * Action Meter Formats
+ */
+enum cfa_p70_meters_flds {
+ CFA_P70_METERS_BKT_C_FLD = 0,
+ CFA_P70_METERS_BKT_E_FLD = 1,
+ CFA_P70_METERS_FLAGS_MTR_VAL_FLD = 2,
+ CFA_P70_METERS_FLAGS_ECN_RMP_EN_FLD = 3,
+ CFA_P70_METERS_FLAGS_CF_FLD = 4,
+ CFA_P70_METERS_FLAGS_PM_FLD = 5,
+ CFA_P70_METERS_FLAGS_RFC2698_FLD = 6,
+ CFA_P70_METERS_FLAGS_CBSM_FLD = 7,
+ CFA_P70_METERS_FLAGS_EBSM_FLD = 8,
+ CFA_P70_METERS_FLAGS_CBND_FLD = 9,
+ CFA_P70_METERS_FLAGS_EBND_FLD = 10,
+ CFA_P70_METERS_CBS_FLD = 11,
+ CFA_P70_METERS_EBS_FLD = 12,
+ CFA_P70_METERS_CIR_FLD = 13,
+ CFA_P70_METERS_EIR_FLD = 14,
+ CFA_P70_METERS_PROTECTION_SCOPE_FLD = 15,
+ CFA_P70_METERS_PROTECTION_RSVD_FLD = 16,
+ CFA_P70_METERS_PROTECTION_ENABLE_FLD = 17,
+ CFA_P70_METERS_MAX_FLD
+};
+
+/**
+ * Enumeration for fkb
+ */
+enum cfa_p70_fkb_flds {
+ CFA_P70_FKB_PROF_ID_FLD = 0,
+ CFA_P70_FKB_L2CTXT_FLD = 1,
+ CFA_P70_FKB_L2FUNC_FLD = 2,
+ CFA_P70_FKB_PARIF_FLD = 3,
+ CFA_P70_FKB_SPIF_FLD = 4,
+ CFA_P70_FKB_SVIF_FLD = 5,
+ CFA_P70_FKB_LCOS_FLD = 6,
+ CFA_P70_FKB_META_HI_FLD = 7,
+ CFA_P70_FKB_META_LO_FLD = 8,
+ CFA_P70_FKB_RCYC_CNT_FLD = 9,
+ CFA_P70_FKB_LOOPBACK_FLD = 10,
+ CFA_P70_FKB_OTL2_TYPE_FLD = 11,
+ CFA_P70_FKB_OTL2_DMAC_FLD = 12,
+ CFA_P70_FKB_OTL2_SMAC_FLD = 13,
+ CFA_P70_FKB_OTL2_DT_FLD = 14,
+ CFA_P70_FKB_OTL2_SA_FLD = 15,
+ CFA_P70_FKB_OTL2_NVT_FLD = 16,
+ CFA_P70_FKB_OTL2_OVP_FLD = 17,
+ CFA_P70_FKB_OTL2_OVD_FLD = 18,
+ CFA_P70_FKB_OTL2_OVV_FLD = 19,
+ CFA_P70_FKB_OTL2_OVT_FLD = 20,
+ CFA_P70_FKB_OTL2_IVP_FLD = 21,
+ CFA_P70_FKB_OTL2_IVD_FLD = 22,
+ CFA_P70_FKB_OTL2_IVV_FLD = 23,
+ CFA_P70_FKB_OTL2_IVT_FLD = 24,
+ CFA_P70_FKB_OTL2_ETYPE_FLD = 25,
+ CFA_P70_FKB_OTL3_TYPE_FLD = 26,
+ CFA_P70_FKB_OTL3_SIP3_FLD = 27,
+ CFA_P70_FKB_OTL3_SIP2_FLD = 28,
+ CFA_P70_FKB_OTL3_SIP1_FLD = 29,
+ CFA_P70_FKB_OTL3_SIP0_FLD = 30,
+ CFA_P70_FKB_OTL3_DIP3_FLD = 31,
+ CFA_P70_FKB_OTL3_DIP2_FLD = 32,
+ CFA_P70_FKB_OTL3_DIP1_FLD = 33,
+ CFA_P70_FKB_OTL3_DIP0_FLD = 34,
+ CFA_P70_FKB_OTL3_TTL_FLD = 35,
+ CFA_P70_FKB_OTL3_PROT_FLD = 36,
+ CFA_P70_FKB_OTL3_FID_FLD = 37,
+ CFA_P70_FKB_OTL3_QOS_FLD = 38,
+ CFA_P70_FKB_OTL3_IEH_NONEXT_FLD = 39,
+ CFA_P70_FKB_OTL3_IEH_SEP_FLD = 40,
+ CFA_P70_FKB_OTL3_IEH_AUTH_FLD = 41,
+ CFA_P70_FKB_OTL3_IEH_DEST_FLD = 42,
+ CFA_P70_FKB_OTL3_IEH_FRAG_FLD = 43,
+ CFA_P70_FKB_OTL3_IEH_RTHDR_FLD = 44,
+ CFA_P70_FKB_OTL3_IEH_HOP_FLD = 45,
+ CFA_P70_FKB_OTL3_IEH_1FRAG_FLD = 46,
+ CFA_P70_FKB_OTL3_DF_FLD = 47,
+ CFA_P70_FKB_OTL3_L3ERR_FLD = 48,
+ CFA_P70_FKB_OTL4_TYPE_FLD = 49,
+ CFA_P70_FKB_OTL4_SRC_FLD = 50,
+ CFA_P70_FKB_OTL4_DST_FLD = 51,
+ CFA_P70_FKB_OTL4_FLAGS_FLD = 52,
+ CFA_P70_FKB_OTL4_SEQ_FLD = 53,
+ CFA_P70_FKB_OTL4_PA_FLD = 54,
+ CFA_P70_FKB_OTL4_OPT_FLD = 55,
+ CFA_P70_FKB_OTL4_TCPTS_FLD = 56,
+ CFA_P70_FKB_OTL4_ERR_FLD = 57,
+ CFA_P70_FKB_OT_TYPE_FLD = 58,
+ CFA_P70_FKB_OT_FLAGS_FLD = 59,
+ CFA_P70_FKB_OT_IDS_FLD = 60,
+ CFA_P70_FKB_OT_ID_FLD = 61,
+ CFA_P70_FKB_OT_CTXTS_FLD = 62,
+ CFA_P70_FKB_OT_CTXT_FLD = 63,
+ CFA_P70_FKB_OT_QOS_FLD = 64,
+ CFA_P70_FKB_OT_ERR_FLD = 65,
+ CFA_P70_FKB_TL2_TYPE_FLD = 66,
+ CFA_P70_FKB_TL2_DMAC_FLD = 67,
+ CFA_P70_FKB_TL2_SMAC_FLD = 68,
+ CFA_P70_FKB_TL2_DT_FLD = 69,
+ CFA_P70_FKB_TL2_SA_FLD = 70,
+ CFA_P70_FKB_TL2_NVT_FLD = 71,
+ CFA_P70_FKB_TL2_OVP_FLD = 72,
+ CFA_P70_FKB_TL2_OVD_FLD = 73,
+ CFA_P70_FKB_TL2_OVV_FLD = 74,
+ CFA_P70_FKB_TL2_OVT_FLD = 75,
+ CFA_P70_FKB_TL2_IVP_FLD = 76,
+ CFA_P70_FKB_TL2_IVD_FLD = 77,
+ CFA_P70_FKB_TL2_IVV_FLD = 78,
+ CFA_P70_FKB_TL2_IVT_FLD = 79,
+ CFA_P70_FKB_TL2_ETYPE_FLD = 80,
+ CFA_P70_FKB_TL3_TYPE_FLD = 81,
+ CFA_P70_FKB_TL3_SIP3_FLD = 82,
+ CFA_P70_FKB_TL3_SIP2_FLD = 83,
+ CFA_P70_FKB_TL3_SIP1_FLD = 84,
+ CFA_P70_FKB_TL3_SIP0_FLD = 85,
+ CFA_P70_FKB_TL3_DIP3_FLD = 86,
+ CFA_P70_FKB_TL3_DIP2_FLD = 87,
+ CFA_P70_FKB_TL3_DIP1_FLD = 88,
+ CFA_P70_FKB_TL3_DIP0_FLD = 89,
+ CFA_P70_FKB_TL3_TTL_FLD = 90,
+ CFA_P70_FKB_TL3_PROT_FLD = 91,
+ CFA_P70_FKB_TL3_FID_FLD = 92,
+ CFA_P70_FKB_TL3_QOS_FLD = 93,
+ CFA_P70_FKB_TL3_IEH_NONEXT_FLD = 94,
+ CFA_P70_FKB_TL3_IEH_SEP_FLD = 95,
+ CFA_P70_FKB_TL3_IEH_AUTH_FLD = 96,
+ CFA_P70_FKB_TL3_IEH_DEST_FLD = 97,
+ CFA_P70_FKB_TL3_IEH_FRAG_FLD = 98,
+ CFA_P70_FKB_TL3_IEH_RTHDR_FLD = 99,
+ CFA_P70_FKB_TL3_IEH_HOP_FLD = 100,
+ CFA_P70_FKB_TL3_IEH_1FRAG_FLD = 101,
+ CFA_P70_FKB_TL3_DF_FLD = 102,
+ CFA_P70_FKB_TL3_L3ERR_FLD = 103,
+ CFA_P70_FKB_TL4_TYPE_FLD = 104,
+ CFA_P70_FKB_TL4_SRC_FLD = 105,
+ CFA_P70_FKB_TL4_DST_FLD = 106,
+ CFA_P70_FKB_TL4_FLAGS_FLD = 107,
+ CFA_P70_FKB_TL4_SEQ_FLD = 108,
+ CFA_P70_FKB_TL4_PA_FLD = 109,
+ CFA_P70_FKB_TL4_OPT_FLD = 110,
+ CFA_P70_FKB_TL4_TCPTS_FLD = 111,
+ CFA_P70_FKB_TL4_ERR_FLD = 112,
+ CFA_P70_FKB_T_TYPE_FLD = 113,
+ CFA_P70_FKB_T_FLAGS_FLD = 114,
+ CFA_P70_FKB_T_IDS_FLD = 115,
+ CFA_P70_FKB_T_ID_FLD = 116,
+ CFA_P70_FKB_T_CTXTS_FLD = 117,
+ CFA_P70_FKB_T_CTXT_FLD = 118,
+ CFA_P70_FKB_T_QOS_FLD = 119,
+ CFA_P70_FKB_T_ERR_FLD = 120,
+ CFA_P70_FKB_L2_TYPE_FLD = 121,
+ CFA_P70_FKB_L2_DMAC_FLD = 122,
+ CFA_P70_FKB_L2_SMAC_FLD = 123,
+ CFA_P70_FKB_L2_DT_FLD = 124,
+ CFA_P70_FKB_L2_SA_FLD = 125,
+ CFA_P70_FKB_L2_NVT_FLD = 126,
+ CFA_P70_FKB_L2_OVP_FLD = 127,
+ CFA_P70_FKB_L2_OVD_FLD = 128,
+ CFA_P70_FKB_L2_OVV_FLD = 129,
+ CFA_P70_FKB_L2_OVT_FLD = 130,
+ CFA_P70_FKB_L2_IVP_FLD = 131,
+ CFA_P70_FKB_L2_IVD_FLD = 132,
+ CFA_P70_FKB_L2_IVV_FLD = 133,
+ CFA_P70_FKB_L2_IVT_FLD = 134,
+ CFA_P70_FKB_L2_ETYPE_FLD = 135,
+ CFA_P70_FKB_L3_TYPE_FLD = 136,
+ CFA_P70_FKB_L3_SIP3_FLD = 137,
+ CFA_P70_FKB_L3_SIP2_FLD = 138,
+ CFA_P70_FKB_L3_SIP1_FLD = 139,
+ CFA_P70_FKB_L3_SIP0_FLD = 140,
+ CFA_P70_FKB_L3_DIP3_FLD = 141,
+ CFA_P70_FKB_L3_DIP2_FLD = 142,
+ CFA_P70_FKB_L3_DIP1_FLD = 143,
+ CFA_P70_FKB_L3_DIP0_FLD = 144,
+ CFA_P70_FKB_L3_TTL_FLD = 145,
+ CFA_P70_FKB_L3_PROT_FLD = 146,
+ CFA_P70_FKB_L3_FID_FLD = 147,
+ CFA_P70_FKB_L3_QOS_FLD = 148,
+ CFA_P70_FKB_L3_IEH_NONEXT_FLD = 149,
+ CFA_P70_FKB_L3_IEH_SEP_FLD = 150,
+ CFA_P70_FKB_L3_IEH_AUTH_FLD = 151,
+ CFA_P70_FKB_L3_IEH_DEST_FLD = 152,
+ CFA_P70_FKB_L3_IEH_FRAG_FLD = 153,
+ CFA_P70_FKB_L3_IEH_RTHDR_FLD = 154,
+ CFA_P70_FKB_L3_IEH_HOP_FLD = 155,
+ CFA_P70_FKB_L3_IEH_1FRAG_FLD = 156,
+ CFA_P70_FKB_L3_DF_FLD = 157,
+ CFA_P70_FKB_L3_L3ERR_FLD = 158,
+ CFA_P70_FKB_L4_TYPE_FLD = 159,
+ CFA_P70_FKB_L4_SRC_FLD = 160,
+ CFA_P70_FKB_L4_DST_FLD = 161,
+ CFA_P70_FKB_L4_FLAGS_FLD = 162,
+ CFA_P70_FKB_L4_SEQ_FLD = 163,
+ CFA_P70_FKB_L4_ACK_FLD = 164,
+ CFA_P70_FKB_L4_WIN_FLD = 165,
+ CFA_P70_FKB_L4_PA_FLD = 166,
+ CFA_P70_FKB_L4_OPT_FLD = 167,
+ CFA_P70_FKB_L4_TCPTS_FLD = 168,
+ CFA_P70_FKB_L4_TSVAL_FLD = 169,
+ CFA_P70_FKB_L4_TXECR_FLD = 170,
+ CFA_P70_FKB_L4_ERR_FLD = 171,
+ CFA_P70_FKB_MAX_FLD = 172,
+};
+
+/**
+ * Enumeration for wc tcam fkb
+ */
+enum cfa_p70_wc_tcam_fkb_flds {
+ CFA_P70_WC_TCAM_FKB_PROF_ID_FLD = 0,
+ CFA_P70_WC_TCAM_FKB_L2CTXT_FLD = 1,
+ CFA_P70_WC_TCAM_FKB_L2FUNC_FLD = 2,
+ CFA_P70_WC_TCAM_FKB_PARIF_FLD = 3,
+ CFA_P70_WC_TCAM_FKB_SPIF_FLD = 4,
+ CFA_P70_WC_TCAM_FKB_SVIF_FLD = 5,
+ CFA_P70_WC_TCAM_FKB_LCOS_FLD = 6,
+ CFA_P70_WC_TCAM_FKB_META_HI_FLD = 7,
+ CFA_P70_WC_TCAM_FKB_META_LO_FLD = 8,
+ CFA_P70_WC_TCAM_FKB_RCYC_CNT_FLD = 9,
+ CFA_P70_WC_TCAM_FKB_LOOPBACK_FLD = 10,
+ CFA_P70_WC_TCAM_FKB_OTL2_TYPE_FLD = 11,
+ CFA_P70_WC_TCAM_FKB_OTL2_DMAC_FLD = 12,
+ CFA_P70_WC_TCAM_FKB_OTL2_SMAC_FLD = 13,
+ CFA_P70_WC_TCAM_FKB_OTL2_DT_FLD = 14,
+ CFA_P70_WC_TCAM_FKB_OTL2_SA_FLD = 15,
+ CFA_P70_WC_TCAM_FKB_OTL2_NVT_FLD = 16,
+ CFA_P70_WC_TCAM_FKB_OTL2_OVP_FLD = 17,
+ CFA_P70_WC_TCAM_FKB_OTL2_OVD_FLD = 18,
+ CFA_P70_WC_TCAM_FKB_OTL2_OVV_FLD = 19,
+ CFA_P70_WC_TCAM_FKB_OTL2_OVT_FLD = 20,
+ CFA_P70_WC_TCAM_FKB_OTL2_IVP_FLD = 21,
+ CFA_P70_WC_TCAM_FKB_OTL2_IVD_FLD = 22,
+ CFA_P70_WC_TCAM_FKB_OTL2_IVV_FLD = 23,
+ CFA_P70_WC_TCAM_FKB_OTL2_IVT_FLD = 24,
+ CFA_P70_WC_TCAM_FKB_OTL2_ETYPE_FLD = 25,
+ CFA_P70_WC_TCAM_FKB_OTL3_TYPE_FLD = 26,
+ CFA_P70_WC_TCAM_FKB_OTL3_SIP3_FLD = 27,
+ CFA_P70_WC_TCAM_FKB_OTL3_SIP2_FLD = 28,
+ CFA_P70_WC_TCAM_FKB_OTL3_SIP1_FLD = 29,
+ CFA_P70_WC_TCAM_FKB_OTL3_SIP0_FLD = 30,
+ CFA_P70_WC_TCAM_FKB_OTL3_DIP3_FLD = 31,
+ CFA_P70_WC_TCAM_FKB_OTL3_DIP2_FLD = 32,
+ CFA_P70_WC_TCAM_FKB_OTL3_DIP1_FLD = 33,
+ CFA_P70_WC_TCAM_FKB_OTL3_DIP0_FLD = 34,
+ CFA_P70_WC_TCAM_FKB_OTL3_TTL_FLD = 35,
+ CFA_P70_WC_TCAM_FKB_OTL3_PROT_FLD = 36,
+ CFA_P70_WC_TCAM_FKB_OTL3_FID_FLD = 37,
+ CFA_P70_WC_TCAM_FKB_OTL3_QOS_FLD = 38,
+ CFA_P70_WC_TCAM_FKB_OTL3_IEH_NONEXT_FLD = 39,
+ CFA_P70_WC_TCAM_FKB_OTL3_IEH_SEP_FLD = 40,
+ CFA_P70_WC_TCAM_FKB_OTL3_IEH_AUTH_FLD = 41,
+ CFA_P70_WC_TCAM_FKB_OTL3_IEH_DEST_FLD = 42,
+ CFA_P70_WC_TCAM_FKB_OTL3_IEH_FRAG_FLD = 43,
+ CFA_P70_WC_TCAM_FKB_OTL3_IEH_RTHDR_FLD = 44,
+ CFA_P70_WC_TCAM_FKB_OTL3_IEH_HOP_FLD = 45,
+ CFA_P70_WC_TCAM_FKB_OTL3_IEH_1FRAG_FLD = 46,
+ CFA_P70_WC_TCAM_FKB_OTL3_DF_FLD = 47,
+ CFA_P70_WC_TCAM_FKB_OTL3_L3ERR_FLD = 48,
+ CFA_P70_WC_TCAM_FKB_OTL4_TYPE_FLD = 49,
+ CFA_P70_WC_TCAM_FKB_OTL4_SRC_FLD = 50,
+ CFA_P70_WC_TCAM_FKB_OTL4_DST_FLD = 51,
+ CFA_P70_WC_TCAM_FKB_OTL4_FLAGS_FLD = 52,
+ CFA_P70_WC_TCAM_FKB_OTL4_SEQ_FLD = 53,
+ CFA_P70_WC_TCAM_FKB_OTL4_PA_FLD = 54,
+ CFA_P70_WC_TCAM_FKB_OTL4_OPT_FLD = 55,
+ CFA_P70_WC_TCAM_FKB_OTL4_TCPTS_FLD = 56,
+ CFA_P70_WC_TCAM_FKB_OTL4_ERR_FLD = 57,
+ CFA_P70_WC_TCAM_FKB_OT_TYPE_FLD = 58,
+ CFA_P70_WC_TCAM_FKB_OT_FLAGS_FLD = 59,
+ CFA_P70_WC_TCAM_FKB_OT_IDS_FLD = 60,
+ CFA_P70_WC_TCAM_FKB_OT_ID_FLD = 61,
+ CFA_P70_WC_TCAM_FKB_OT_CTXTS_FLD = 62,
+ CFA_P70_WC_TCAM_FKB_OT_CTXT_FLD = 63,
+ CFA_P70_WC_TCAM_FKB_OT_QOS_FLD = 64,
+ CFA_P70_WC_TCAM_FKB_OT_ERR_FLD = 65,
+ CFA_P70_WC_TCAM_FKB_TL2_TYPE_FLD = 66,
+ CFA_P70_WC_TCAM_FKB_TL2_DMAC_FLD = 67,
+ CFA_P70_WC_TCAM_FKB_TL2_SMAC_FLD = 68,
+ CFA_P70_WC_TCAM_FKB_TL2_DT_FLD = 69,
+ CFA_P70_WC_TCAM_FKB_TL2_SA_FLD = 70,
+ CFA_P70_WC_TCAM_FKB_TL2_NVT_FLD = 71,
+ CFA_P70_WC_TCAM_FKB_TL2_OVP_FLD = 72,
+ CFA_P70_WC_TCAM_FKB_TL2_OVD_FLD = 73,
+ CFA_P70_WC_TCAM_FKB_TL2_OVV_FLD = 74,
+ CFA_P70_WC_TCAM_FKB_TL2_OVT_FLD = 75,
+ CFA_P70_WC_TCAM_FKB_TL2_IVP_FLD = 76,
+ CFA_P70_WC_TCAM_FKB_TL2_IVD_FLD = 77,
+ CFA_P70_WC_TCAM_FKB_TL2_IVV_FLD = 78,
+ CFA_P70_WC_TCAM_FKB_TL2_IVT_FLD = 79,
+ CFA_P70_WC_TCAM_FKB_TL2_ETYPE_FLD = 80,
+ CFA_P70_WC_TCAM_FKB_TL3_TYPE_FLD = 81,
+ CFA_P70_WC_TCAM_FKB_TL3_SIP3_FLD = 82,
+ CFA_P70_WC_TCAM_FKB_TL3_SIP2_FLD = 83,
+ CFA_P70_WC_TCAM_FKB_TL3_SIP1_FLD = 84,
+ CFA_P70_WC_TCAM_FKB_TL3_SIP0_FLD = 85,
+ CFA_P70_WC_TCAM_FKB_TL3_DIP3_FLD = 86,
+ CFA_P70_WC_TCAM_FKB_TL3_DIP2_FLD = 87,
+ CFA_P70_WC_TCAM_FKB_TL3_DIP1_FLD = 88,
+ CFA_P70_WC_TCAM_FKB_TL3_DIP0_FLD = 89,
+ CFA_P70_WC_TCAM_FKB_TL3_TTL_FLD = 90,
+ CFA_P70_WC_TCAM_FKB_TL3_PROT_FLD = 91,
+ CFA_P70_WC_TCAM_FKB_TL3_FID_FLD = 92,
+ CFA_P70_WC_TCAM_FKB_TL3_QOS_FLD = 93,
+ CFA_P70_WC_TCAM_FKB_TL3_IEH_NONEXT_FLD = 94,
+ CFA_P70_WC_TCAM_FKB_TL3_IEH_SEP_FLD = 95,
+ CFA_P70_WC_TCAM_FKB_TL3_IEH_AUTH_FLD = 96,
+ CFA_P70_WC_TCAM_FKB_TL3_IEH_DEST_FLD = 97,
+ CFA_P70_WC_TCAM_FKB_TL3_IEH_FRAG_FLD = 98,
+ CFA_P70_WC_TCAM_FKB_TL3_IEH_RTHDR_FLD = 99,
+ CFA_P70_WC_TCAM_FKB_TL3_IEH_HOP_FLD = 100,
+ CFA_P70_WC_TCAM_FKB_TL3_IEH_1FRAG_FLD = 101,
+ CFA_P70_WC_TCAM_FKB_TL3_DF_FLD = 102,
+ CFA_P70_WC_TCAM_FKB_TL3_L3ERR_FLD = 103,
+ CFA_P70_WC_TCAM_FKB_TL4_TYPE_FLD = 104,
+ CFA_P70_WC_TCAM_FKB_TL4_SRC_FLD = 105,
+ CFA_P70_WC_TCAM_FKB_TL4_DST_FLD = 106,
+ CFA_P70_WC_TCAM_FKB_TL4_FLAGS_FLD = 107,
+ CFA_P70_WC_TCAM_FKB_TL4_SEQ_FLD = 108,
+ CFA_P70_WC_TCAM_FKB_TL4_PA_FLD = 109,
+ CFA_P70_WC_TCAM_FKB_TL4_OPT_FLD = 110,
+ CFA_P70_WC_TCAM_FKB_TL4_TCPTS_FLD = 111,
+ CFA_P70_WC_TCAM_FKB_TL4_ERR_FLD = 112,
+ CFA_P70_WC_TCAM_FKB_T_TYPE_FLD = 113,
+ CFA_P70_WC_TCAM_FKB_T_FLAGS_FLD = 114,
+ CFA_P70_WC_TCAM_FKB_T_IDS_FLD = 115,
+ CFA_P70_WC_TCAM_FKB_T_ID_FLD = 116,
+ CFA_P70_WC_TCAM_FKB_T_CTXTS_FLD = 117,
+ CFA_P70_WC_TCAM_FKB_T_CTXT_FLD = 118,
+ CFA_P70_WC_TCAM_FKB_T_QOS_FLD = 119,
+ CFA_P70_WC_TCAM_FKB_T_ERR_FLD = 120,
+ CFA_P70_WC_TCAM_FKB_L2_TYPE_FLD = 121,
+ CFA_P70_WC_TCAM_FKB_L2_DMAC_FLD = 122,
+ CFA_P70_WC_TCAM_FKB_L2_SMAC_FLD = 123,
+ CFA_P70_WC_TCAM_FKB_L2_DT_FLD = 124,
+ CFA_P70_WC_TCAM_FKB_L2_SA_FLD = 125,
+ CFA_P70_WC_TCAM_FKB_L2_NVT_FLD = 126,
+ CFA_P70_WC_TCAM_FKB_L2_OVP_FLD = 127,
+ CFA_P70_WC_TCAM_FKB_L2_OVD_FLD = 128,
+ CFA_P70_WC_TCAM_FKB_L2_OVV_FLD = 129,
+ CFA_P70_WC_TCAM_FKB_L2_OVT_FLD = 130,
+ CFA_P70_WC_TCAM_FKB_L2_IVP_FLD = 131,
+ CFA_P70_WC_TCAM_FKB_L2_IVD_FLD = 132,
+ CFA_P70_WC_TCAM_FKB_L2_IVV_FLD = 133,
+ CFA_P70_WC_TCAM_FKB_L2_IVT_FLD = 134,
+ CFA_P70_WC_TCAM_FKB_L2_ETYPE_FLD = 135,
+ CFA_P70_WC_TCAM_FKB_L3_TYPE_FLD = 136,
+ CFA_P70_WC_TCAM_FKB_L3_SIP3_FLD = 137,
+ CFA_P70_WC_TCAM_FKB_L3_SIP2_FLD = 138,
+ CFA_P70_WC_TCAM_FKB_L3_SIP1_FLD = 139,
+ CFA_P70_WC_TCAM_FKB_L3_SIP0_FLD = 140,
+ CFA_P70_WC_TCAM_FKB_L3_DIP3_FLD = 141,
+ CFA_P70_WC_TCAM_FKB_L3_DIP2_FLD = 142,
+ CFA_P70_WC_TCAM_FKB_L3_DIP1_FLD = 143,
+ CFA_P70_WC_TCAM_FKB_L3_DIP0_FLD = 144,
+ CFA_P70_WC_TCAM_FKB_L3_TTL_FLD = 145,
+ CFA_P70_WC_TCAM_FKB_L3_PROT_FLD = 146,
+ CFA_P70_WC_TCAM_FKB_L3_FID_FLD = 147,
+ CFA_P70_WC_TCAM_FKB_L3_QOS_FLD = 148,
+ CFA_P70_WC_TCAM_FKB_L3_IEH_NONEXT_FLD = 149,
+ CFA_P70_WC_TCAM_FKB_L3_IEH_SEP_FLD = 150,
+ CFA_P70_WC_TCAM_FKB_L3_IEH_AUTH_FLD = 151,
+ CFA_P70_WC_TCAM_FKB_L3_IEH_DEST_FLD = 152,
+ CFA_P70_WC_TCAM_FKB_L3_IEH_FRAG_FLD = 153,
+ CFA_P70_WC_TCAM_FKB_L3_IEH_RTHDR_FLD = 154,
+ CFA_P70_WC_TCAM_FKB_L3_IEH_HOP_FLD = 155,
+ CFA_P70_WC_TCAM_FKB_L3_IEH_1FRAG_FLD = 156,
+ CFA_P70_WC_TCAM_FKB_L3_DF_FLD = 157,
+ CFA_P70_WC_TCAM_FKB_L3_L3ERR_FLD = 158,
+ CFA_P70_WC_TCAM_FKB_L4_TYPE_FLD = 159,
+ CFA_P70_WC_TCAM_FKB_L4_SRC_FLD = 160,
+ CFA_P70_WC_TCAM_FKB_L4_DST_FLD = 161,
+ CFA_P70_WC_TCAM_FKB_L4_FLAGS_FLD = 162,
+ CFA_P70_WC_TCAM_FKB_L4_SEQ_FLD = 163,
+ CFA_P70_WC_TCAM_FKB_L4_ACK_FLD = 164,
+ CFA_P70_WC_TCAM_FKB_L4_WIN_FLD = 165,
+ CFA_P70_WC_TCAM_FKB_L4_PA_FLD = 166,
+ CFA_P70_WC_TCAM_FKB_L4_OPT_FLD = 167,
+ CFA_P70_WC_TCAM_FKB_L4_TCPTS_FLD = 168,
+ CFA_P70_WC_TCAM_FKB_L4_TSVAL_FLD = 169,
+ CFA_P70_WC_TCAM_FKB_L4_TXECR_FLD = 170,
+ CFA_P70_WC_TCAM_FKB_L4_ERR_FLD = 171,
+ CFA_P70_WC_TCAM_FKB_MAX_FLD = 172,
+};
+
+/**
+ * Enumeration for em fkb
+ */
+enum cfa_p70_em_fkb_flds {
+ CFA_P70_EM_FKB_PROF_ID_FLD = 0,
+ CFA_P70_EM_FKB_L2CTXT_FLD = 1,
+ CFA_P70_EM_FKB_L2FUNC_FLD = 2,
+ CFA_P70_EM_FKB_PARIF_FLD = 3,
+ CFA_P70_EM_FKB_SPIF_FLD = 4,
+ CFA_P70_EM_FKB_SVIF_FLD = 5,
+ CFA_P70_EM_FKB_LCOS_FLD = 6,
+ CFA_P70_EM_FKB_META_HI_FLD = 7,
+ CFA_P70_EM_FKB_META_LO_FLD = 8,
+ CFA_P70_EM_FKB_RCYC_CNT_FLD = 9,
+ CFA_P70_EM_FKB_LOOPBACK_FLD = 10,
+ CFA_P70_EM_FKB_OTL2_TYPE_FLD = 11,
+ CFA_P70_EM_FKB_OTL2_DMAC_FLD = 12,
+ CFA_P70_EM_FKB_OTL2_SMAC_FLD = 13,
+ CFA_P70_EM_FKB_OTL2_DT_FLD = 14,
+ CFA_P70_EM_FKB_OTL2_SA_FLD = 15,
+ CFA_P70_EM_FKB_OTL2_NVT_FLD = 16,
+ CFA_P70_EM_FKB_OTL2_OVP_FLD = 17,
+ CFA_P70_EM_FKB_OTL2_OVD_FLD = 18,
+ CFA_P70_EM_FKB_OTL2_OVV_FLD = 19,
+ CFA_P70_EM_FKB_OTL2_OVT_FLD = 20,
+ CFA_P70_EM_FKB_OTL2_IVP_FLD = 21,
+ CFA_P70_EM_FKB_OTL2_IVD_FLD = 22,
+ CFA_P70_EM_FKB_OTL2_IVV_FLD = 23,
+ CFA_P70_EM_FKB_OTL2_IVT_FLD = 24,
+ CFA_P70_EM_FKB_OTL2_ETYPE_FLD = 25,
+ CFA_P70_EM_FKB_OTL3_TYPE_FLD = 26,
+ CFA_P70_EM_FKB_OTL3_SIP3_FLD = 27,
+ CFA_P70_EM_FKB_OTL3_SIP2_FLD = 28,
+ CFA_P70_EM_FKB_OTL3_SIP1_FLD = 29,
+ CFA_P70_EM_FKB_OTL3_SIP0_FLD = 30,
+ CFA_P70_EM_FKB_OTL3_DIP3_FLD = 31,
+ CFA_P70_EM_FKB_OTL3_DIP2_FLD = 32,
+ CFA_P70_EM_FKB_OTL3_DIP1_FLD = 33,
+ CFA_P70_EM_FKB_OTL3_DIP0_FLD = 34,
+ CFA_P70_EM_FKB_OTL3_TTL_FLD = 35,
+ CFA_P70_EM_FKB_OTL3_PROT_FLD = 36,
+ CFA_P70_EM_FKB_OTL3_FID_FLD = 37,
+ CFA_P70_EM_FKB_OTL3_QOS_FLD = 38,
+ CFA_P70_EM_FKB_OTL3_IEH_NONEXT_FLD = 39,
+ CFA_P70_EM_FKB_OTL3_IEH_SEP_FLD = 40,
+ CFA_P70_EM_FKB_OTL3_IEH_AUTH_FLD = 41,
+ CFA_P70_EM_FKB_OTL3_IEH_DEST_FLD = 42,
+ CFA_P70_EM_FKB_OTL3_IEH_FRAG_FLD = 43,
+ CFA_P70_EM_FKB_OTL3_IEH_RTHDR_FLD = 44,
+ CFA_P70_EM_FKB_OTL3_IEH_HOP_FLD = 45,
+ CFA_P70_EM_FKB_OTL3_IEH_1FRAG_FLD = 46,
+ CFA_P70_EM_FKB_OTL3_DF_FLD = 47,
+ CFA_P70_EM_FKB_OTL3_L3ERR_FLD = 48,
+ CFA_P70_EM_FKB_OTL4_TYPE_FLD = 49,
+ CFA_P70_EM_FKB_OTL4_SRC_FLD = 50,
+ CFA_P70_EM_FKB_OTL4_DST_FLD = 51,
+ CFA_P70_EM_FKB_OTL4_FLAGS_FLD = 52,
+ CFA_P70_EM_FKB_OTL4_SEQ_FLD = 53,
+ CFA_P70_EM_FKB_OTL4_PA_FLD = 54,
+ CFA_P70_EM_FKB_OTL4_OPT_FLD = 55,
+ CFA_P70_EM_FKB_OTL4_TCPTS_FLD = 56,
+ CFA_P70_EM_FKB_OTL4_ERR_FLD = 57,
+ CFA_P70_EM_FKB_OT_TYPE_FLD = 58,
+ CFA_P70_EM_FKB_OT_FLAGS_FLD = 59,
+ CFA_P70_EM_FKB_OT_IDS_FLD = 60,
+ CFA_P70_EM_FKB_OT_ID_FLD = 61,
+ CFA_P70_EM_FKB_OT_CTXTS_FLD = 62,
+ CFA_P70_EM_FKB_OT_CTXT_FLD = 63,
+ CFA_P70_EM_FKB_OT_QOS_FLD = 64,
+ CFA_P70_EM_FKB_OT_ERR_FLD = 65,
+ CFA_P70_EM_FKB_TL2_TYPE_FLD = 66,
+ CFA_P70_EM_FKB_TL2_DMAC_FLD = 67,
+ CFA_P70_EM_FKB_TL2_SMAC_FLD = 68,
+ CFA_P70_EM_FKB_TL2_DT_FLD = 69,
+ CFA_P70_EM_FKB_TL2_SA_FLD = 70,
+ CFA_P70_EM_FKB_TL2_NVT_FLD = 71,
+ CFA_P70_EM_FKB_TL2_OVP_FLD = 72,
+ CFA_P70_EM_FKB_TL2_OVD_FLD = 73,
+ CFA_P70_EM_FKB_TL2_OVV_FLD = 74,
+ CFA_P70_EM_FKB_TL2_OVT_FLD = 75,
+ CFA_P70_EM_FKB_TL2_IVP_FLD = 76,
+ CFA_P70_EM_FKB_TL2_IVD_FLD = 77,
+ CFA_P70_EM_FKB_TL2_IVV_FLD = 78,
+ CFA_P70_EM_FKB_TL2_IVT_FLD = 79,
+ CFA_P70_EM_FKB_TL2_ETYPE_FLD = 80,
+ CFA_P70_EM_FKB_TL3_TYPE_FLD = 81,
+ CFA_P70_EM_FKB_TL3_SIP3_FLD = 82,
+ CFA_P70_EM_FKB_TL3_SIP2_FLD = 83,
+ CFA_P70_EM_FKB_TL3_SIP1_FLD = 84,
+ CFA_P70_EM_FKB_TL3_SIP0_FLD = 85,
+ CFA_P70_EM_FKB_TL3_DIP3_FLD = 86,
+ CFA_P70_EM_FKB_TL3_DIP2_FLD = 87,
+ CFA_P70_EM_FKB_TL3_DIP1_FLD = 88,
+ CFA_P70_EM_FKB_TL3_DIP0_FLD = 89,
+ CFA_P70_EM_FKB_TL3_TTL_FLD = 90,
+ CFA_P70_EM_FKB_TL3_PROT_FLD = 91,
+ CFA_P70_EM_FKB_TL3_FID_FLD = 92,
+ CFA_P70_EM_FKB_TL3_QOS_FLD = 93,
+ CFA_P70_EM_FKB_TL3_IEH_NONEXT_FLD = 94,
+ CFA_P70_EM_FKB_TL3_IEH_SEP_FLD = 95,
+ CFA_P70_EM_FKB_TL3_IEH_AUTH_FLD = 96,
+ CFA_P70_EM_FKB_TL3_IEH_DEST_FLD = 97,
+ CFA_P70_EM_FKB_TL3_IEH_FRAG_FLD = 98,
+ CFA_P70_EM_FKB_TL3_IEH_RTHDR_FLD = 99,
+ CFA_P70_EM_FKB_TL3_IEH_HOP_FLD = 100,
+ CFA_P70_EM_FKB_TL3_IEH_1FRAG_FLD = 101,
+ CFA_P70_EM_FKB_TL3_DF_FLD = 102,
+ CFA_P70_EM_FKB_TL3_L3ERR_FLD = 103,
+ CFA_P70_EM_FKB_TL4_TYPE_FLD = 104,
+ CFA_P70_EM_FKB_TL4_SRC_FLD = 105,
+ CFA_P70_EM_FKB_TL4_DST_FLD = 106,
+ CFA_P70_EM_FKB_TL4_FLAGS_FLD = 107,
+ CFA_P70_EM_FKB_TL4_SEQ_FLD = 108,
+ CFA_P70_EM_FKB_TL4_PA_FLD = 109,
+ CFA_P70_EM_FKB_TL4_OPT_FLD = 110,
+ CFA_P70_EM_FKB_TL4_TCPTS_FLD = 111,
+ CFA_P70_EM_FKB_TL4_ERR_FLD = 112,
+ CFA_P70_EM_FKB_T_TYPE_FLD = 113,
+ CFA_P70_EM_FKB_T_FLAGS_FLD = 114,
+ CFA_P70_EM_FKB_T_IDS_FLD = 115,
+ CFA_P70_EM_FKB_T_ID_FLD = 116,
+ CFA_P70_EM_FKB_T_CTXTS_FLD = 117,
+ CFA_P70_EM_FKB_T_CTXT_FLD = 118,
+ CFA_P70_EM_FKB_T_QOS_FLD = 119,
+ CFA_P70_EM_FKB_T_ERR_FLD = 120,
+ CFA_P70_EM_FKB_L2_TYPE_FLD = 121,
+ CFA_P70_EM_FKB_L2_DMAC_FLD = 122,
+ CFA_P70_EM_FKB_L2_SMAC_FLD = 123,
+ CFA_P70_EM_FKB_L2_DT_FLD = 124,
+ CFA_P70_EM_FKB_L2_SA_FLD = 125,
+ CFA_P70_EM_FKB_L2_NVT_FLD = 126,
+ CFA_P70_EM_FKB_L2_OVP_FLD = 127,
+ CFA_P70_EM_FKB_L2_OVD_FLD = 128,
+ CFA_P70_EM_FKB_L2_OVV_FLD = 129,
+ CFA_P70_EM_FKB_L2_OVT_FLD = 130,
+ CFA_P70_EM_FKB_L2_IVP_FLD = 131,
+ CFA_P70_EM_FKB_L2_IVD_FLD = 132,
+ CFA_P70_EM_FKB_L2_IVV_FLD = 133,
+ CFA_P70_EM_FKB_L2_IVT_FLD = 134,
+ CFA_P70_EM_FKB_L2_ETYPE_FLD = 135,
+ CFA_P70_EM_FKB_L3_TYPE_FLD = 136,
+ CFA_P70_EM_FKB_L3_SIP3_FLD = 137,
+ CFA_P70_EM_FKB_L3_SIP2_FLD = 138,
+ CFA_P70_EM_FKB_L3_SIP1_FLD = 139,
+ CFA_P70_EM_FKB_L3_SIP0_FLD = 140,
+ CFA_P70_EM_FKB_L3_DIP3_FLD = 141,
+ CFA_P70_EM_FKB_L3_DIP2_FLD = 142,
+ CFA_P70_EM_FKB_L3_DIP1_FLD = 143,
+ CFA_P70_EM_FKB_L3_DIP0_FLD = 144,
+ CFA_P70_EM_FKB_L3_TTL_FLD = 145,
+ CFA_P70_EM_FKB_L3_PROT_FLD = 146,
+ CFA_P70_EM_FKB_L3_FID_FLD = 147,
+ CFA_P70_EM_FKB_L3_QOS_FLD = 148,
+ CFA_P70_EM_FKB_L3_IEH_NONEXT_FLD = 149,
+ CFA_P70_EM_FKB_L3_IEH_SEP_FLD = 150,
+ CFA_P70_EM_FKB_L3_IEH_AUTH_FLD = 151,
+ CFA_P70_EM_FKB_L3_IEH_DEST_FLD = 152,
+ CFA_P70_EM_FKB_L3_IEH_FRAG_FLD = 153,
+ CFA_P70_EM_FKB_L3_IEH_RTHDR_FLD = 154,
+ CFA_P70_EM_FKB_L3_IEH_HOP_FLD = 155,
+ CFA_P70_EM_FKB_L3_IEH_1FRAG_FLD = 156,
+ CFA_P70_EM_FKB_L3_DF_FLD = 157,
+ CFA_P70_EM_FKB_L3_L3ERR_FLD = 158,
+ CFA_P70_EM_FKB_L4_TYPE_FLD = 159,
+ CFA_P70_EM_FKB_L4_SRC_FLD = 160,
+ CFA_P70_EM_FKB_L4_DST_FLD = 161,
+ CFA_P70_EM_FKB_L4_FLAGS_FLD = 162,
+ CFA_P70_EM_FKB_L4_SEQ_FLD = 163,
+ CFA_P70_EM_FKB_L4_ACK_FLD = 164,
+ CFA_P70_EM_FKB_L4_WIN_FLD = 165,
+ CFA_P70_EM_FKB_L4_PA_FLD = 166,
+ CFA_P70_EM_FKB_L4_OPT_FLD = 167,
+ CFA_P70_EM_FKB_L4_TCPTS_FLD = 168,
+ CFA_P70_EM_FKB_L4_TSVAL_FLD = 169,
+ CFA_P70_EM_FKB_L4_TXECR_FLD = 170,
+ CFA_P70_EM_FKB_L4_ERR_FLD = 171,
+ CFA_P70_EM_FKB_MAX_FLD = 172,
+};
+
+/**
+ * Enumeration for em key layout
+ */
+enum cfa_p70_em_key_layout_flds {
+ CFA_P70_EM_KL_RANGE_IDX_FLD = 0,
+ CFA_P70_EM_KL_RANGE_PROFILE_FLD = 1,
+ CFA_P70_EM_KL_CREC_TIMER_VALUE_FLD = 2,
+ CFA_P70_EM_KL_CREC_STATE_FLD = 3,
+ CFA_P70_EM_KL_CREC_TCP_MSB_OPP_INIT_FLD = 4,
+ CFA_P70_EM_KL_CREC_TCP_MSB_OPP_FLD = 5,
+ CFA_P70_EM_KL_CREC_TCP_MSB_LOC_FLD = 6,
+ CFA_P70_EM_KL_CREC_TCP_WIN_FLD = 7,
+ CFA_P70_EM_KL_CREC_TCP_UPDT_EN_FLD = 8,
+ CFA_P70_EM_KL_CREC_TCP_DIR_FLD = 9,
+ CFA_P70_EM_KL_METADATA_FLD = 10,
+ CFA_P70_EM_KL_PROF_FUNC_FLD = 11,
+ CFA_P70_EM_KL_META_PROF_FLD = 12,
+ CFA_P70_EM_KL_RECYCLE_DEST_FLD = 13,
+ CFA_P70_EM_KL_FC_PTR_FLD = 14,
+ CFA_P70_EM_KL_FC_TYPE_FLD = 15,
+ CFA_P70_EM_KL_FC_OP_FLD = 16,
+ CFA_P70_EM_KL_PATHS_M1_FLD = 17,
+ CFA_P70_EM_KL_ACT_REC_SIZE_FLD = 18,
+ CFA_P70_EM_KL_RING_TABLE_IDX_FLD = 19,
+ CFA_P70_EM_KL_DESTINATION_FLD = 20,
+ CFA_P70_EM_KL_ACT_REC_PTR_FLD = 21,
+ CFA_P70_EM_KL_ACT_HINT_FLD = 22,
+ CFA_P70_EM_KL_STRENGTH_FLD = 23,
+ CFA_P70_EM_KL_OPCODE_FLD = 24,
+ CFA_P70_EM_KL_EPOCH1_FLD = 25,
+ CFA_P70_EM_KL_EPOCH0_FLD = 26,
+ CFA_P70_EM_KL_REC_SIZE_FLD = 27,
+ CFA_P70_EM_KL_VALID_FLD = 28,
+ CFA_P70_EM_KL_PROF_ID_FLD = 29,
+ CFA_P70_EM_KL_L2CTXT_FLD = 30,
+ CFA_P70_EM_KL_L2FUNC_FLD = 31,
+ CFA_P70_EM_KL_PARIF_FLD = 32,
+ CFA_P70_EM_KL_SPIF_FLD = 33,
+ CFA_P70_EM_KL_SVIF_FLD = 34,
+ CFA_P70_EM_KL_LCOS_FLD = 35,
+ CFA_P70_EM_KL_META_HI_FLD = 36,
+ CFA_P70_EM_KL_META_LO_FLD = 37,
+ CFA_P70_EM_KL_RCYC_CNT_FLD = 38,
+ CFA_P70_EM_KL_LOOPBACK_FLD = 39,
+ CFA_P70_EM_KL_OTL2_TYPE_FLD = 40,
+ CFA_P70_EM_KL_OTL2_DMAC_FLD = 41,
+ CFA_P70_EM_KL_OTL2_SMAC_FLD = 42,
+ CFA_P70_EM_KL_OTL2_DT_FLD = 43,
+ CFA_P70_EM_KL_OTL2_SA_FLD = 44,
+ CFA_P70_EM_KL_OTL2_NVT_FLD = 45,
+ CFA_P70_EM_KL_OTL2_OVP_FLD = 46,
+ CFA_P70_EM_KL_OTL2_OVD_FLD = 47,
+ CFA_P70_EM_KL_OTL2_OVV_FLD = 48,
+ CFA_P70_EM_KL_OTL2_OVT_FLD = 49,
+ CFA_P70_EM_KL_OTL2_IVP_FLD = 50,
+ CFA_P70_EM_KL_OTL2_IVD_FLD = 51,
+ CFA_P70_EM_KL_OTL2_IVV_FLD = 52,
+ CFA_P70_EM_KL_OTL2_IVT_FLD = 53,
+ CFA_P70_EM_KL_OTL2_ETYPE_FLD = 54,
+ CFA_P70_EM_KL_OTL3_TYPE_FLD = 55,
+ CFA_P70_EM_KL_OTL3_SIP3_FLD = 56,
+ CFA_P70_EM_KL_OTL3_SIP2_FLD = 57,
+ CFA_P70_EM_KL_OTL3_SIP1_FLD = 58,
+ CFA_P70_EM_KL_OTL3_SIP0_FLD = 59,
+ CFA_P70_EM_KL_OTL3_DIP3_FLD = 60,
+ CFA_P70_EM_KL_OTL3_DIP2_FLD = 61,
+ CFA_P70_EM_KL_OTL3_DIP1_FLD = 62,
+ CFA_P70_EM_KL_OTL3_DIP0_FLD = 63,
+ CFA_P70_EM_KL_OTL3_TTL_FLD = 64,
+ CFA_P70_EM_KL_OTL3_PROT_FLD = 65,
+ CFA_P70_EM_KL_OTL3_FID_FLD = 66,
+ CFA_P70_EM_KL_OTL3_QOS_FLD = 67,
+ CFA_P70_EM_KL_OTL3_IEH_NONEXT_FLD = 68,
+ CFA_P70_EM_KL_OTL3_IEH_SEP_FLD = 69,
+ CFA_P70_EM_KL_OTL3_IEH_AUTH_FLD = 70,
+ CFA_P70_EM_KL_OTL3_IEH_DEST_FLD = 71,
+ CFA_P70_EM_KL_OTL3_IEH_FRAG_FLD = 72,
+ CFA_P70_EM_KL_OTL3_IEH_RTHDR_FLD = 73,
+ CFA_P70_EM_KL_OTL3_IEH_HOP_FLD = 74,
+ CFA_P70_EM_KL_OTL3_IEH_1FRAG_FLD = 75,
+ CFA_P70_EM_KL_OTL3_DF_FLD = 76,
+ CFA_P70_EM_KL_OTL3_L3ERR_FLD = 77,
+ CFA_P70_EM_KL_OTL4_TYPE_FLD = 78,
+ CFA_P70_EM_KL_OTL4_SRC_FLD = 79,
+ CFA_P70_EM_KL_OTL4_DST_FLD = 80,
+ CFA_P70_EM_KL_OTL4_FLAGS_FLD = 81,
+ CFA_P70_EM_KL_OTL4_SEQ_FLD = 82,
+ CFA_P70_EM_KL_OTL4_PA_FLD = 83,
+ CFA_P70_EM_KL_OTL4_OPT_FLD = 84,
+ CFA_P70_EM_KL_OTL4_TCPTS_FLD = 85,
+ CFA_P70_EM_KL_OTL4_ERR_FLD = 86,
+ CFA_P70_EM_KL_OT_TYPE_FLD = 87,
+ CFA_P70_EM_KL_OT_FLAGS_FLD = 88,
+ CFA_P70_EM_KL_OT_IDS_FLD = 89,
+ CFA_P70_EM_KL_OT_ID_FLD = 90,
+ CFA_P70_EM_KL_OT_CTXTS_FLD = 91,
+ CFA_P70_EM_KL_OT_CTXT_FLD = 92,
+ CFA_P70_EM_KL_OT_QOS_FLD = 93,
+ CFA_P70_EM_KL_OT_ERR_FLD = 94,
+ CFA_P70_EM_KL_TL2_TYPE_FLD = 95,
+ CFA_P70_EM_KL_TL2_DMAC_FLD = 96,
+ CFA_P70_EM_KL_TL2_SMAC_FLD = 97,
+ CFA_P70_EM_KL_TL2_DT_FLD = 98,
+ CFA_P70_EM_KL_TL2_SA_FLD = 99,
+ CFA_P70_EM_KL_TL2_NVT_FLD = 100,
+ CFA_P70_EM_KL_TL2_OVP_FLD = 101,
+ CFA_P70_EM_KL_TL2_OVD_FLD = 102,
+ CFA_P70_EM_KL_TL2_OVV_FLD = 103,
+ CFA_P70_EM_KL_TL2_OVT_FLD = 104,
+ CFA_P70_EM_KL_TL2_IVP_FLD = 105,
+ CFA_P70_EM_KL_TL2_IVD_FLD = 106,
+ CFA_P70_EM_KL_TL2_IVV_FLD = 107,
+ CFA_P70_EM_KL_TL2_IVT_FLD = 108,
+ CFA_P70_EM_KL_TL2_ETYPE_FLD = 109,
+ CFA_P70_EM_KL_TL3_TYPE_FLD = 110,
+ CFA_P70_EM_KL_TL3_SIP3_FLD = 111,
+ CFA_P70_EM_KL_TL3_SIP2_FLD = 112,
+ CFA_P70_EM_KL_TL3_SIP1_FLD = 113,
+ CFA_P70_EM_KL_TL3_SIP0_FLD = 114,
+ CFA_P70_EM_KL_TL3_DIP3_FLD = 115,
+ CFA_P70_EM_KL_TL3_DIP2_FLD = 116,
+ CFA_P70_EM_KL_TL3_DIP1_FLD = 117,
+ CFA_P70_EM_KL_TL3_DIP0_FLD = 118,
+ CFA_P70_EM_KL_TL3_TTL_FLD = 119,
+ CFA_P70_EM_KL_TL3_PROT_FLD = 120,
+ CFA_P70_EM_KL_TL3_FID_FLD = 121,
+ CFA_P70_EM_KL_TL3_QOS_FLD = 122,
+ CFA_P70_EM_KL_TL3_IEH_NONEXT_FLD = 123,
+ CFA_P70_EM_KL_TL3_IEH_SEP_FLD = 124,
+ CFA_P70_EM_KL_TL3_IEH_AUTH_FLD = 125,
+ CFA_P70_EM_KL_TL3_IEH_DEST_FLD = 126,
+ CFA_P70_EM_KL_TL3_IEH_FRAG_FLD = 127,
+ CFA_P70_EM_KL_TL3_IEH_RTHDR_FLD = 128,
+ CFA_P70_EM_KL_TL3_IEH_HOP_FLD = 129,
+ CFA_P70_EM_KL_TL3_IEH_1FRAG_FLD = 130,
+ CFA_P70_EM_KL_TL3_DF_FLD = 131,
+ CFA_P70_EM_KL_TL3_L3ERR_FLD = 132,
+ CFA_P70_EM_KL_TL4_TYPE_FLD = 133,
+ CFA_P70_EM_KL_TL4_SRC_FLD = 134,
+ CFA_P70_EM_KL_TL4_DST_FLD = 135,
+ CFA_P70_EM_KL_TL4_FLAGS_FLD = 136,
+ CFA_P70_EM_KL_TL4_SEQ_FLD = 137,
+ CFA_P70_EM_KL_TL4_PA_FLD = 138,
+ CFA_P70_EM_KL_TL4_OPT_FLD = 139,
+ CFA_P70_EM_KL_TL4_TCPTS_FLD = 140,
+ CFA_P70_EM_KL_TL4_ERR_FLD = 141,
+ CFA_P70_EM_KL_T_TYPE_FLD = 142,
+ CFA_P70_EM_KL_T_FLAGS_FLD = 143,
+ CFA_P70_EM_KL_T_IDS_FLD = 144,
+ CFA_P70_EM_KL_T_ID_FLD = 145,
+ CFA_P70_EM_KL_T_CTXTS_FLD = 146,
+ CFA_P70_EM_KL_T_CTXT_FLD = 147,
+ CFA_P70_EM_KL_T_QOS_FLD = 148,
+ CFA_P70_EM_KL_T_ERR_FLD = 149,
+ CFA_P70_EM_KL_L2_TYPE_FLD = 150,
+ CFA_P70_EM_KL_L2_DMAC_FLD = 151,
+ CFA_P70_EM_KL_L2_SMAC_FLD = 152,
+ CFA_P70_EM_KL_L2_DT_FLD = 153,
+ CFA_P70_EM_KL_L2_SA_FLD = 154,
+ CFA_P70_EM_KL_L2_NVT_FLD = 155,
+ CFA_P70_EM_KL_L2_OVP_FLD = 156,
+ CFA_P70_EM_KL_L2_OVD_FLD = 157,
+ CFA_P70_EM_KL_L2_OVV_FLD = 158,
+ CFA_P70_EM_KL_L2_OVT_FLD = 159,
+ CFA_P70_EM_KL_L2_IVP_FLD = 160,
+ CFA_P70_EM_KL_L2_IVD_FLD = 161,
+ CFA_P70_EM_KL_L2_IVV_FLD = 162,
+ CFA_P70_EM_KL_L2_IVT_FLD = 163,
+ CFA_P70_EM_KL_L2_ETYPE_FLD = 164,
+ CFA_P70_EM_KL_L3_TYPE_FLD = 165,
+ CFA_P70_EM_KL_L3_SIP3_FLD = 166,
+ CFA_P70_EM_KL_L3_SIP2_FLD = 167,
+ CFA_P70_EM_KL_L3_SIP1_FLD = 168,
+ CFA_P70_EM_KL_L3_SIP0_FLD = 169,
+ CFA_P70_EM_KL_L3_DIP3_FLD = 170,
+ CFA_P70_EM_KL_L3_DIP2_FLD = 171,
+ CFA_P70_EM_KL_L3_DIP1_FLD = 172,
+ CFA_P70_EM_KL_L3_DIP0_FLD = 173,
+ CFA_P70_EM_KL_L3_TTL_FLD = 174,
+ CFA_P70_EM_KL_L3_PROT_FLD = 175,
+ CFA_P70_EM_KL_L3_FID_FLD = 176,
+ CFA_P70_EM_KL_L3_QOS_FLD = 177,
+ CFA_P70_EM_KL_L3_IEH_NONEXT_FLD = 178,
+ CFA_P70_EM_KL_L3_IEH_SEP_FLD = 179,
+ CFA_P70_EM_KL_L3_IEH_AUTH_FLD = 180,
+ CFA_P70_EM_KL_L3_IEH_DEST_FLD = 181,
+ CFA_P70_EM_KL_L3_IEH_FRAG_FLD = 182,
+ CFA_P70_EM_KL_L3_IEH_RTHDR_FLD = 183,
+ CFA_P70_EM_KL_L3_IEH_HOP_FLD = 184,
+ CFA_P70_EM_KL_L3_IEH_1FRAG_FLD = 185,
+ CFA_P70_EM_KL_L3_DF_FLD = 186,
+ CFA_P70_EM_KL_L3_L3ERR_FLD = 187,
+ CFA_P70_EM_KL_L4_TYPE_FLD = 188,
+ CFA_P70_EM_KL_L4_SRC_FLD = 189,
+ CFA_P70_EM_KL_L4_DST_FLD = 190,
+ CFA_P70_EM_KL_L4_FLAGS_FLD = 191,
+ CFA_P70_EM_KL_L4_SEQ_FLD = 192,
+ CFA_P70_EM_KL_L4_ACK_FLD = 193,
+ CFA_P70_EM_KL_L4_WIN_FLD = 194,
+ CFA_P70_EM_KL_L4_PA_FLD = 195,
+ CFA_P70_EM_KL_L4_OPT_FLD = 196,
+ CFA_P70_EM_KL_L4_TCPTS_FLD = 197,
+ CFA_P70_EM_KL_L4_TSVAL_FLD = 198,
+ CFA_P70_EM_KL_L4_TXECR_FLD = 199,
+ CFA_P70_EM_KL_L4_ERR_FLD = 200,
+ CFA_P70_EM_KEY_LAYOUT_MAX_FLD = 201,
+ CFA_P70_EM_KL_MAX_FLD = CFA_P70_EM_KEY_LAYOUT_MAX_FLD,
+};
+
+/**
+ * Enumeration for action
+ */
+enum cfa_p70_action_flds {
+ CFA_P70_ACT_TYPE_FLD = 0,
+ CFA_P70_ACT_DROP_FLD = 1,
+ CFA_P70_ACT_VLAN_DELETE_FLD = 2,
+ CFA_P70_ACT_DEST_FLD = 3,
+ CFA_P70_ACT_DEST_OP_FLD = 4,
+ CFA_P70_ACT_DECAP_FLD = 5,
+ CFA_P70_ACT_MIRRORING_FLD = 6,
+ CFA_P70_ACT_METER_PTR_FLD = 7,
+ CFA_P70_ACT_STAT0_OFF_FLD = 8,
+ CFA_P70_ACT_STAT0_OP_FLD = 9,
+ CFA_P70_ACT_STAT0_CTR_TYPE_FLD = 10,
+ CFA_P70_ACT_MOD_OFF_FLD = 11,
+ CFA_P70_ACT_ENC_OFF_FLD = 12,
+ CFA_P70_ACT_SRC_OFF_FLD = 13,
+ CFA_P70_ACT_COMPACT_RSVD_0_FLD = 14,
+ CFA_P70_ACT_STAT0_PTR_FLD = 15,
+ CFA_P70_ACT_STAT1_PTR_FLD = 16,
+ CFA_P70_ACT_STAT1_OP_FLD = 17,
+ CFA_P70_ACT_STAT1_CTR_TYPE_FLD = 18,
+ CFA_P70_ACT_MOD_PTR_FLD = 19,
+ CFA_P70_ACT_ENC_PTR_FLD = 20,
+ CFA_P70_ACT_SRC_PTR_FLD = 21,
+ CFA_P70_ACT_FULL_RSVD_0_FLD = 22,
+ CFA_P70_ACT_SRC_KO_EN_FLD = 23,
+ CFA_P70_ACT_MCG_RSVD_0_FLD = 24,
+ CFA_P70_ACT_NEXT_PTR_FLD = 25,
+ CFA_P70_ACT_PTR0_ACT_HINT_FLD = 26,
+ CFA_P70_ACT_PTR0_ACT_REC_PTR_FLD = 27,
+ CFA_P70_ACT_PTR1_ACT_HINT_FLD = 28,
+ CFA_P70_ACT_PTR1_ACT_REC_PTR_FLD = 29,
+ CFA_P70_ACT_PTR2_ACT_HINT_FLD = 30,
+ CFA_P70_ACT_PTR2_ACT_REC_PTR_FLD = 31,
+ CFA_P70_ACT_PTR3_ACT_HINT_FLD = 32,
+ CFA_P70_ACT_PTR3_ACT_REC_PTR_FLD = 33,
+ CFA_P70_ACT_PTR4_ACT_HINT_FLD = 34,
+ CFA_P70_ACT_PTR4_ACT_REC_PTR_FLD = 35,
+ CFA_P70_ACT_PTR5_ACT_HINT_FLD = 36,
+ CFA_P70_ACT_PTR5_ACT_REC_PTR_FLD = 37,
+ CFA_P70_ACT_PTR6_ACT_HINT_FLD = 38,
+ CFA_P70_ACT_PTR6_ACT_REC_PTR_FLD = 39,
+ CFA_P70_ACT_PTR7_ACT_HINT_FLD = 40,
+ CFA_P70_ACT_PTR7_ACT_REC_PTR_FLD = 41,
+ CFA_P70_ACT_MCG_SUBSEQ_RSVD_0_FLD = 42,
+ CFA_P70_ACT_MOD_MODIFY_ACT_HDR_FLD = 43,
+ CFA_P70_ACT_MOD_MD_UPDT_DATA_FLD = 44,
+ CFA_P70_ACT_MOD_MD_UPDT_PROF_FLD = 45,
+ CFA_P70_ACT_MOD_MD_UPDT_OP_FLD = 46,
+ CFA_P70_ACT_MOD_MD_UPDT_RSVD_0_FLD = 47,
+ CFA_P70_ACT_MOD_MD_UPDT_TOP_FLD = 48,
+ CFA_P70_ACT_MOD_RM_OVLAN_FLD = 49,
+ CFA_P70_ACT_MOD_RM_IVLAN_FLD = 50,
+ CFA_P70_ACT_MOD_RPL_IVLAN_FLD = 51,
+ CFA_P70_ACT_MOD_RPL_OVLAN_FLD = 52,
+ CFA_P70_ACT_MOD_TTL_UPDT_OP_FLD = 53,
+ CFA_P70_ACT_MOD_TTL_UPDT_ALT_VID_FLD = 54,
+ CFA_P70_ACT_MOD_TTL_UPDT_ALT_PFID_FLD = 55,
+ CFA_P70_ACT_MOD_TTL_UPDT_TOP_FLD = 56,
+ CFA_P70_ACT_MOD_TNL_MODIFY_DEL_FLD = 57,
+ CFA_P70_ACT_MOD_TNL_MODIFY_8B_NEW_PROT_FLD = 58,
+ CFA_P70_ACT_MOD_TNL_MODIFY_8B_EXIST_PROT_FLD = 59,
+ CFA_P70_ACT_MOD_TNL_MODIFY_8B_VEC_FLD = 60,
+ CFA_P70_ACT_MOD_TNL_MODIFY_8B_TOP_FLD = 61,
+ CFA_P70_ACT_MOD_TNL_MODIFY_16B_NEW_PROT_FLD = 62,
+ CFA_P70_ACT_MOD_TNL_MODIFY_16B_EXIST_PROT_FLD = 63,
+ CFA_P70_ACT_MOD_TNL_MODIFY_16B_VEC_FLD = 64,
+ CFA_P70_ACT_MOD_TNL_MODIFY_16B_TOP_FLD = 65,
+ CFA_P70_ACT_MOD_UPDT_FIELD_DATA0_FLD = 66,
+ CFA_P70_ACT_MOD_UPDT_FIELD_VEC_RSVD_FLD = 67,
+ CFA_P70_ACT_MOD_UPDT_FIELD_VEC_KID_FLD = 68,
+ CFA_P70_ACT_MOD_UPDT_FIELD_TOP_FLD = 69,
+ CFA_P70_ACT_MOD_SMAC_FLD = 70,
+ CFA_P70_ACT_MOD_DMAC_FLD = 71,
+ CFA_P70_ACT_MOD_SIPV6_FLD = 72,
+ CFA_P70_ACT_MOD_DIPV6_FLD = 73,
+ CFA_P70_ACT_MOD_SIPV4_FLD = 74,
+ CFA_P70_ACT_MOD_DIPV4_FLD = 75,
+ CFA_P70_ACT_MOD_SPORT_FLD = 76,
+ CFA_P70_ACT_MOD_DPORT_FLD = 77,
+ CFA_P70_ACT_ENC_ECV_TNL_FLD = 78,
+ CFA_P70_ACT_ENC_ECV_L4_FLD = 79,
+ CFA_P70_ACT_ENC_ECV_L3_FLD = 80,
+ CFA_P70_ACT_ENC_ECV_L2_FLD = 81,
+ CFA_P70_ACT_ENC_ECV_VTAG_FLD = 82,
+ CFA_P70_ACT_ENC_ECV_EC_FLD = 83,
+ CFA_P70_ACT_ENC_ECV_VALID_FLD = 84,
+ CFA_P70_ACT_ENC_EC_IP_TTL_IH_FLD = 85,
+ CFA_P70_ACT_ENC_EC_IP_TOS_IH_FLD = 86,
+ CFA_P70_ACT_ENC_EC_TUN_QOS_FLD = 87,
+ CFA_P70_ACT_ENC_EC_GRE_SET_K_FLD = 88,
+ CFA_P70_ACT_ENC_EC_DMAC_OVR_FLD = 89,
+ CFA_P70_ACT_ENC_EC_VLAN_OVR_FLD = 90,
+ CFA_P70_ACT_ENC_EC_SMAC_OVR_FLD = 91,
+ CFA_P70_ACT_ENC_EC_IPV4_ID_CTRL_FLD = 92,
+ CFA_P70_ACT_ENC_L2_DMAC_FLD = 93,
+ CFA_P70_ACT_ENC_VLAN1_TAG_VID_FLD = 94,
+ CFA_P70_ACT_ENC_VLAN1_TAG_DE_FLD = 95,
+ CFA_P70_ACT_ENC_VLAN1_TAG_PRI_FLD = 96,
+ CFA_P70_ACT_ENC_VLAN1_TAG_TPID_FLD = 97,
+ CFA_P70_ACT_ENC_VLAN2_IT_VID_FLD = 98,
+ CFA_P70_ACT_ENC_VLAN2_IT_DE_FLD = 99,
+ CFA_P70_ACT_ENC_VLAN2_IT_PRI_FLD = 100,
+ CFA_P70_ACT_ENC_VLAN2_IT_TPID_FLD = 101,
+ CFA_P70_ACT_ENC_VLAN2_OT_VID_FLD = 102,
+ CFA_P70_ACT_ENC_VLAN2_OT_DE_FLD = 103,
+ CFA_P70_ACT_ENC_VLAN2_OT_PRI_FLD = 104,
+ CFA_P70_ACT_ENC_VLAN2_OT_TPID_FLD = 105,
+ CFA_P70_ACT_ENC_IPV4_ID_FLD = 106,
+ CFA_P70_ACT_ENC_IPV4_TOS_FLD = 107,
+ CFA_P70_ACT_ENC_IPV4_HLEN_FLD = 108,
+ CFA_P70_ACT_ENC_IPV4_VER_FLD = 109,
+ CFA_P70_ACT_ENC_IPV4_PROT_FLD = 110,
+ CFA_P70_ACT_ENC_IPV4_TTL_FLD = 111,
+ CFA_P70_ACT_ENC_IPV4_FRAG_FLD = 112,
+ CFA_P70_ACT_ENC_IPV4_FLAGS_FLD = 113,
+ CFA_P70_ACT_ENC_IPV4_DEST_FLD = 114,
+ CFA_P70_ACT_ENC_IPV6_FLOW_LABEL_FLD = 115,
+ CFA_P70_ACT_ENC_IPV6_TRAFFIC_CLASS_FLD = 116,
+ CFA_P70_ACT_ENC_IPV6_VER_FLD = 117,
+ CFA_P70_ACT_ENC_IPV6_HOP_LIMIT_FLD = 118,
+ CFA_P70_ACT_ENC_IPV6_NEXT_HEADER_FLD = 119,
+ CFA_P70_ACT_ENC_IPV6_PAYLOAD_LENGTH_FLD = 120,
+ CFA_P70_ACT_ENC_IPV6_DEST_FLD = 121,
+ CFA_P70_ACT_ENC_MPLS_TAG1_FLD = 122,
+ CFA_P70_ACT_ENC_MPLS_TAG2_FLD = 123,
+ CFA_P70_ACT_ENC_MPLS_TAG3_FLD = 124,
+ CFA_P70_ACT_ENC_MPLS_TAG4_FLD = 125,
+ CFA_P70_ACT_ENC_MPLS_TAG5_FLD = 126,
+ CFA_P70_ACT_ENC_MPLS_TAG6_FLD = 127,
+ CFA_P70_ACT_ENC_MPLS_TAG7_FLD = 128,
+ CFA_P70_ACT_ENC_MPLS_TAG8_FLD = 129,
+ CFA_P70_ACT_ENC_L4_DEST_PORT_FLD = 130,
+ CFA_P70_ACT_ENC_L4_SRC_PORT_FLD = 131,
+ CFA_P70_ACT_ENC_TNL_VXLAN_NEXT_PROT_FLD = 132,
+ CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_0_FLD = 133,
+ CFA_P70_ACT_ENC_TNL_VXLAN_FLAGS_FLD = 134,
+ CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_1_FLD = 135,
+ CFA_P70_ACT_ENC_TNL_VXLAN_VNI_FLD = 136,
+ CFA_P70_ACT_ENC_TNL_NGE_PROT_TYPE_FLD = 137,
+ CFA_P70_ACT_ENC_TNL_NGE_RSVD_0_FLD = 138,
+ CFA_P70_ACT_ENC_TNL_NGE_FLAGS_C_FLD = 139,
+ CFA_P70_ACT_ENC_TNL_NGE_FLAGS_O_FLD = 140,
+ CFA_P70_ACT_ENC_TNL_NGE_FLAGS_OPT_LEN_FLD = 141,
+ CFA_P70_ACT_ENC_TNL_NGE_FLAGS_VER_FLD = 142,
+ CFA_P70_ACT_ENC_TNL_NGE_RSVD_1_FLD = 143,
+ CFA_P70_ACT_ENC_TNL_NGE_VNI_FLD = 144,
+ CFA_P70_ACT_ENC_TNL_NGE_OPTIONS_FLD = 145,
+ CFA_P70_ACT_ENC_TNL_NVGRE_FLOW_ID_FLD = 146,
+ CFA_P70_ACT_ENC_TNL_NVGRE_VSID_FLD = 147,
+ CFA_P70_ACT_ENC_TNL_GRE_KEY_FLD = 148,
+ CFA_P70_ACT_ENC_TNL_GENERIC_TID_FLD = 149,
+ CFA_P70_ACT_ENC_TNL_GENERIC_LENGTH_FLD = 150,
+ CFA_P70_ACT_ENC_TNL_GENERIC_HEADER_FLD = 151,
+ CFA_P70_ACT_SRC_MAC_FLD = 152,
+ CFA_P70_ACT_SRC_IPV4_ADDR_FLD = 153,
+ CFA_P70_ACT_SRC_IPV6_ADDR_FLD = 154,
+ CFA_P70_ACT_STAT0_B16_FPC_FLD = 155,
+ CFA_P70_ACT_STAT1_B16_FPC_FLD = 156,
+ CFA_P70_ACT_STAT0_B16_FBC_FLD = 157,
+ CFA_P70_ACT_STAT1_B16_FBC_FLD = 158,
+ CFA_P70_ACT_STAT0_B24_FPC_FLD = 159,
+ CFA_P70_ACT_STAT1_B24_FPC_FLD = 160,
+ CFA_P70_ACT_STAT0_B24_FBC_FLD = 161,
+ CFA_P70_ACT_STAT1_B24_FBC_FLD = 162,
+ CFA_P70_ACT_STAT0_B24_TIMESTAMP_FLD = 163,
+ CFA_P70_ACT_STAT1_B24_TIMESTAMP_FLD = 164,
+ CFA_P70_ACT_STAT0_B24_TCP_FLAGS_FLD = 165,
+ CFA_P70_ACT_STAT1_B24_TCP_FLAGS_FLD = 166,
+ CFA_P70_ACT_STAT0_B24_UNUSED_0_FLD = 167,
+ CFA_P70_ACT_STAT1_B24_UNUSED_0_FLD = 168,
+ CFA_P70_ACT_STAT0_B32A_FPC_FLD = 169,
+ CFA_P70_ACT_STAT1_B32A_FPC_FLD = 170,
+ CFA_P70_ACT_STAT0_B32A_FBC_FLD = 171,
+ CFA_P70_ACT_STAT1_B32A_FBC_FLD = 172,
+ CFA_P70_ACT_STAT0_B32A_MPC_FLD = 173,
+ CFA_P70_ACT_STAT1_B32A_MPC_FLD = 174,
+ CFA_P70_ACT_STAT0_B32A_MBC_FLD = 175,
+ CFA_P70_ACT_STAT1_B32A_MBC_FLD = 176,
+ CFA_P70_ACT_STAT0_B32B_FPC_FLD = 177,
+ CFA_P70_ACT_STAT1_B32B_FPC_FLD = 178,
+ CFA_P70_ACT_STAT0_B32B_FBC_FLD = 179,
+ CFA_P70_ACT_STAT1_B32B_FBC_FLD = 180,
+ CFA_P70_ACT_STAT0_B32B_TIMESTAMP_FLD = 181,
+ CFA_P70_ACT_STAT1_B32B_TIMESTAMP_FLD = 182,
+ CFA_P70_ACT_STAT0_B32B_TCP_FLAGS_FLD = 183,
+ CFA_P70_ACT_STAT1_B32B_TCP_FLAGS_FLD = 184,
+ CFA_P70_ACT_STAT0_B32B_UNUSED_0_FLD = 185,
+ CFA_P70_ACT_STAT1_B32B_UNUSED_0_FLD = 186,
+ CFA_P70_ACT_STAT0_B32B_MPC15_0_FLD = 187,
+ CFA_P70_ACT_STAT1_B32B_MPC15_0_FLD = 188,
+ CFA_P70_ACT_STAT0_B32B_MPC37_16_FLD = 189,
+ CFA_P70_ACT_STAT1_B32B_MPC37_16_FLD = 190,
+ CFA_P70_ACT_STAT0_B32B_MBC_FLD = 191,
+ CFA_P70_ACT_STAT1_B32B_MBC_FLD = 192,
+ CFA_P70_ACTION_MAX_FLD = 193,
+ CFA_P70_ACT_MAX_FLD = CFA_P70_ACTION_MAX_FLD,
+};
+
+#define CFA_P70_EM_KEY_LAYOUT_2_BASE_FLD(FLD) \
+ ((FLD) - CFA_P70_EM_LREC_MAX_FLD)
+
+/* clang-format on */
+
+#endif /* _CFA_BLD_P70_FIELD_IDS_H_ */
new file mode 100644
@@ -0,0 +1,548 @@
+/****************************************************************************
+ * Copyright(c) 2021 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * @file cfa_bld_p70_mpc.h
+ *
+ * @brief CFA 7.0 Public api definitions to build CFA Mid-path commands and
+ * Parse CFA Mid-path Command completions
+ */
+
+#ifndef _CFA_BLD_P70_MPC_H_
+#define _CFA_BLD_P70_MPC_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * CFA Mid-Path Command (MPC) opcodes. The MPC CFA operations
+ * are divided into 2 sub groups. Cache access operations
+ * and EM update operations.
+ */
+enum cfa_mpc_opcode {
+ /**
+ * MPC Cache access commands
+ */
+ /* MPC Command to read Action/Lookup cache (up to 4 lines) */
+ CFA_MPC_READ,
+ /* MPC Command to write to Action/Lookup cache (up to 4 lines) */
+ CFA_MPC_WRITE,
+ /* MPC Cmd to Read and Clear Action/Lookup cache line (max 1 line) */
+ CFA_MPC_READ_CLR,
+ /* MPC Cmd to Invalidate Action/Lkup cache lines (up to 4 lines) */
+ CFA_MPC_INVALIDATE,
+
+ /**
+ * MPC EM update commands
+ */
+ /**
+ * MPC Command to search for an EM entry by its key in the
+ * EM bucket chain
+ */
+ CFA_MPC_EM_SEARCH,
+ /* MPC command to insert a new EM entry to the EM bucket chain */
+ CFA_MPC_EM_INSERT,
+ /* MPC Command to delete an EM entry from the EM bucket chain */
+ CFA_MPC_EM_DELETE,
+ /* MPC Command to add an EM bucket to the tail of EM bucket chain */
+ CFA_MPC_EM_CHAIN,
+ CFA_MPC_OPC_MAX,
+};
+
+/**
+ * CFA MPC Cache access reading mode
+ */
+enum cfa_mpc_read_mode {
+ CFA_MPC_RD_NORMAL, /**< Normal read mode */
+ CFA_MPC_RD_EVICT, /**< Read the cache and evict the cache line */
+ CFA_MPC_RD_DEBUG_LINE, /**< Debug read mode line */
+ CFA_MPC_RD_DEBUG_TAG, /**< Debug read mode tag */
+ CFA_MPC_RD_MODE_MAX
+};
+
+/**
+ * CFA MPC Cache access writing mode
+ */
+enum cfa_mpc_write_mode {
+ CFA_MPC_WR_WRITE_THRU, /**< Write to cache in Write through mode */
+ CFA_MPC_WR_WRITE_BACK, /**< Write to cache in Write back mode */
+ CFA_MPC_WR_MODE_MAX
+};
+
+/**
+ * CFA MPC Cache access eviction mode
+ */
+enum cfa_mpc_evict_mode {
+ /**
+ * Line evict: These modes evict a single cache line
+ * In these modes, the eviction occurs regardless of the cache line
+ * state (CLEAN/CLEAN_FAST_EVICT/DIRTY)
+ */
+ /* Cache line addressed by set/way is evicted */
+ CFA_MPC_EV_EVICT_LINE,
+ /* Cache line hit with the table scope/address tuple is evicted */
+ CFA_MPC_EV_EVICT_SCOPE_ADDRESS,
+
+ /**
+ * Set Evict: These modes evict cache lines that meet certain criteria
+ * from the entire cache set.
+ */
+ /*
+ * Cache lines only in CLEAN state are evicted from the set
+ * derived from the address
+ */
+ CFA_MPC_EV_EVICT_CLEAN_LINES,
+ /*
+ * Cache lines only in CLEAN_FAST_EVICT state are evicted from
+ * the set derived from the address
+ */
+ CFA_MPC_EV_EVICT_CLEAN_FAST_EVICT_LINES,
+ /*
+ * Cache lines in both CLEAN and CLEAN_FAST_EVICT states are
+ * evicted from the set derived from the address
+ */
+ CFA_MPC_EV_EVICT_CLEAN_AND_CLEAN_FAST_EVICT_LINES,
+ /*
+ * All Cache lines in the set identified by the address and
+ * belonging to the table scope are evicted.
+ */
+ CFA_MPC_EV_EVICT_TABLE_SCOPE,
+ CFA_MPC_EV_MODE_MAX,
+};
+
+/**
+ * CFA Hardware Cache Table Type
+ */
+enum cfa_hw_table_type {
+ CFA_HW_TABLE_ACTION, /**< CFA Action Record Table */
+ CFA_HW_TABLE_LOOKUP, /**< CFA EM Lookup Record Table */
+ CFA_HW_TABLE_MAX
+};
+
+/**
+ * MPC Command parameters specific to Cache read operations
+ */
+struct cfa_mpc_cache_read_params {
+ /* Specifies the cache option for reading the cache lines */
+ enum cfa_mpc_read_mode mode;
+ /**
+ * Clear mask to use for the Read-Clear operation
+ * Each bit in the mask correspond to 2 bytes in the
+ * cache line. Setting the corresponding mask bit, clears
+ * the corresponding data bytes in the cache line AFTER
+ * the read. This field is ignored for Read CMD.
+ */
+ uint16_t clear_mask;
+ /**
+ * External host memory address
+ *
+ * The 64-bit IOVA host address to which to write the DMA data returned
+ * in the completion. The data will be written to the same function as
+ * the one that owns the queue this command is read from. Address must
+ * be 4 byte aligned.
+ */
+ uint64_t host_address;
+};
+
+/**
+ * MPC Command parameters specific to Cache write operation
+ */
+struct cfa_mpc_cache_write_params {
+ /* Specifies the cache option for the write access */
+ enum cfa_mpc_write_mode mode;
+ /* Pointer to data to be written to cache */
+ const uint8_t *data_ptr;
+};
+
+/**
+ * MPC Command parameters specific to Cache evict/invalidate operation
+ */
+struct cfa_mpc_cache_evict_params {
+ /* Specifies the cache option for Invalidation operation */
+ enum cfa_mpc_evict_mode mode;
+};
+
+/**
+ * MPC CFA Command parameters for cache related operations
+ */
+struct cfa_mpc_cache_axs_params {
+ /** Common parameters for cache operations */
+ /*
+ * Opaque value that will be returned in the MPC CFA
+ * Completion message. This can be used by the caller to associate
+ * completions with commands.
+ */
+ uint32_t opaque;
+ /*
+ * Table Scope to address the cache line. For Thor2
+ * the table scope goes for 0 - 31.
+ */
+ uint8_t tbl_scope;
+ /*
+ * Table Index to address the cache line. Note that
+ * this is the offset to the 32B record in the table
+ * scope backing store, expressed in 32B units.
+ */
+ uint32_t tbl_index;
+ /*
+ * Number of cache lines (32B word) in the access
+ * This should be set to 1 for READ-CLEAR command and between 1 and
+ * 4 for all other cache access commands (READ/WRITE/INVALIDATE)
+ */
+ uint8_t data_size;
+ /* CFA table type for which this Host IF hw operation is intended for */
+ enum cfa_hw_table_type tbl_type;
+
+ /* Cache operation specific params */
+ union {
+ /** Read and Read clear specific parameters */
+ struct cfa_mpc_cache_read_params read;
+ /** Cache write specific parameters */
+ struct cfa_mpc_cache_write_params write;
+ /** Cache invalidate operation specific parameters */
+ struct cfa_mpc_cache_evict_params evict;
+ };
+};
+
+/**
+ * MPC CFA command parameters specific to EM insert operation
+ */
+struct cfa_mpc_em_insert_params {
+ /*
+ * Pointer to the Exact Match entry to search. The
+ * EM Key in the entry is used to for the search
+ */
+ const uint8_t *em_entry;
+ /* Size of the EM entry in 32B words (1- 4) */
+ uint8_t data_size;
+ /* Flag to indicate if a matching entry (if found) should be replaced */
+ bool replace;
+ /* Table index to write the EM entry being inserted */
+ uint32_t entry_idx;
+ /*
+ * Table index to the EM record that can be used to
+ * create a new EM bucket, if the insertion results
+ * in a EM bucket chain's tail update.
+ */
+ uint32_t bucket_idx;
+};
+
+/**
+ * MPC CFA command parameters specific to EM search operation
+ */
+struct cfa_mpc_em_search_params {
+ /*
+ * Pointer to the Exact Match entry to search. The
+ * EM Key in the entry is used to for the search
+ */
+ uint8_t *em_entry;
+ /* Size of the EM entry in 32B words (1- 4) */
+ uint8_t data_size;
+};
+
+/**
+ * MPC CFA command parameters specific to EM delete operation
+ */
+struct cfa_mpc_em_delete_params {
+ /* Table index to the EM record to delete */
+ uint32_t entry_idx;
+ /*
+ * Table index to the static bucket for the EM bucket chain.
+ * As part of EM Delete processing, the hw walks the EM bucket
+ * chain to determine if the entry_idx is part of the chain.
+ * If the entry_idx is found to be a part of the chain, it is
+ * deleted from the chain and the EM bucket is repacked. If the
+ * tail of the bucket has only one valid entry, then the delete
+ * operation results in a tail update and one free EM entry
+ */
+ uint32_t bucket_idx;
+};
+
+/**
+ * MPC CFA command parameters specific to EM chain operation
+ */
+struct cfa_mpc_em_chain_params {
+ /*
+ * Table index that will form the chain
+ * pointer to the tail bucket in the EM bucket chain
+ */
+ uint32_t entry_idx;
+ /*
+ * Table index to the static bucket for
+ * EM bucket chain to be updated.
+ */
+ uint32_t bucket_idx;
+};
+
+/**
+ * MPC CFA Command parameters for EM operations
+ */
+struct cfa_mpc_em_op_params {
+ /** Common parameters for EM update operations */
+ /*
+ * Opaque value that will be returned in the MPC CFA
+ * Completion message. This can be used by the caller to associate
+ * completions with commands.
+ */
+ uint32_t opaque;
+ /*
+ * Table Scope to address the cache line. For Thor2
+ * the table scope goes for 0 - 31.
+ */
+ uint8_t tbl_scope;
+ /** EM update operation specific params */
+ union {
+ /** EM Search operation params */
+ struct cfa_mpc_em_search_params search;
+ /** EM Insert operation params */
+ struct cfa_mpc_em_insert_params insert;
+ /** EM Delete operation params */
+ struct cfa_mpc_em_delete_params del;
+ /** EM Chain operation params */
+ struct cfa_mpc_em_chain_params chain;
+ };
+};
+
+/**
+ * MPC CFA Command completion status
+ */
+enum cfa_mpc_cmpl_status {
+ /* Command success */
+ CFA_MPC_OK = 0,
+ /* Unsupported CFA opcode */
+ CFA_MPC_UNSPRT_ERR = 1,
+ /* CFA command format error */
+ CFA_MPC_FMT_ERR = 2,
+ /* SVIF-Table Scope error */
+ CFA_MPC_SCOPE_ERR = 3,
+ /* Address error: Only used if EM command or TABLE_TYPE=EM */
+ CFA_MPC_ADDR_ERR = 4,
+ /* Cache operation error */
+ CFA_MPC_CACHE_ERR = 5,
+ /* EM_SEARCH or EM_DELETE did not find a matching EM entry */
+ CFA_MPC_EM_MISS = 6,
+ /* EM_INSERT found a matching EM entry and REPLACE=0 in the command */
+ CFA_MPC_EM_DUPLICATE = 7,
+ /* EM_EVENT_COLLECTION_FAIL no events to return */
+ CFA_MPC_EM_EVENT_COLLECTION_FAIL = 8,
+ /*
+ * EM_INSERT required a dynamic bucket to be added to the chain
+ * to successfully insert the EM entry, but the entry provided
+ * for use as dynamic bucket was invalid. (bucket_idx == 0)
+ */
+ CFA_MPC_EM_ABORT = 9,
+};
+
+/**
+ * MPC Cache access command completion result
+ */
+struct cfa_mpc_cache_axs_result {
+ /*
+ * Opaque value returned in the completion message. This can
+ * be used by the caller to associate completions with commands.
+ */
+ uint32_t opaque;
+ /* MPC Command completion status code */
+ enum cfa_mpc_cmpl_status status;
+ /*
+ * Additional error information
+ * when status code is one of FMT, SCOPE, ADDR or CACHE error
+ */
+ uint32_t error_data;
+ /*
+ * Pointer to buffer to copy read data to.
+ * Needs to be valid for READ, READ-CLEAR operations
+ * Not set for write and evict operations
+ */
+ uint8_t *rd_data;
+ /*
+ * Size of the data buffer in Bytes. Should be at least
+ * be data_size * 32 for MPC cache reads
+ */
+ uint16_t data_len;
+};
+
+/**
+ * MPC EM search operation result
+ */
+struct cfa_mpc_em_search_result {
+ uint32_t bucket_num; /**< See CFA EAS */
+ uint32_t num_entries; /**< See CFA EAS */
+ /* Set to HASH[35:24] of the hash computed from the EM entry key. */
+ uint32_t hash_msb;
+ /*
+ * IF a match is found, this field is set
+ * to the table index of the matching EM entry
+ */
+ uint32_t match_idx;
+ /*
+ * Table index to the static bucket determined by hashing the EM entry
+ * key
+ */
+ uint32_t bucket_idx;
+};
+
+/**
+ * MPC EM insert operation result
+ */
+struct cfa_mpc_em_insert_result {
+ uint32_t bucket_num; /**< See CFA EAS */
+ uint32_t num_entries; /**< See CFA EAS */
+ /* Set to HASH[35:24] of the hash computed from the EM entry key. */
+ uint32_t hash_msb;
+ /*
+ * If replace = 1 and a matchng entry is found, this field is
+ * updated with the table index of the replaced entry. This table
+ * index is therefore free for use.
+ */
+ uint32_t match_idx;
+ /*
+ * Table index to the static bucket determined by hashing the EM entry
+ * key
+ */
+ uint32_t bucket_idx;
+ /* Flag: Matching entry was found and replace */
+ uint8_t replaced : 1;
+ /* Flag: EM bucket chain was updated */
+ uint8_t chain_update : 1;
+};
+
+/**
+ * MPC EM delete operation result
+ */
+struct cfa_mpc_em_delete_result {
+ uint32_t bucket_num; /**< See CFA EAS */
+ uint32_t num_entries; /**< See CFA EAS */
+ /*
+ * Table index to EM bucket tail BEFORE the delete command
+ * was processed with a OK or EM_MISS status. If chain update = 1, then
+ * this bucket can be freed
+ */
+ uint32_t prev_tail;
+ /*
+ * Table index to EM bucket tail AFTER the delete command
+ * was processed with a OK or EM_MISS status. Same as prev_tail
+ * if chain_update = 0.
+ */
+ uint32_t new_tail;
+ /* Flag: EM bucket chain was updated */
+ uint8_t chain_update : 1;
+};
+
+/**
+ * MPC EM chain operation result
+ */
+struct cfa_mpc_em_chain_result {
+ uint32_t bucket_num; /**< See CFA EAS */
+ uint32_t num_entries; /**< See CFA EAS */
+};
+
+/**
+ * MPC EM operation completion result
+ */
+struct cfa_mpc_em_op_result {
+ /*
+ * Opaque value returned in the completion message. This can
+ * be used by the caller to associate completions with commands.
+ */
+ uint32_t opaque;
+ /* MPC Command completion status code */
+ enum cfa_mpc_cmpl_status status;
+ /*
+ * Additional error information
+ * when status code is one of FMT, SCOPE, ADDR or CACHE error
+ */
+ uint32_t error_data;
+ union {
+ /** EM Search specific results */
+ struct cfa_mpc_em_search_result search;
+ /** EM Insert specific results */
+ struct cfa_mpc_em_insert_result insert;
+ /** EM Delete specific results */
+ struct cfa_mpc_em_delete_result del;
+ /** EM Chain specific results */
+ struct cfa_mpc_em_chain_result chain;
+ };
+};
+
+/**
+ * Build MPC CFA Cache access command
+ *
+ * @param [in] opc MPC opcode
+ *
+ * @param [out] cmd_buff Command data buffer to write the command to
+ *
+ * @param [in/out] cmd_buff_len Pointer to command buffer size param
+ * Set by caller to indicate the input cmd_buff size.
+ * Set to the actual size of the command generated by the api.
+ *
+ * @param [in] parms Pointer to MPC cache access command parameters
+ *
+ * @return 0 on Success, negative errno on failure
+ */
+int cfa_mpc_build_cache_axs_cmd(enum cfa_mpc_opcode opc, uint8_t *cmd_buff,
+ uint32_t *cmd_buff_len,
+ struct cfa_mpc_cache_axs_params *parms);
+
+/**
+ * Parse MPC CFA Cache access command completion result
+ *
+ * @param [in] opc MPC cache access opcode
+ *
+ * @param [in] resp_buff Data buffer containing the response to parse
+ *
+ * @param [in] resp_buff_len Response buffer size
+ *
+ * @param [out] result Pointer to MPC cache access result object. This
+ * object will contain the fields parsed and extracted from the
+ * response buffer.
+ *
+ * @return 0 on Success, negative errno on failure
+ */
+int cfa_mpc_parse_cache_axs_resp(enum cfa_mpc_opcode opc, uint8_t *resp_buff,
+ uint32_t resp_buff_len,
+ struct cfa_mpc_cache_axs_result *result);
+
+/**
+ * Build MPC CFA EM operation command
+ *
+ * @param [in] opc MPC EM opcode
+ *
+ * @param [in] cmd_buff Command data buffer to write the command to
+ *
+ * @param [in/out] cmd_buff_len Pointer to command buffer size param
+ * Set by caller to indicate the input cmd_buff size.
+ * Set to the actual size of the command generated by the api.
+ *
+ * @param [in] parms Pointer to MPC cache access command parameters
+ *
+ * @return 0 on Success, negative errno on failure
+ */
+int cfa_mpc_build_em_op_cmd(enum cfa_mpc_opcode opc, uint8_t *cmd_buff,
+ uint32_t *cmd_buff_len,
+ struct cfa_mpc_em_op_params *parms);
+
+/**
+ * Parse MPC CFA EM operation command completion result
+ *
+ * @param [in] opc MPC cache access opcode
+ *
+ * @param [in] resp_buff Data buffer containing the response to parse
+ *
+ * @param [in] resp_buff_len Response buffer size
+ *
+ * @param [out] result Pointer to MPC EM operation result object. This
+ * object will contain the fields parsed and extracted from the
+ * response buffer.
+ *
+ * @return 0 on Success, negative errno on failure
+ */
+int cfa_mpc_parse_em_op_resp(enum cfa_mpc_opcode opc, uint8_t *resp_buff,
+ uint32_t resp_buff_len,
+ struct cfa_mpc_em_op_result *result);
+
+#endif /* _CFA_BLD_P70_MPC_H_ */
new file mode 100644
@@ -0,0 +1,164 @@
+/****************************************************************************
+ * Copyright(c) 2021 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * @file
+ *
+ * @brief
+ */
+
+#ifndef _CFA_P70_H_
+#define _CFA_P70_H_
+
+#include "sys_util.h"
+#include "cfa_p70_hw.h"
+
+#define BITS_TO_BYTES(n) (((n) + 7) / 8)
+#define BYTES_TO_WORDS(n) (((n) + 3) / 4)
+
+/* EM Lrec size */
+#define CFA_P70_EM_LREC_SZ CFA_P70_EM_LREC_TOTAL_NUM_BITS
+/* Encap header length */
+#define CFA_P70_ACT_ENCAP_MIN_HDR_LEN 64
+/* Max AR pointers per MCG record */
+#define CFA_P70_ACT_MCG_MAX_AR_PTR 8
+/* Max Key fields */
+#define CFA_P70_KEY_FLD_ID_MAX CFA_P70_EM_KEY_LAYOUT_MAX_FLD
+
+/* profiler ILT, l2ctxt remap, and profile remap are 32-bit accessed */
+#define CFA_PROF_P7P0_ILT_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_PROF_ILT_DR_TOTAL_NUM_BITS)
+#define CFA_PROF_P7P0_L2_CTXT_RMP_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_PROF_L2_CTXT_RMP_DR_TOTAL_NUM_BITS)
+#define CFA_PROF_P7P0_PROFILE_RMP_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_PROF_PROFILE_RMP_DR_TOTAL_NUM_BITS)
+/* profiler TCAM and L2 ctxt TCAM are accessed via Wide-bus */
+#define CFA_PROF_P7P0_PROFILE_TCAM_NUM_WORDS \
+ NUM_WORDS_ALIGN_128BIT(CFA_P70_PROF_PROFILE_TCAM_TOTAL_NUM_BITS)
+#define CFA_PROF_P7P0_L2_CTXT_TCAM_NUM_WORDS \
+ NUM_WORDS_ALIGN_128BIT(CFA_P70_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS)
+/* FKB are accessed via Wide-bus */
+#define CFA_P70_EM_FKB_NUM_WORDS NUM_WORDS_ALIGN_128BIT(CFA_P70_EM_FKB_MAX_FLD)
+#define CFA_P70_EM_FKB_NUM_ENTRIES 128
+
+/* EM FKB Mask */
+/* EM_FKB_MASK total num bits defined in CFA EAS section 3.3.9.2.2 EM Key */
+#define CFA_P70_EM_FKB_MASK_TOTAL_NUM_BITS 896
+#define CFA_P70_EM_FKB_MASK_NUM_WORDS \
+ NUM_WORDS_ALIGN_128BIT(CFA_P70_EM_FKB_MASK_TOTAL_NUM_BITS)
+#define CFA_P70_EM_FKB_MASK_NUM_ENTRIES 128
+
+#define CFA_P70_WC_TCAM_FKB_NUM_WORDS \
+ NUM_WORDS_ALIGN_128BIT(CFA_P70_WC_TCAM_FKB_MAX_FLD)
+#define CFA_P70_WC_TCAM_FKB_NUM_ENTRIES 128
+/* VNIC-SVIF Properties Table are accessed via Wide-bus */
+#define CFA_ACT_P7P0_VSPT_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_VSPT_DR_TX_TOTAL_NUM_BITS)
+#define CFA_P70_ACT_VEB_TCAM_NUM_WORDS \
+ NUM_WORDS_ALIGN_128BIT(CFA_P70_ACT_VEB_TCAM_RX_TOTAL_NUM_BITS)
+#define CFA_P70_ACT_MIRROR_NUM_WORDS \
+ NUM_WORDS_ALIGN_128BIT(CFA_P70_ACT_MIRROR_TOTAL_NUM_BITS)
+#define CFA_P7P0_ACT_VEB_RMP_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_VEB_RMP_TOTAL_NUM_BITS)
+#define CFA_P7P0_ACT_LBT_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_LBT_DR_TOTAL_NUM_BITS)
+#define CFA_P70_LKUP_EM_ENTRY_SIZE_IN_BITS 256
+#define CFA_P70_LKUP_EM_MAX_ENTRIES 4
+#define CFA_P70_LKUP_EM_MAX_ENTRY_SIZE_IN_BITS \
+ (CFA_P70_LKUP_EM_ENTRY_SIZE_IN_BITS * CFA_P70_LKUP_EM_MAX_ENTRIES)
+/* Maximum EM key size in bits */
+#define CFA_P70_LKUP_EM_DATA_SIZE_IN_BITS \
+ (CFA_P70_LKUP_EM_MAX_ENTRY_SIZE_IN_BITS - CFA_P70_EM_LREC_SZ)
+#define CFA_P70_LKUP_WC_DATA_SIZE_IN_BITS 688
+#define CFA_P70_LKUP_WC_DATA_SIZE_WITH_CTRL_INFO_IN_BITS 700
+#define CFA_P70_LKUP_WC_DATA_SIZE \
+ (BITS_TO_BYTES(CFA_P70_LKUP_WC_DATA_SIZE_IN_BITS))
+#define CFA_P70_LKUP_WC_MAX_DATA_SIZE \
+ (BITS_TO_BYTES(CFA_P70_LKUP_WC_DATA_SIZE_WITH_CTRL_INFO_IN_BITS))
+#define CFA_P70_LKUP_WC_NUM_WORDS (BYTES_TO_WORDS(CFA_P70_LKUP_WC_DATA_SIZE))
+#define CFA_P70_LKUP_WC_NUM_WORDS_PER_BANK (CFA_P70_LKUP_WC_NUM_WORDS / 2)
+#define CFA_P70_LKUP_WC_LREC_DATA_SIZE \
+ (BITS_TO_BYTES(CFA_P70_WC_LREC_TOTAL_NUM_BITS))
+#define CFA_P70_LKUP_WC_LREC_NUM_WORDS \
+ (BYTES_TO_WORDS(CFA_P70_LKUP_WC_LREC_DATA_SIZE))
+#define CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO 175
+#define CFA_P70_LKUP_WC_SLICE_LEN 172
+#define CFA_P70_LKUP_WC_TCAM_IDX_MASK 0x1fff
+#define CFA_P70_LKUP_WC_ROW_IDX_SFT 2
+#define CFA_P70_LKUP_WC_SLICE_IDX_MASK 0x3
+#define CFA_P70_LKUP_WC_NUM_SLICES 4
+#define CFA_P70_LKUP_WC_NUM_SLICES_PER_BANK 2
+#define CFA_P70_LKUP_WC_TCAM_CTRL_172B_KEY 0
+#define CFA_P70_LKUP_WC_TCAM_CTRL_344B_KEY 1
+#define CFA_P70_LKUP_WC_TCAM_CTRL_688B_KEY 2
+#define CFA_P70_LKUP_WC_TCAM_CTRL_MODE_SFT 29
+#define CFA_P70_LKUP_WC_TCAM_CTRL_MODE_MASK 0x3
+#define CFA_P70_LKUP_WC_TCAM_CTRL_VALID_SFT 31
+#define CFA_P70_LKUP_WC_TCAM_CTRL_VALID_MASK 0x1
+#define CFA_P70_LKUP_WC_TCAM_CTRL_NUM_BITS 3
+#define CFA_P70_LKUP_WC_TCAM_CTRL_MODE_NUM_BITS 2
+#define GET_NUM_SLICES_FROM_MODE(mode) (1 << (mode))
+#define CFA_P70_LKUP_WC_SLICE_NUM_BYTES \
+ (BITS_TO_BYTES(CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO))
+#define CFA_P70_LKUP_WC_SLICE_NUM_WORDS \
+ (BYTES_TO_WORDS(CFA_P70_LKUP_WC_SLICE_NUM_BYTES))
+#define CFA_P70_WC_TCAM_GET_NUM_SLICES_FROM_NUM_BYTES(n) \
+ ((((n) << 3) + CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO - 1) / \
+ CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO)
+#define CFA_MASK32(N) (((N) < 32) ? ((1U << (N)) - 1) : 0xffffffff)
+#define CFA_P70_ECV_VTAG_ADD0_IMMED CFA_P70_ECV_VTAG_ADD0_IMMED_PRI0
+#define CFA_P70_ECV_VTAG_PRI_MASK \
+ (~CFA_P70_ECV_VTAG_ADD0_IMMED & \
+ CFA_MASK32(CFA_P70_ACT_ENC_ECV_VTAG_NUM_BITS))
+
+#define CFA_P70_LKUP_EPOCH0_NUM_WORDS 1
+#define CFA_P70_LKUP_EPOCH1_NUM_WORDS 1
+#define CFA_P70_LKUP_EPOCH0_ENTRIES 4096
+#define CFA_P70_LKUP_EPOCH1_ENTRIES 256
+
+/* Field range check table register widths */
+#define CFA_P70_FRC_PROF_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_FRC_PROFILE_TOTAL_NUM_BITS)
+#define CFA_P70_FRC_ENTRY_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_FRC_RANGE_TOTAL_NUM_BITS)
+
+/* Connection tracking table register widths */
+#define CFA_P70_CT_STATE_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_CT_STATE_TOTAL_NUM_BITS)
+#define CFA_P70_CT_RULE_TCAM_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_CT_RULE_TOTAL_NUM_BITS)
+#define CFA_P70_CT_RULE_TCAM_RMP_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_CT_RULE_RECORD_TOTAL_NUM_BITS)
+
+/* Feature Chain table register widths */
+#define CFA_P70_ACT_FC_TCAM_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_FC_TCAM_TOTAL_NUM_BITS)
+#define CFA_P70_ACT_FC_TCAM_RMP_NUM_WORDS \
+ NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_FC_TCAM_RESULT_TOTAL_NUM_BITS)
+/* Feature Context table register width */
+#define CFA_P70_ACT_FC_NUM_WORDS \
+ NUM_WORDS_ALIGN_128BIT(CFA_P70_ACT_FC_RMP_DR_TOTAL_NUM_BITS)
+
+/* Meter instance table register width */
+#define CFA_P70_ACT_METER_NUM_WORDS \
+ NUM_WORDS_ALIGN_128BIT(CFA_P70_METERS_TOTAL_NUM_BITS)
+
+/* Metadata Mask table register widths */
+#define CFA_P70_METAMASK_PROF_NUM_WORDS 1
+#define CFA_P70_METAMASK_LKUP_NUM_WORDS 1
+#define CFA_P70_METAMASK_ACT_NUM_WORDS 1
+#define MAX_METAMASK_PROF(chip_cfg) 8
+#define MAX_METAMASK_LKUP(chip_cfg) 8
+#define MAX_METAMASK_ACT(chip_cfg) 16
+
+#define CFA_P70_VEB_TCAM_NUM_SLICES 1
+#define CFA_P70_CT_TCAM_NUM_SLICES 1
+#define CFA_P70_FC_TCAM_NUM_SLICES 1
+#define CFA_P70_L2CTXT_TCAM_NUM_SLICES 1
+#define CFA_P70_PROF_TCAM_NUM_SLICES 1
+
+#endif /* _CFA_P70_H_ */
new file mode 100644
@@ -0,0 +1,4286 @@
+/****************************************************************************
+ * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * Name: cfa_p70_hw.h
+ *
+ * Description: CFA HW table layout field position/length definitions
+ *
+ * Date: 09/29/22 11:50:37
+ *
+ * Note: This file is scripted generated by ./cfa_header_gen.py.
+ * DO NOT modify this file manually !!!!
+ *
+ ****************************************************************************/
+#ifndef _CFA_P70_HW_H_
+#define _CFA_P70_HW_H_
+
+/* clang-format off */
+#include "cfa_bld_p70_field_ids.h"
+
+
+/**
+ * Field code selection 1 for range checking (for idx 1 ...)
+ */
+#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_1_BITPOS 36
+#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_1_NUM_BITS 4
+
+/**
+ * Mask of ranges to check against FIELD_SEL_1
+ */
+#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_1_BITPOS 20
+#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_1_NUM_BITS 16
+
+/**
+ * Field code selection 0 for range checking
+ */
+#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_0_BITPOS 16
+#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_0_NUM_BITS 4
+
+/**
+ * Mask of ranges to check against FIELD_SEL_0 The following shows the
+ * FIELD_SEL code points:
+ */
+#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_BITPOS 0
+#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_NUM_BITS 16
+/**
+ * Mask of ranges to check against FIELD_SEL_0 The following shows the
+ * FIELD_SEL code points:
+ */
+enum cfa_p70_lkup_frc_profile_range_check_0 {
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL2_OVLAN_VID = 0,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL2_IVLAN_VID = 1,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL4_SRC = 2,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL4_DEST = 3,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L2_OVLAN_VID = 4,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L2_IVLAN_VID = 5,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_IP_LENGTH = 6,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L4_SRC = 7,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L4_DEST = 8,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TUN_ID = 9,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TUN_CTXT = 10,
+ CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_0 = 15,
+};
+
+/**
+ * Total number of bits for LKUP_FRC_PROFILE
+ */
+#define CFA_P70_LKUP_FRC_PROFILE_TOTAL_NUM_BITS 40
+
+/**
+ * When 1, block rule searches and do host notify during background
+ * visit
+ */
+#define CFA_P70_LKUP_CT_STATE_NOTIFY_BITPOS 13
+#define CFA_P70_LKUP_CT_STATE_NOTIFY_NUM_BITS 1
+
+/**
+ * Next state to go to after host notify (only used when NOTIFY=1)
+ */
+#define CFA_P70_LKUP_CT_STATE_NOTIFY_STATE_BITPOS 8
+#define CFA_P70_LKUP_CT_STATE_NOTIFY_STATE_NUM_BITS 5
+
+/**
+ * Default forwarding action (0=fwd, 1=miss, 2/3=copy)
+ */
+#define CFA_P70_LKUP_CT_STATE_ACTION_BITPOS 6
+#define CFA_P70_LKUP_CT_STATE_ACTION_NUM_BITS 2
+
+/**
+ * Specifies timer (0=disabled, 1-3=timers 1-3)
+ */
+#define CFA_P70_LKUP_CT_STATE_TIMER_SELECT_BITPOS 4
+#define CFA_P70_LKUP_CT_STATE_TIMER_SELECT_NUM_BITS 2
+
+/**
+ * Timer preload value for connections in this state
+ */
+#define CFA_P70_LKUP_CT_STATE_TIMER_PRELOAD_BITPOS 0
+#define CFA_P70_LKUP_CT_STATE_TIMER_PRELOAD_NUM_BITS 4
+
+/**
+ * Total number of bits for LKUP_CT_STATE
+ */
+#define CFA_P70_LKUP_CT_STATE_TOTAL_NUM_BITS 14
+
+/**
+ * Rule only used if VALID=1 (for idx 1 ...)
+ */
+#define CFA_P70_LKUP_CT_RULE_VALID_BITPOS 38
+#define CFA_P70_LKUP_CT_RULE_VALID_NUM_BITS 1
+
+/**
+ * Mask
+ */
+#define CFA_P70_LKUP_CT_RULE_MASK_BITPOS 19
+#define CFA_P70_LKUP_CT_RULE_MASK_NUM_BITS 19
+
+/**
+ * Rule for packet (1) or background (0)
+ */
+#define CFA_P70_LKUP_CT_RULE_PKT_NOT_BG_BITPOS 18
+#define CFA_P70_LKUP_CT_RULE_PKT_NOT_BG_NUM_BITS 1
+
+/**
+ * Current connection state
+ */
+#define CFA_P70_LKUP_CT_RULE_STATE_BITPOS 13
+#define CFA_P70_LKUP_CT_RULE_STATE_NUM_BITS 5
+
+/**
+ * TCP packet flags
+ */
+#define CFA_P70_LKUP_CT_RULE_TCP_FLAGS_BITPOS 4
+#define CFA_P70_LKUP_CT_RULE_TCP_FLAGS_NUM_BITS 9
+
+/**
+ * Packet protocol is TCP
+ */
+#define CFA_P70_LKUP_CT_RULE_PROT_IS_TCP_BITPOS 3
+#define CFA_P70_LKUP_CT_RULE_PROT_IS_TCP_NUM_BITS 1
+
+/**
+ * Updating tcp_msb_loc
+ */
+#define CFA_P70_LKUP_CT_RULE_MSB_UPDT_BITPOS 2
+#define CFA_P70_LKUP_CT_RULE_MSB_UPDT_NUM_BITS 1
+
+/**
+ * Packet flag error
+ */
+#define CFA_P70_LKUP_CT_RULE_FLAGS_FAILED_BITPOS 1
+#define CFA_P70_LKUP_CT_RULE_FLAGS_FAILED_NUM_BITS 1
+
+/**
+ * Packet failed TCP window check If VALID=0, the rule is ignored during
+ * searches. When VALID=1, MASK[18:0] provides a mask for bits 18:0. If
+ * the mask bit is set to 0, the corresponding bit is ignored during
+ * searches (does not need to match for the rule to match). During
+ * background updates, all fields in the search key other than STATE are
+ * always 0 (PKT_NOT_BG=0 and the other fields are unused). During
+ * packet updates when PROT_IS_TCP=0, PKT_NOT_BG=1 and STATE is set to
+ * the current state but the other fields will always be 0. If there is
+ * a matching rule found, the record in LKUP_CT_RULE_RECORD for that
+ * rule number is used.
+ */
+#define CFA_P70_LKUP_CT_RULE_WIN_FAILED_BITPOS 0
+#define CFA_P70_LKUP_CT_RULE_WIN_FAILED_NUM_BITS 1
+
+/**
+ * Total number of bits for LKUP_CT_RULE
+ */
+#define CFA_P70_LKUP_CT_RULE_TOTAL_NUM_BITS 39
+
+/**
+ * Forward action (packet only): 0=fwd, 1=miss, 2/3=copy
+ */
+#define CFA_P70_LKUP_CT_RULE_RECORD_ACTION_BITPOS 7
+#define CFA_P70_LKUP_CT_RULE_RECORD_ACTION_NUM_BITS 2
+
+/**
+ * Next state for the connection
+ */
+#define CFA_P70_LKUP_CT_RULE_RECORD_NEXT_STATE_BITPOS 2
+#define CFA_P70_LKUP_CT_RULE_RECORD_NEXT_STATE_NUM_BITS 5
+
+/**
+ * Signals whether to send message to other CFA.k When SEND=0, no
+ * message is sent. Otherwise, SEND[1] indicates that TCP_MSB_LOC in the
+ * message is valid and SEND[0] that STATE is valid.
+ */
+#define CFA_P70_LKUP_CT_RULE_RECORD_SEND_BITPOS 0
+#define CFA_P70_LKUP_CT_RULE_RECORD_SEND_NUM_BITS 2
+
+/**
+ * Total number of bits for LKUP_CT_RULE_RECORD
+ */
+#define CFA_P70_LKUP_CT_RULE_RECORD_TOTAL_NUM_BITS 9
+
+/**
+ * destination remap mode when enabled
+ */
+#define CFA_P70_ACT_VEB_RMP_MODE_BITPOS 6
+#define CFA_P70_ACT_VEB_RMP_MODE_NUM_BITS 1
+/**
+ * destination remap mode when enabled
+ */
+enum cfa_p70_act_veb_rmp_mode {
+ /* over write existing bitmap with entry */
+ CFA_P70_ACT_VEB_RMP_MODE_OVRWRT = 0,
+ /* or entry bit map with existing */
+ CFA_P70_ACT_VEB_RMP_MODE_ORTGTHR = 1,
+};
+
+/**
+ * enable remap the bitmap
+ */
+#define CFA_P70_ACT_VEB_RMP_ENABLE_BITPOS 5
+#define CFA_P70_ACT_VEB_RMP_ENABLE_NUM_BITS 1
+
+/**
+ * destination bitmap #CAS_SW_REF
+ * Action.CFA.VEB.Remap.tx.veb.remap.entry
+ */
+#define CFA_P70_ACT_VEB_RMP_BITMAP_BITPOS 0
+#define CFA_P70_ACT_VEB_RMP_BITMAP_NUM_BITS 5
+
+/**
+ * Total number of bits for ACT_VEB_RMP
+ */
+#define CFA_P70_ACT_VEB_RMP_TOTAL_NUM_BITS 7
+
+/**
+ * Range low
+ */
+#define CFA_P70_LKUP_FRC_RANGE_RANGE_LO_BITPOS 16
+#define CFA_P70_LKUP_FRC_RANGE_RANGE_LO_NUM_BITS 16
+
+/**
+ * Range high Field matches range when in [range_lo, range_hi]
+ * (inclusive). A read/write to this register causes a read/write to the
+ * LKUP_FRC_RANGE memory at address LKUP_FRC_RANGE_ADDR.
+ */
+#define CFA_P70_LKUP_FRC_RANGE_RANGE_HI_BITPOS 0
+#define CFA_P70_LKUP_FRC_RANGE_RANGE_HI_NUM_BITS 16
+
+/**
+ * Total number of bits for LKUP_FRC_RANGE
+ */
+#define CFA_P70_LKUP_FRC_RANGE_TOTAL_NUM_BITS 32
+
+/**
+ * TCAM entry is valid (for idx 7 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_VALID_BITPOS 255
+#define CFA_P70_PROF_L2_CTXT_TCAM_VALID_NUM_BITS 1
+
+/**
+ * spare bits (for idx 7 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_SPARE_BITPOS 253
+#define CFA_P70_PROF_L2_CTXT_TCAM_SPARE_NUM_BITS 2
+
+/**
+ * Multi-pass cycle count (for idx 7 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_MPASS_CNT_BITPOS 251
+#define CFA_P70_PROF_L2_CTXT_TCAM_MPASS_CNT_NUM_BITS 2
+
+/**
+ * Recycle count from prof_in (for idx 7 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_RCYC_BITPOS 247
+#define CFA_P70_PROF_L2_CTXT_TCAM_RCYC_NUM_BITS 4
+
+/**
+ * loopback input from prof_in (for idx 7 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_LOOPBACK_BITPOS 246
+#define CFA_P70_PROF_L2_CTXT_TCAM_LOOPBACK_NUM_BITS 1
+
+/**
+ * Source network port from prof_in (for idx 7 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_SPIF_BITPOS 244
+#define CFA_P70_PROF_L2_CTXT_TCAM_SPIF_NUM_BITS 2
+
+/**
+ * Partition provided by input block (for idx 7 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_PARIF_BITPOS 239
+#define CFA_P70_PROF_L2_CTXT_TCAM_PARIF_NUM_BITS 5
+
+/**
+ * Source network port or vnic (for idx 7 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_SVIF_BITPOS 228
+#define CFA_P70_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS 11
+
+/**
+ * Metadata provided by Input block
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_METADATA_BITPOS 196
+#define CFA_P70_PROF_L2_CTXT_TCAM_METADATA_NUM_BITS 32
+
+/**
+ * L2 function
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_L2_FUNC_BITPOS 188
+#define CFA_P70_PROF_L2_CTXT_TCAM_L2_FUNC_NUM_BITS 8
+
+/**
+ * ROCE Packet detected by the Parser (for idx 5 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_ROCE_BITPOS 187
+#define CFA_P70_PROF_L2_CTXT_TCAM_ROCE_NUM_BITS 1
+
+/**
+ * Pure LLC Packet detected by the Parser. (for idx 5 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_PURE_LLC_BITPOS 186
+#define CFA_P70_PROF_L2_CTXT_TCAM_PURE_LLC_NUM_BITS 1
+
+/**
+ * 5b enc Outer Tunnel Type (for idx 5 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_BITPOS 181
+#define CFA_P70_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_NUM_BITS 5
+
+/**
+ * 5b enc Tunnel Type The id_ctxt field is tunnel id or tunnel context
+ * selected from outer tunnel header or tunnel header. (for idx 5 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_T_HDR_TYPE_BITPOS 176
+#define CFA_P70_PROF_L2_CTXT_TCAM_T_HDR_TYPE_NUM_BITS 5
+
+/**
+ * FLDS Tunnel Status ID or Context. Each of these fields are from the
+ * selected outer tunnel, tunnel, inner, or outermost L2 header
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_ID_CTXT_BITPOS 144
+#define CFA_P70_PROF_L2_CTXT_TCAM_ID_CTXT_NUM_BITS 32
+
+/**
+ * Selected DMAC/SMAC
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_MAC0_BITPOS 96
+#define CFA_P70_PROF_L2_CTXT_TCAM_MAC0_NUM_BITS 48
+
+/**
+ * Selected DMAC/SMAC
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_MAC1_BITPOS 48
+#define CFA_P70_PROF_L2_CTXT_TCAM_MAC1_NUM_BITS 48
+
+/**
+ * 1+ VLAN tags present (for idx 1 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_VTAG_PRESENT_BITPOS 47
+#define CFA_P70_PROF_L2_CTXT_TCAM_VTAG_PRESENT_NUM_BITS 1
+
+/**
+ * 2 VLAN tags present (for idx 1 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_TWO_VTAGS_BITPOS 46
+#define CFA_P70_PROF_L2_CTXT_TCAM_TWO_VTAGS_NUM_BITS 1
+
+/**
+ * Outer VLAN VID (for idx 1 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_VID_BITPOS 34
+#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_VID_NUM_BITS 12
+
+/**
+ * Outer VLAN TPID, 3b encoded
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_BITPOS 31
+#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_NUM_BITS 3
+
+/**
+ * Inner VLAN VID
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_VID_BITPOS 19
+#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_VID_NUM_BITS 12
+
+/**
+ * Inner VLAN TPID, 3b encoded
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_BITPOS 16
+#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_NUM_BITS 3
+
+/**
+ * Ethertype. #CAS_SW_REF Profiler.l2ip.context.tcam.key #CAS_SW_REF
+ * Profiler.l2ip.context.ipv6.tcam.key
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_ETYPE_BITPOS 0
+#define CFA_P70_PROF_L2_CTXT_TCAM_ETYPE_NUM_BITS 16
+
+/**
+ * Total number of bits for PROF_L2_CTXT_TCAM
+ */
+#define CFA_P70_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS 256
+
+/**
+ * Valid(1)/Invalid(0) TCAM entry. (for idx 5 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_VALID_BITPOS 183
+#define CFA_P70_PROF_PROFILE_TCAM_VALID_NUM_BITS 1
+
+/**
+ * spare bits. (for idx 5 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_SPARE_BITPOS 181
+#define CFA_P70_PROF_PROFILE_TCAM_SPARE_NUM_BITS 2
+
+/**
+ * Loopback bit. (for idx 5 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_LOOPBACK_BITPOS 180
+#define CFA_P70_PROF_PROFILE_TCAM_LOOPBACK_NUM_BITS 1
+
+/**
+ * Packet type directly from prof_in (for idx 5 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_PKT_TYPE_BITPOS 176
+#define CFA_P70_PROF_PROFILE_TCAM_PKT_TYPE_NUM_BITS 4
+
+/**
+ * Recycle count from prof_in (for idx 5 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_RCYC_BITPOS 172
+#define CFA_P70_PROF_PROFILE_TCAM_RCYC_NUM_BITS 4
+
+/**
+ * From L2 Context Lookup stage.
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_METADATA_BITPOS 140
+#define CFA_P70_PROF_PROFILE_TCAM_METADATA_NUM_BITS 32
+
+/**
+ * Aggregate error flag from Input stage. (for idx 4 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_AGG_ERROR_BITPOS 139
+#define CFA_P70_PROF_PROFILE_TCAM_AGG_ERROR_NUM_BITS 1
+
+/**
+ * L2 function (for idx 4 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L2_FUNC_BITPOS 131
+#define CFA_P70_PROF_PROFILE_TCAM_L2_FUNC_NUM_BITS 8
+
+/**
+ * Profile function from L2 Context Lookup stage.
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_PROF_FUNC_BITPOS 123
+#define CFA_P70_PROF_PROFILE_TCAM_PROF_FUNC_NUM_BITS 8
+
+/**
+ * From FLDS Input General Status tunnel(1)/no tunnel(0) (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_HREC_NEXT_BITPOS 121
+#define CFA_P70_PROF_PROFILE_TCAM_HREC_NEXT_NUM_BITS 2
+
+/**
+ * INT header type. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_TYPE_BITPOS 119
+#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_TYPE_NUM_BITS 2
+
+/**
+ * INT header group. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_GROUP_BITPOS 117
+#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_GROUP_NUM_BITS 2
+
+/**
+ * INT metadata is tail stamp. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_INT_IFA_TAIL_BITPOS 116
+#define CFA_P70_PROF_PROFILE_TCAM_INT_IFA_TAIL_NUM_BITS 1
+
+/**
+ * resolved flds_otl2_hdr_valid. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_VALID_BITPOS 115
+#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_VALID_NUM_BITS 1
+
+/**
+ * Outer Tunnel L2 header type. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_BITPOS 113
+#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_NUM_BITS 2
+
+/**
+ * flds_otl2_dst_type remapped: UC(0)/MC(2)/BC(3) (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_BITPOS 111
+#define CFA_P70_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_NUM_BITS 2
+
+/**
+ * 1+ VLAN tags present in Outer Tunnel L2 header (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_BITPOS 110
+#define CFA_P70_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_NUM_BITS 1
+
+/**
+ * 2 VLAN tags present in Outer Tunnel L2 header (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_BITPOS 109
+#define CFA_P70_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_NUM_BITS 1
+
+/**
+ * resolved flds_otl3_hdr_valid. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_VALID_BITPOS 108
+#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_VALID_NUM_BITS 1
+
+/**
+ * flds_otl3_hdr_valid is stop_w_error. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_BITPOS 107
+#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_NUM_BITS 1
+
+/**
+ * Outer Tunnel L3 header type directly from FLDS. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_BITPOS 103
+#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_NUM_BITS 4
+
+/**
+ * Outer Tunnel L3 header is IPV4 or IPV6. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_BITPOS 102
+#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_NUM_BITS 1
+
+/**
+ * resolved flds_otl4_hdr_valid. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_VALID_BITPOS 101
+#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_VALID_NUM_BITS 1
+
+/**
+ * flds_otl4_hdr_valid is stop_w_error. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_BITPOS 100
+#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_NUM_BITS 1
+
+/**
+ * Outer Tunnel L4 header type. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_BITPOS 96
+#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_NUM_BITS 4
+
+/**
+ * OTL4 header is UDP or TCP. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_BITPOS 95
+#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_NUM_BITS 1
+
+/**
+ * resolved flds_ot_hdr_valid. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_VALID_BITPOS 94
+#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_VALID_NUM_BITS 1
+
+/**
+ * flds_ot_hdr_valid is stop_w_error. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_ERROR_BITPOS 93
+#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_ERROR_NUM_BITS 1
+
+/**
+ * Outer Tunnel header type. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_TYPE_BITPOS 88
+#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_TYPE_NUM_BITS 5
+
+/**
+ * Outer Tunnel header flags. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_FLAGS_BITPOS 80
+#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_FLAGS_NUM_BITS 8
+
+/**
+ * resolved flds_tl2_hdr_valid. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_VALID_BITPOS 79
+#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_VALID_NUM_BITS 1
+
+/**
+ * Tunnel L2 header type directly from FLDS. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_TYPE_BITPOS 77
+#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_TYPE_NUM_BITS 2
+
+/**
+ * flds_tl2_dst_type remapped: UC(0)/MC(2)/BC(3) (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL2_UC_MC_BC_BITPOS 75
+#define CFA_P70_PROF_PROFILE_TCAM_TL2_UC_MC_BC_NUM_BITS 2
+
+/**
+ * 1+ VLAN tags present in Tunnel L2 header (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_BITPOS 74
+#define CFA_P70_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_NUM_BITS 1
+
+/**
+ * 2 VLAN tags present in Tunnel L2 header (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_BITPOS 73
+#define CFA_P70_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_NUM_BITS 1
+
+/**
+ * resolved flds_tl3_hdr_valid. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_VALID_BITPOS 72
+#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_VALID_NUM_BITS 1
+
+/**
+ * flds_tl3_hdr_valid is stop_w_error. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ERROR_BITPOS 71
+#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ERROR_NUM_BITS 1
+
+/**
+ * Tunnel L3 header type directly from FLDS. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_TYPE_BITPOS 67
+#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_TYPE_NUM_BITS 4
+
+/**
+ * Tunnel L3 header is IPV4 or IPV6. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ISIP_BITPOS 66
+#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ISIP_NUM_BITS 1
+
+/**
+ * resolved flds_tl4_hdr_valid. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_VALID_BITPOS 65
+#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_VALID_NUM_BITS 1
+
+/**
+ * flds_tl4_hdr_valid is stop_w_error. (for idx 2 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_ERROR_BITPOS 64
+#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_ERROR_NUM_BITS 1
+
+/**
+ * Tunnel L4 header type directly from FLDS. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_TYPE_BITPOS 60
+#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_TYPE_NUM_BITS 4
+
+/**
+ * TL4 header is UDP or TCP. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_BITPOS 59
+#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_NUM_BITS 1
+
+/**
+ * resolved flds_tun_hdr_valid. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_VALID_BITPOS 58
+#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_VALID_NUM_BITS 1
+
+/**
+ * flds_tun_hdr_valid is stop_w_error. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_ERROR_BITPOS 57
+#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_ERROR_NUM_BITS 1
+
+/**
+ * Tunnel header type directly from FLDS. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_TYPE_BITPOS 52
+#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_TYPE_NUM_BITS 5
+
+/**
+ * Tunnel header flags directly from FLDS. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_BITPOS 44
+#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_NUM_BITS 8
+
+/**
+ * resolved flds_l2_hdr_valid. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_VALID_BITPOS 43
+#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_VALID_NUM_BITS 1
+
+/**
+ * flds_l2_hdr_valid is stop_w_error. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_ERROR_BITPOS 42
+#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_ERROR_NUM_BITS 1
+
+/**
+ * L2 header type directly from FLDS. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_TYPE_BITPOS 40
+#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_TYPE_NUM_BITS 2
+
+/**
+ * flds_l2_dst_type remapped: UC(0)/MC(2)/BC(3). (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L2_UC_MC_BC_BITPOS 38
+#define CFA_P70_PROF_PROFILE_TCAM_L2_UC_MC_BC_NUM_BITS 2
+
+/**
+ * 1+ VLAN tags present in inner L2 header. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_BITPOS 37
+#define CFA_P70_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_NUM_BITS 1
+
+/**
+ * 2 VLAN tags present in inner L2 header. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L2_TWO_VTAGS_BITPOS 36
+#define CFA_P70_PROF_PROFILE_TCAM_L2_TWO_VTAGS_NUM_BITS 1
+
+/**
+ * resolved flds_l3_hdr_valid. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_VALID_BITPOS 35
+#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_VALID_NUM_BITS 1
+
+/**
+ * flds_l3_hdr_valid is stop_w_error. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ERROR_BITPOS 34
+#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ERROR_NUM_BITS 1
+
+/**
+ * L3 header type directly from FLDS.
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_TYPE_BITPOS 30
+#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_TYPE_NUM_BITS 4
+
+/**
+ * L3 header is IPV4 or IPV6.
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ISIP_BITPOS 29
+#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ISIP_NUM_BITS 1
+
+/**
+ * L3 header next protocol directly from FLDS.
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L3_PROT_BITPOS 21
+#define CFA_P70_PROF_PROFILE_TCAM_L3_PROT_NUM_BITS 8
+
+/**
+ * resolved flds_l4_hdr_valid.
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_VALID_BITPOS 20
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_VALID_NUM_BITS 1
+
+/**
+ * flds_l4_hdr_valid is stop_w_error.
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_ERROR_BITPOS 19
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_ERROR_NUM_BITS 1
+
+/**
+ * L4 header type directly from FLDS.
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_TYPE_BITPOS 15
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_TYPE_NUM_BITS 4
+
+/**
+ * L4 header is UDP or TCP.2
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_BITPOS 14
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_NUM_BITS 1
+
+/**
+ * L4 header subtype directly from FLDS.
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_BITPOS 11
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_NUM_BITS 3
+
+/**
+ * L4 header flags directly from FLDS.
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_FLAGS_BITPOS 2
+#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_FLAGS_NUM_BITS 9
+
+/**
+ * DCN present bits directly from FLDS. #CAS_SW_REF
+ * Profiler.profile.lookup.tcam.key
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_L4_DCN_PRESENT_BITPOS 0
+#define CFA_P70_PROF_PROFILE_TCAM_L4_DCN_PRESENT_NUM_BITS 2
+
+/**
+ * Total number of bits for PROF_PROFILE_TCAM
+ */
+#define CFA_P70_PROF_PROFILE_TCAM_TOTAL_NUM_BITS 184
+
+/**
+ * Valid entry (for idx 2 ...)
+ */
+#define CFA_P70_ACT_VEB_TCAM_TX_VALID_BITPOS 79
+#define CFA_P70_ACT_VEB_TCAM_TX_VALID_NUM_BITS 1
+
+/**
+ * PF Parif Number (for idx 2 ...)
+ */
+#define CFA_P70_ACT_VEB_TCAM_TX_PARIF_IN_BITPOS 74
+#define CFA_P70_ACT_VEB_TCAM_TX_PARIF_IN_NUM_BITS 5
+
+/**
+ * Number of VLAN Tags. (for idx 2 ...)
+ */
+#define CFA_P70_ACT_VEB_TCAM_TX_NUM_VTAGS_BITPOS 72
+#define CFA_P70_ACT_VEB_TCAM_TX_NUM_VTAGS_NUM_BITS 2
+
+/**
+ * Dest. MAC Address
+ */
+#define CFA_P70_ACT_VEB_TCAM_TX_DMAC_BITPOS 24
+#define CFA_P70_ACT_VEB_TCAM_TX_DMAC_NUM_BITS 48
+
+/**
+ * Outer VLAN Tag ID
+ */
+#define CFA_P70_ACT_VEB_TCAM_TX_OVID_BITPOS 12
+#define CFA_P70_ACT_VEB_TCAM_TX_OVID_NUM_BITS 12
+
+/**
+ * Inner VLAN Tag ID #CAS_SW_REF Action.CFA.VEB.TCAM.tx.veb.tcam.entry
+ */
+#define CFA_P70_ACT_VEB_TCAM_TX_IVID_BITPOS 0
+#define CFA_P70_ACT_VEB_TCAM_TX_IVID_NUM_BITS 12
+
+/**
+ * Total number of bits for ACT_VEB_TCAM_TX
+ */
+#define CFA_P70_ACT_VEB_TCAM_TX_TOTAL_NUM_BITS 80
+
+/**
+ * Valid entry (for idx 2 ...)
+ */
+#define CFA_P70_ACT_VEB_TCAM_RX_VALID_BITPOS 79
+#define CFA_P70_ACT_VEB_TCAM_RX_VALID_NUM_BITS 1
+
+/**
+ * spare (for idx 2 ...)
+ */
+#define CFA_P70_ACT_VEB_TCAM_RX_SPARE_BITPOS 78
+#define CFA_P70_ACT_VEB_TCAM_RX_SPARE_NUM_BITS 1
+
+/**
+ * program to zero (for idx 2 ...)
+ */
+#define CFA_P70_ACT_VEB_TCAM_RX_PADDING_BITPOS 68
+#define CFA_P70_ACT_VEB_TCAM_RX_PADDING_NUM_BITS 10
+
+/**
+ * DMAC is unicast address (for idx 2 ...)
+ */
+#define CFA_P70_ACT_VEB_TCAM_RX_UNICAST_BITPOS 67
+#define CFA_P70_ACT_VEB_TCAM_RX_UNICAST_NUM_BITS 1
+
+/**
+ * DMAC is multicast address (for idx 2 ...)
+ */
+#define CFA_P70_ACT_VEB_TCAM_RX_MULTICAST_BITPOS 66
+#define CFA_P70_ACT_VEB_TCAM_RX_MULTICAST_NUM_BITS 1
+
+/**
+ * DMAC is broadcast address (for idx 2 ...)
+ */
+#define CFA_P70_ACT_VEB_TCAM_RX_BROADCAST_BITPOS 65
+#define CFA_P70_ACT_VEB_TCAM_RX_BROADCAST_NUM_BITS 1
+
+/**
+ * pfid
+ */
+#define CFA_P70_ACT_VEB_TCAM_RX_PFID_BITPOS 60
+#define CFA_P70_ACT_VEB_TCAM_RX_PFID_NUM_BITS 5
+
+/**
+ * vfid (for idx 1 ...)
+ */
+#define CFA_P70_ACT_VEB_TCAM_RX_VFID_BITPOS 48
+#define CFA_P70_ACT_VEB_TCAM_RX_VFID_NUM_BITS 12
+
+/**
+ * source mac #CAS_SW_REF AAction.CFA.VEB.TCAM.rx.veb.tcam.entry
+ */
+#define CFA_P70_ACT_VEB_TCAM_RX_SMAC_BITPOS 0
+#define CFA_P70_ACT_VEB_TCAM_RX_SMAC_NUM_BITS 48
+
+/**
+ * Total number of bits for ACT_VEB_TCAM_RX
+ */
+#define CFA_P70_ACT_VEB_TCAM_RX_TOTAL_NUM_BITS 80
+
+/**
+ * Valid entry (for idx 1 ...)
+ */
+#define CFA_P70_ACT_FC_TCAM_FC_VALID_BITPOS 33
+#define CFA_P70_ACT_FC_TCAM_FC_VALID_NUM_BITS 1
+
+/**
+ * Reserved (for idx 1 ...)
+ */
+#define CFA_P70_ACT_FC_TCAM_FC_RSVD_BITPOS 32
+#define CFA_P70_ACT_FC_TCAM_FC_RSVD_NUM_BITS 1
+
+/**
+ * Updated metadata. #CAS_SW_REF Action.CFA.FC.TCAM.fc.tcam.meta.entry
+ * #CAS_SW_REF Action.CFA.FC.TCAM.fc.tcam.l2ip.func.entry #CAS_SW_REF
+ * Action.CFA.FC.TCAM.fc.tcam.l2.ctxt.entry #CAS_SW_REF
+ * Action.CFA.FC.TCAM.fc.tcam.l2ipf.ctxt.entry
+ */
+#define CFA_P70_ACT_FC_TCAM_FC_METADATA_BITPOS 0
+#define CFA_P70_ACT_FC_TCAM_FC_METADATA_NUM_BITS 32
+
+/**
+ * Total number of bits for ACT_FC_TCAM
+ */
+#define CFA_P70_ACT_FC_TCAM_TOTAL_NUM_BITS 34
+
+/**
+ * New metadata.
+ */
+#define CFA_P70_ACT_FC_RMP_DR_METADATA_BITPOS 40
+#define CFA_P70_ACT_FC_RMP_DR_METADATA_NUM_BITS 32
+
+/**
+ * Metadata merge control mask.
+ */
+#define CFA_P70_ACT_FC_RMP_DR_METAMASK_BITPOS 8
+#define CFA_P70_ACT_FC_RMP_DR_METAMASK_NUM_BITS 32
+
+/**
+ * New L2 function. #CAS_SW_REF Action.CFA.FC.Remap.fc.remap.entry
+ */
+#define CFA_P70_ACT_FC_RMP_DR_L2_FUNC_BITPOS 0
+#define CFA_P70_ACT_FC_RMP_DR_L2_FUNC_NUM_BITS 8
+
+/**
+ * Total number of bits for ACT_FC_RMP_DR
+ */
+#define CFA_P70_ACT_FC_RMP_DR_TOTAL_NUM_BITS 72
+
+/**
+ * enables ilt metadata (for idx 3 ...)
+ */
+#define CFA_P70_PROF_ILT_DR_ILT_META_EN_BITPOS 104
+#define CFA_P70_PROF_ILT_DR_ILT_META_EN_NUM_BITS 1
+
+/**
+ * meta profile register index (for idx 3 ...)
+ */
+#define CFA_P70_PROF_ILT_DR_META_PROF_BITPOS 101
+#define CFA_P70_PROF_ILT_DR_META_PROF_NUM_BITS 3
+
+/**
+ * ilt metadata, used when ilt_meta_en is set
+ */
+#define CFA_P70_PROF_ILT_DR_METADATA_BITPOS 69
+#define CFA_P70_PROF_ILT_DR_METADATA_NUM_BITS 32
+
+/**
+ * Partition (for idx 2 ...)
+ */
+#define CFA_P70_PROF_ILT_DR_PARIF_BITPOS 64
+#define CFA_P70_PROF_ILT_DR_PARIF_NUM_BITS 5
+
+/**
+ * L2 function (for idx 1 ...)
+ */
+#define CFA_P70_PROF_ILT_DR_L2_FUNC_BITPOS 56
+#define CFA_P70_PROF_ILT_DR_L2_FUNC_NUM_BITS 8
+
+/**
+ * When set cfa_meta opcode is allowed (for idx 1 ...)
+ */
+#define CFA_P70_PROF_ILT_DR_EN_BD_META_BITPOS 55
+#define CFA_P70_PROF_ILT_DR_EN_BD_META_NUM_BITS 1
+
+/**
+ * When set act_rec_ptr is set to cfa_action if it is non-zero.
+ * Otherwise act_rec_ptr is set to act_rec_ptr from this table. (for idx
+ * 1 ...)
+ */
+#define CFA_P70_PROF_ILT_DR_EN_BD_ACTION_BITPOS 54
+#define CFA_P70_PROF_ILT_DR_EN_BD_ACTION_NUM_BITS 1
+
+/**
+ * When set destination is set to destination from this table. Otherwise
+ * it is set to est_dest. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_ILT_DR_EN_ILT_DEST_BITPOS 53
+#define CFA_P70_PROF_ILT_DR_EN_ILT_DEST_NUM_BITS 1
+
+/**
+ * ILT opcode (for idx 1 ...)
+ */
+#define CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BITPOS 50
+#define CFA_P70_PROF_ILT_DR_ILT_FWD_OP_NUM_BITS 3
+/**
+ * ILT opcode (for idx 1 ...)
+ */
+enum cfa_p70_prof_ilt_dr_ilt_fwd_op {
+ /* cfa is bypassed */
+ CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BYPASS_CFA = 0,
+ /* cfa is bypassed if packet is ROCE */
+ CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BYPASS_CFA_ROCE = 1,
+ /* profiler and lookup blocks are bypassed */
+ CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BYPASS_LKUP = 2,
+ /* packet proceeds to L2 Context Stage */
+ CFA_P70_PROF_ILT_DR_ILT_FWD_OP_NORMAL_FLOW = 3,
+ /* mark packet for drop */
+ CFA_P70_PROF_ILT_DR_ILT_FWD_OP_DROP = 4,
+};
+
+/**
+ * action hint used with act_rec_ptr (for idx 1 ...)
+ */
+#define CFA_P70_PROF_ILT_DR_ILT_ACT_HINT_BITPOS 48
+#define CFA_P70_PROF_ILT_DR_ILT_ACT_HINT_NUM_BITS 2
+
+/**
+ * table scope used with act_rec_ptr (for idx 1 ...)
+ */
+#define CFA_P70_PROF_ILT_DR_ILT_SCOPE_BITPOS 43
+#define CFA_P70_PROF_ILT_DR_ILT_SCOPE_NUM_BITS 5
+
+/**
+ * Default act_rec_ptr or explicit on Lookup Bypass.
+ */
+#define CFA_P70_PROF_ILT_DR_ILT_ACT_REC_PTR_BITPOS 17
+#define CFA_P70_PROF_ILT_DR_ILT_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * used for destination #CAS_SW_REF Profiler.input.lookup.table.entry
+ */
+#define CFA_P70_PROF_ILT_DR_ILT_DESTINATION_BITPOS 0
+#define CFA_P70_PROF_ILT_DR_ILT_DESTINATION_NUM_BITS 17
+
+/**
+ * Total number of bits for PROF_ILT_DR
+ */
+#define CFA_P70_PROF_ILT_DR_TOTAL_NUM_BITS 105
+
+/**
+ * Normal operation. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_BITPOS 42
+#define CFA_P70_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_NUM_BITS 1
+
+/**
+ * Enable search in EM database. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_BITPOS 41
+#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_NUM_BITS 1
+
+/**
+ * ID to differentiate common EM keys. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_BITPOS 33
+#define CFA_P70_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_NUM_BITS 8
+
+/**
+ * Exact match key template select.
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_EM_KEY_ID_BITPOS 26
+#define CFA_P70_PROF_PROFILE_RMP_DR_EM_KEY_ID_NUM_BITS 7
+
+/**
+ * Exact Match Lookup table scope.
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SCOPE_BITPOS 21
+#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SCOPE_NUM_BITS 5
+
+/**
+ * Enable search in TCAM database.
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_BITPOS 20
+#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_NUM_BITS 1
+
+/**
+ * ID to differentiate common TCAM keys.
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_BITPOS 12
+#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_NUM_BITS 8
+
+/**
+ * TCAM key template select.
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_BITPOS 5
+#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_NUM_BITS 7
+
+/**
+ * Wild-card TCAM Lookup table scope.
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SCOPE_BITPOS 0
+#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SCOPE_NUM_BITS 5
+
+/**
+ * Total number of bits for PROF_PROFILE_RMP_DR
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_TOTAL_NUM_BITS 43
+
+/**
+ * Bypass operation. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_BITPOS 42
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_NUM_BITS 1
+
+/**
+ * Reserved for future use. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_RESERVED_BITPOS 36
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_RESERVED_NUM_BITS 6
+
+/**
+ * Bypass operations. (for idx 1 ...)
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BITPOS 33
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_NUM_BITS 3
+/**
+ * Bypass operations. (for idx 1 ...)
+ */
+enum cfa_p70_prof_profile_rmp_dr_byp_bypass_op {
+ /* cfa is bypassed */
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_CFA = 0,
+ /* Byass lookup use act_record_ptr from this table. */
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_LKUP = 1,
+ /* Byass lookup use Partition Default Action Record Pointer Table */
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_DEFAULT = 2,
+ /* Byass lookup use Partition Error Action Record Pointer Table. */
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_ERROR = 3,
+ /* set the drop flag. */
+ CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_DROP = 4,
+};
+
+/**
+ * action hint used with plact_rec_ptr
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_BITPOS 31
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_NUM_BITS 2
+
+/**
+ * table scope used with pl_act_rec_ptr
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_BITPOS 26
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_NUM_BITS 5
+
+/**
+ * Used for BYPASS_LKUP. #CAS_SW_REF Profiler.profile.remap.entry.build
+ * #CAS_SW_REF Profiler.profile.remap.entry.bypass.cfa #CAS_SW_REF
+ * Profiler.profile.remap.entry.bypass.lkup #CAS_SW_REF
+ * Profiler.profile.remap.entry.other
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_BITPOS 0
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * Total number of bits for PROF_PROFILE_RMP_DR_BYP
+ */
+#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_TOTAL_NUM_BITS 43
+
+/**
+ * VLAN TPID anti-spoofing control.
+ */
+#define CFA_P70_ACT_VSPT_DR_TX_TPID_AS_CTL_BITPOS 29
+#define CFA_P70_ACT_VSPT_DR_TX_TPID_AS_CTL_NUM_BITS 2
+/**
+ * VLAN TPID anti-spoofing control.
+ */
+enum cfa_p70_act_vspt_dr_tx_tpid_as_ctl {
+ CFA_P70_ACT_VSPT_DR_TX_TPID_IGNORE = 0,
+ CFA_P70_ACT_VSPT_DR_TX_TPID_DEFAULT = 1,
+ CFA_P70_ACT_VSPT_DR_TX_TPID_DROP = 2,
+};
+
+/**
+ * VLAN allowed TPID bit map.
+ */
+#define CFA_P70_ACT_VSPT_DR_TX_ALWD_TPID_BITPOS 21
+#define CFA_P70_ACT_VSPT_DR_TX_ALWD_TPID_NUM_BITS 8
+
+/**
+ * VLAN encoded default TPID.
+ */
+#define CFA_P70_ACT_VSPT_DR_TX_DFLT_TPID_BITPOS 18
+#define CFA_P70_ACT_VSPT_DR_TX_DFLT_TPID_NUM_BITS 3
+
+/**
+ * VLAN PRIority anti-spoofing control.
+ */
+#define CFA_P70_ACT_VSPT_DR_TX_PRI_AS_CTL_BITPOS 16
+#define CFA_P70_ACT_VSPT_DR_TX_PRI_AS_CTL_NUM_BITS 2
+/**
+ * VLAN PRIority anti-spoofing control.
+ */
+enum cfa_p70_act_vspt_dr_tx_pri_as_ctl {
+ CFA_P70_ACT_VSPT_DR_TX_PRI_IGNORE = 0,
+ CFA_P70_ACT_VSPT_DR_TX_PRI_DEFAULT = 1,
+ CFA_P70_ACT_VSPT_DR_TX_PRI_DROP = 2,
+};
+
+/**
+ * VLAN allowed PRIority bit map.
+ */
+#define CFA_P70_ACT_VSPT_DR_TX_ALWD_PRI_BITPOS 8
+#define CFA_P70_ACT_VSPT_DR_TX_ALWD_PRI_NUM_BITS 8
+
+/**
+ * VLAN default PRIority.
+ */
+#define CFA_P70_ACT_VSPT_DR_TX_DFLT_PRI_BITPOS 5
+#define CFA_P70_ACT_VSPT_DR_TX_DFLT_PRI_NUM_BITS 3
+
+/**
+ * Mirror destination (1..31) or 5'h0=NO_MIRROR #CAS_SW_REF
+ * Action.CFA.DEST.SVIF.Property.Tables.tx.svif.property.entry
+ */
+#define CFA_P70_ACT_VSPT_DR_TX_MIR_BITPOS 0
+#define CFA_P70_ACT_VSPT_DR_TX_MIR_NUM_BITS 5
+
+/**
+ * Total number of bits for ACT_VSPT_DR_TX
+ */
+#define CFA_P70_ACT_VSPT_DR_TX_TOTAL_NUM_BITS 31
+
+/**
+ * Reserved for future use.
+ */
+#define CFA_P70_ACT_VSPT_DR_RX_RSVD_BITPOS 24
+#define CFA_P70_ACT_VSPT_DR_RX_RSVD_NUM_BITS 7
+
+/**
+ * Output metadata format select.
+ */
+#define CFA_P70_ACT_VSPT_DR_RX_METAFMT_BITPOS 22
+#define CFA_P70_ACT_VSPT_DR_RX_METAFMT_NUM_BITS 2
+/**
+ * Output metadata format select.
+ */
+enum cfa_p70_act_vspt_dr_rx_metafmt {
+ CFA_P70_ACT_VSPT_DR_RX_METAFMT_ACT_REC_PTR = 0,
+ CFA_P70_ACT_VSPT_DR_RX_METAFMT_TUNNEL_ID = 1,
+ CFA_P70_ACT_VSPT_DR_RX_METAFMT_CSTM_HDR_DATA = 2,
+ CFA_P70_ACT_VSPT_DR_RX_METAFMT_HDR_OFFSETS = 3,
+};
+
+/**
+ * Function ID: 4 bit PF and 12 bit VID (VNIC ID)
+ */
+#define CFA_P70_ACT_VSPT_DR_RX_FID_BITPOS 5
+#define CFA_P70_ACT_VSPT_DR_RX_FID_NUM_BITS 17
+
+/**
+ * Mirror destination (1..31) or 5'h0=NO_MIRROR #CAS_SW_REF
+ * Action.CFA.DEST.SVIF.Property.Tables.rx.destination.property.entry
+ */
+#define CFA_P70_ACT_VSPT_DR_RX_MIR_BITPOS 0
+#define CFA_P70_ACT_VSPT_DR_RX_MIR_NUM_BITS 5
+
+/**
+ * Total number of bits for ACT_VSPT_DR_RX
+ */
+#define CFA_P70_ACT_VSPT_DR_RX_TOTAL_NUM_BITS 31
+
+/**
+ * LAG destination bit map.
+ */
+#define CFA_P70_ACT_LBT_DR_DST_BMP_BITPOS 0
+#define CFA_P70_ACT_LBT_DR_DST_BMP_NUM_BITS 5
+
+/**
+ * Total number of bits for ACT_LBT_DR
+ */
+#define CFA_P70_ACT_LBT_DR_TOTAL_NUM_BITS 5
+
+/**
+ * Preserve incoming partition, don't remap (for idx 3 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_BITPOS 126
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_NUM_BITS 1
+
+/**
+ * Partition, replaces parif from input block (for idx 3 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_PARIF_BITPOS 121
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_PARIF_NUM_BITS 5
+
+/**
+ * Preserve incoming L2_CTXT (for idx 3 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_BITPOS 120
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_NUM_BITS 1
+
+/**
+ * L2 logical id which may be used in EM and WC Lookups. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_BITPOS 109
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_NUM_BITS 11
+
+/**
+ * Preserve incoming PROF_FUNC (for idx 3 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_BITPOS 108
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_NUM_BITS 1
+
+/**
+ * Allow Profile TCAM Lookup Table to be logically partitioned. (for idx
+ * 3 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_PROF_FUNC_BITPOS 100
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_PROF_FUNC_NUM_BITS 8
+
+/**
+ * Context operation code. (for idx 3 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_BITPOS 98
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_NUM_BITS 2
+/**
+ * Context operation code. (for idx 3 ...)
+ */
+enum cfa_p70_prof_l2_ctxt_rmp_dr_ctxt_opcode {
+ /* def_ctxt_data provides destination */
+ CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_BYPASS_CFA = 0,
+ /* def_ctxt_data provides act_rec_ptr */
+ CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_BYPASS_LKUP = 1,
+ /* continue normal flow */
+ CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_NORMAL_FLOW = 2,
+ /* mark packet for drop */
+ CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_DROP = 3,
+};
+
+/**
+ * Enables remap of meta_data from Input block (for idx 3 ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_BITPOS 97
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_NUM_BITS 1
+
+/**
+ * l2ip_meta_prof[2:0] = l2ip_meta[34:32], l2ip_meta_data[31:0] =
+ * l2ip_meta[31:0]
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_BITPOS 62
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_NUM_BITS 35
+
+/**
+ * Enables remap of action record pointer from Input block (for idx 1
+ * ...)
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_BITPOS 61
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_NUM_BITS 1
+
+/**
+ * l2ip_act_hint[1:0] = l2ip_act_data[32:31], l2ip_act_scope[4:0] =
+ * l2ip_act_data[30:26], l2ip_act_rec_ptr[25:0] = l2ip_act_data[25:0]
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_BITPOS 28
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_NUM_BITS 33
+
+/**
+ * Enables remap of ring_table_idx
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_BITPOS 27
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_NUM_BITS 1
+
+/**
+ * ring_table_idx[8:0] = l2ip_rfs_data[8:0] (rx only)
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_BITPOS 18
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_NUM_BITS 9
+
+/**
+ * Enables remap of destination from input block
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_BITPOS 17
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_NUM_BITS 1
+
+/**
+ * destination[16:0] = l2ip_dest_data[16:0] #CAS_SW_REF
+ * Profiler.l2ip.context.remap.table
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_BITPOS 0
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_NUM_BITS 17
+
+/**
+ * Total number of bits for PROF_L2_CTXT_RMP_DR
+ */
+#define CFA_P70_PROF_L2_CTXT_RMP_DR_TOTAL_NUM_BITS 127
+
+/**
+ * FC TCAM Search Result.
+ */
+#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_RESULT_BITPOS 0
+#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_RESULT_NUM_BITS 6
+
+/**
+ * Unused Field.
+ */
+#define CFA_P70_ACT_FC_TCAM_RESULT_UNUSED_0_BITPOS 6
+#define CFA_P70_ACT_FC_TCAM_RESULT_UNUSED_0_NUM_BITS 25
+
+/**
+ * FC TCAM Search Hit.
+ */
+#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_HIT_BITPOS 31
+#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_HIT_NUM_BITS 1
+
+/**
+ * Total number of bits for ACT_FC_TCAM_RESULT
+ */
+#define CFA_P70_ACT_FC_TCAM_RESULT_TOTAL_NUM_BITS 32
+
+/**
+ * Unused Field.
+ */
+#define CFA_P70_ACT_MIRROR_UNUSED_0_BITPOS 0
+#define CFA_P70_ACT_MIRROR_UNUSED_0_NUM_BITS 21
+#define CFA_P70_ACT_MIRROR_RELATIVE_BITPOS 21
+#define CFA_P70_ACT_MIRROR_RELATIVE_NUM_BITS 1
+/**
+ * RELATIVE
+ */
+enum cfa_p70_act_mirror_relative {
+ /* act_rec_ptr field is absolute. */
+ CFA_P70_ACT_MIRROR_RELATIVE_ABSOLUTE = 0,
+ /*
+ * act_rec_ptr field is relative to the original action record pointer.
+ */
+ CFA_P70_ACT_MIRROR_RELATIVE_RELATIVE = 1,
+};
+
+/**
+ * micr1_act_hint[1:0] - action hint used with act_rec_ptr.
+ */
+#define CFA_P70_ACT_MIRROR_HINT_BITPOS 22
+#define CFA_P70_ACT_MIRROR_HINT_NUM_BITS 2
+
+/**
+ * Sampling mode.
+ */
+#define CFA_P70_ACT_MIRROR_SAMP_BITPOS 24
+#define CFA_P70_ACT_MIRROR_SAMP_NUM_BITS 2
+/**
+ * Sampling mode.
+ */
+enum cfa_p70_act_mirror_samp {
+ /* PRNG based. */
+ CFA_P70_ACT_MIRROR_SAMP_STAT = 0,
+ /* packet count based. */
+ CFA_P70_ACT_MIRROR_SAMP_PACKET = 1,
+ /* packet count w/jitter based. */
+ CFA_P70_ACT_MIRROR_SAMP_JITTER = 2,
+ /* timer based. */
+ CFA_P70_ACT_MIRROR_SAMP_TIMER = 3,
+};
+
+/**
+ * Truncation mode.
+ */
+#define CFA_P70_ACT_MIRROR_TRUNC_BITPOS 26
+#define CFA_P70_ACT_MIRROR_TRUNC_NUM_BITS 2
+/**
+ * Truncation mode.
+ */
+enum cfa_p70_act_mirror_trunc {
+ /* No Truncation. */
+ CFA_P70_ACT_MIRROR_TRUNC_DISABLED = 0,
+ /* RFFU. */
+ CFA_P70_ACT_MIRROR_TRUNC_RSVD = 1,
+ /* mirror copy will restrict outermost tunnel payload to 128B. */
+ CFA_P70_ACT_MIRROR_TRUNC_B128 = 2,
+ /* mirror copy will restrict outermost tunnel payload to 256B. */
+ CFA_P70_ACT_MIRROR_TRUNC_B256 = 3,
+};
+#define CFA_P70_ACT_MIRROR_IGN_DROP_BITPOS 28
+#define CFA_P70_ACT_MIRROR_IGN_DROP_NUM_BITS 1
+/**
+ * IGN_DROP
+ */
+enum cfa_p70_act_mirror_ign_drop {
+ /*
+ * Honor Drop When set the mirror copy is made regardless if the initial
+ * action is to drop the packet or not.
+ */
+ CFA_P70_ACT_MIRROR_IGN_DROP_HONOR = 0,
+ /* Ignore Drop */
+ CFA_P70_ACT_MIRROR_IGN_DROP_IGNORE = 1,
+};
+#define CFA_P70_ACT_MIRROR_MODE_BITPOS 29
+#define CFA_P70_ACT_MIRROR_MODE_NUM_BITS 2
+/**
+ * MODE
+ */
+enum cfa_p70_act_mirror_mode {
+ /* No Copy. */
+ CFA_P70_ACT_MIRROR_MODE_DISABLED = 0,
+ /* Override AR. */
+ CFA_P70_ACT_MIRROR_MODE_OVERRIDE = 1,
+ /* Ingress Copy. */
+ CFA_P70_ACT_MIRROR_MODE_INGRESS = 2,
+ /* Egress Copy. */
+ CFA_P70_ACT_MIRROR_MODE_EGRESS = 3,
+};
+#define CFA_P70_ACT_MIRROR_COND_BITPOS 31
+#define CFA_P70_ACT_MIRROR_COND_NUM_BITS 1
+/**
+ * COND
+ */
+enum cfa_p70_act_mirror_cond {
+ /* mirror is only processed if Lookup copy bit is set */
+ CFA_P70_ACT_MIRROR_COND_UNCONDITIONAL = 0,
+ /* mirror is processed unconditionally. */
+ CFA_P70_ACT_MIRROR_COND_CONDITIONAL = 1,
+};
+
+/**
+ * Mirror Destination 1 Action Record Pointer.
+ */
+#define CFA_P70_ACT_MIRROR_AR_PTR_BITPOS 32
+#define CFA_P70_ACT_MIRROR_AR_PTR_NUM_BITS 26
+
+/**
+ * Mirror Destination 1 Sampling Conifiguration.
+ */
+#define CFA_P70_ACT_MIRROR_SAMP_CFG_BITPOS 64
+#define CFA_P70_ACT_MIRROR_SAMP_CFG_NUM_BITS 32
+
+/**
+ * Total number of bits for ACT_MIRROR
+ */
+#define CFA_P70_ACT_MIRROR_TOTAL_NUM_BITS 96
+
+/**
+ * This is the new medadata that is merged with the existing packet
+ * metadata, based on the profile selected by META_PROF.
+ */
+#define CFA_P70_WC_LREC_METADATA_BITPOS 5
+#define CFA_P70_WC_LREC_METADATA_NUM_BITS 32
+
+/**
+ * Specifies one of 8 metadata profile masks to use when merging the
+ * input metadata with the LREC metadata for recycling.
+ */
+#define CFA_P70_WC_LREC_META_PROF_BITPOS 37
+#define CFA_P70_WC_LREC_META_PROF_NUM_BITS 3
+
+/**
+ * When a packet is recycled to the Profile TCAM, this value is used as
+ * the PROF_FUNC field in the TCAM search.
+ */
+#define CFA_P70_WC_LREC_PROF_FUNC_BITPOS 40
+#define CFA_P70_WC_LREC_PROF_FUNC_NUM_BITS 8
+
+/**
+ * Indicates whether the packet will be recycled to the L2 Context TCAM,
+ * the Profile TCAM. When to the Profile TCAM, PROF_FUNC is used for the
+ * search key.
+ */
+#define CFA_P70_WC_LREC_RECYCLE_DEST_BITPOS 48
+#define CFA_P70_WC_LREC_RECYCLE_DEST_NUM_BITS 1
+
+/**
+ * Flow counter pointer.
+ */
+#define CFA_P70_WC_LREC_FC_PTR_BITPOS 0
+#define CFA_P70_WC_LREC_FC_PTR_NUM_BITS 28
+
+/**
+ * Flow counter type.
+ */
+#define CFA_P70_WC_LREC_FC_TYPE_BITPOS 28
+#define CFA_P70_WC_LREC_FC_TYPE_NUM_BITS 2
+
+/**
+ * Flow counter op.
+ */
+#define CFA_P70_WC_LREC_FC_OP_BITPOS 30
+#define CFA_P70_WC_LREC_FC_OP_NUM_BITS 1
+/**
+ * Enumeration definition for field 'fc_op'
+ */
+enum cfa_p70_wc_lrec_fc_op {
+ /* ingress */
+ CFA_P70_WC_LREC_FC_OP_INGRESS = 0,
+ /* egress */
+ CFA_P70_WC_LREC_FC_OP_EGRESS = 1,
+};
+
+/**
+ * When not present, a value of 0 is used which disables ECMP. The final
+ * action record location is: ! ACT_REC_PTR += (ECMP_HASH % PATHS_M1 +
+ * 1)) * ACT_REC_SIZE
+ */
+#define CFA_P70_WC_LREC_PATHS_M1_BITPOS 31
+#define CFA_P70_WC_LREC_PATHS_M1_NUM_BITS 4
+
+/**
+ * Specifies the size in 32B units of the action memory allocated for
+ * each ECMP path.
+ */
+#define CFA_P70_WC_LREC_ACT_REC_SIZE_BITPOS 35
+#define CFA_P70_WC_LREC_ACT_REC_SIZE_NUM_BITS 5
+
+/**
+ * This field is used in flow steering applications such as Linux RFS.
+ * This field is used in conjunction with the VNIC destination in the
+ * action record on RX to steer the packet to a specific ring.
+ */
+#define CFA_P70_WC_LREC_RING_TABLE_IDX_BITPOS 40
+#define CFA_P70_WC_LREC_RING_TABLE_IDX_NUM_BITS 9
+
+/**
+ * This field provides a destination for the packet, which goes directly
+ * to the output of CFA.
+ */
+#define CFA_P70_WC_LREC_DESTINATION_BITPOS 49
+#define CFA_P70_WC_LREC_DESTINATION_NUM_BITS 17
+
+/**
+ * This is the action record pointer. This value points into the current
+ * scope action table. Not that when ACT_REC_SIZE and PATHS_M1 are
+ * preset and PATHS_M1 != 0, the value may be modified using this as the
+ * base pointer for ECMP.
+ */
+#define CFA_P70_WC_LREC_ACT_REC_PTR_BITPOS 49
+#define CFA_P70_WC_LREC_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This value provides a hit of the action record size to the Action
+ * block.
+ */
+#define CFA_P70_WC_LREC_ACT_HINT_BITPOS 75
+#define CFA_P70_WC_LREC_ACT_HINT_NUM_BITS 2
+
+/**
+ * When both WC and EM have a hit, the one with the higher STRENGTH is
+ * used. If the STRENGTHs are equal, the LKUP_TIE_BREAKER register bit
+ * determines the winner. (0=WC, 1=EM)
+ */
+#define CFA_P70_WC_LREC_STRENGTH_BITPOS 77
+#define CFA_P70_WC_LREC_STRENGTH_NUM_BITS 2
+
+/**
+ * This field defines the format for the LREC and the basic thing that
+ * will be done with the packet.
+ */
+#define CFA_P70_WC_LREC_OPCODE_BITPOS 79
+#define CFA_P70_WC_LREC_OPCODE_NUM_BITS 4
+/**
+ * Enumeration definition for field 'opcode'
+ */
+enum cfa_p70_wc_lrec_opcode {
+ /*
+ * This value means the packet will go to the action block for edit
+ * processing and that no RFS will be specified for the packet.
+ */
+ CFA_P70_WC_LREC_OPCODE_NORMAL = 0,
+ /*
+ * This value means the packet will go to the action block for edit
+ * processing and that RFS will be specified for the packet.
+ */
+ CFA_P70_WC_LREC_OPCODE_NORMAL_RFS = 1,
+ /*
+ * This value means the packet will go directly to the output, bypassing
+ * the action block and that no RFS will be specified for the packet.
+ */
+ CFA_P70_WC_LREC_OPCODE_FAST = 2,
+ /*
+ * This value means the packet will go directly to the output, bypassing
+ * the action block and that RFS will be specified for the packet.
+ */
+ CFA_P70_WC_LREC_OPCODE_FAST_RFS = 3,
+ /*
+ * This value Recycles the packet to the Profiler and provides LREC
+ * fields that determine the fields returned to the Profiler for further
+ * processing.
+ */
+ CFA_P70_WC_LREC_OPCODE_RECYCLE = 8,
+};
+
+/**
+ * In addition to requiring VALID=1, the bits indexed by epoch1 must be
+ * set to '1' in the EPOCH1_MASK table, or the LREC is invalid. This is
+ * used to invalidate rules as a group.
+ */
+#define CFA_P70_WC_LREC_EPOCH1_BITPOS 83
+#define CFA_P70_WC_LREC_EPOCH1_NUM_BITS 6
+
+/**
+ * In addition to requiring VALID=1, the bits indexed by epoch0 must be
+ * set to '1' in the EPOCH0_MASK table, or the LREC is invalid. This is
+ * used to invalidate rules as a group.
+ */
+#define CFA_P70_WC_LREC_EPOCH0_BITPOS 89
+#define CFA_P70_WC_LREC_EPOCH0_NUM_BITS 12
+
+/**
+ * Record size in 32B words minus 1 (ignored by hardware).
+ */
+#define CFA_P70_WC_LREC_REC_SIZE_BITPOS 101
+#define CFA_P70_WC_LREC_REC_SIZE_NUM_BITS 2
+
+/**
+ * When set to '0', the LREC is not valid.
+ */
+#define CFA_P70_WC_LREC_VALID_BITPOS 103
+#define CFA_P70_WC_LREC_VALID_NUM_BITS 1
+
+/**
+ * Total number of bits for wc_lrec
+ */
+#define CFA_P70_WC_LREC_TOTAL_NUM_BITS 104
+
+/**
+ * This value provides a base pointer to the LKUP_FRC_RANGE memory. Each
+ * packet can have up to 16 ranges. A value of 16'hFFFF disables FRC.
+ */
+#define CFA_P70_EM_LREC_RANGE_IDX_BITPOS 0
+#define CFA_P70_EM_LREC_RANGE_IDX_NUM_BITS 16
+
+/**
+ * Selects one of 16 profiles for FRC in the LKUP_RANGE_PROFILE table,
+ * which specifies 2 packet fields to range check and gives a mask of 16
+ * ranges determined by range_index.
+ */
+#define CFA_P70_EM_LREC_RANGE_PROFILE_BITPOS 16
+#define CFA_P70_EM_LREC_RANGE_PROFILE_NUM_BITS 4
+
+/**
+ * Current timer value for the connection.
+ */
+#define CFA_P70_EM_LREC_CREC_TIMER_VALUE_BITPOS 20
+#define CFA_P70_EM_LREC_CREC_TIMER_VALUE_NUM_BITS 4
+
+/**
+ * Current state of the connection.
+ */
+#define CFA_P70_EM_LREC_CREC_STATE_BITPOS 24
+#define CFA_P70_EM_LREC_CREC_STATE_NUM_BITS 5
+
+/**
+ * Set to one by hardware whenever a notify of a valid tcp_msb_opp has
+ * been written into the connection record. Software can also initialize
+ * this to one if it initializes tcp_msb_opp to a valid value.
+ */
+#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_INIT_BITPOS 29
+#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_INIT_NUM_BITS 1
+
+/**
+ * Bits 31:14 of seq# or ack# as seen in packets on the opposite path.
+ */
+#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_BITPOS 30
+#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_NUM_BITS 18
+
+/**
+ * Bits 31:14 of seq# or ack# as seen in packets on the local path.
+ */
+#define CFA_P70_EM_LREC_CREC_TCP_MSB_LOC_BITPOS 48
+#define CFA_P70_EM_LREC_CREC_TCP_MSB_LOC_NUM_BITS 18
+
+/**
+ * Window size is 1<<TCP_WIN. A value of 0 disables window checks. Only
+ * modified by SW.
+ */
+#define CFA_P70_EM_LREC_CREC_TCP_WIN_BITPOS 66
+#define CFA_P70_EM_LREC_CREC_TCP_WIN_NUM_BITS 5
+
+/**
+ * Enables update of TCP_MSB_LOC when '1'. Only modified by SW.
+ */
+#define CFA_P70_EM_LREC_CREC_TCP_UPDT_EN_BITPOS 71
+#define CFA_P70_EM_LREC_CREC_TCP_UPDT_EN_NUM_BITS 1
+
+/**
+ * Direction of tracked connection. Only modified by SW.
+ */
+#define CFA_P70_EM_LREC_CREC_TCP_DIR_BITPOS 72
+#define CFA_P70_EM_LREC_CREC_TCP_DIR_NUM_BITS 1
+/**
+ * Enumeration definition for field 'crec_tcp_dir'
+ */
+enum cfa_p70_em_lrec_crec_tcp_dir {
+ /* RX */
+ CFA_P70_EM_LREC_CREC_TCP_DIR_RX = 0,
+ /* TX */
+ CFA_P70_EM_LREC_CREC_TCP_DIR_TX = 1,
+};
+
+/**
+ * This is the new medadata that is merged with the existing packet
+ * metadata, based on the profile selected by META_PROF.
+ */
+#define CFA_P70_EM_LREC_METADATA_BITPOS 29
+#define CFA_P70_EM_LREC_METADATA_NUM_BITS 32
+
+/**
+ * When a packet is recycled to the Profile TCAM, this value is used as
+ * the PROF_FUNC field in the TCAM search.
+ */
+#define CFA_P70_EM_LREC_PROF_FUNC_BITPOS 61
+#define CFA_P70_EM_LREC_PROF_FUNC_NUM_BITS 8
+
+/**
+ * Specifies one of 8 metadata profile masks to use when merging the
+ * input metadata with the LREC metadata for recycling.
+ */
+#define CFA_P70_EM_LREC_META_PROF_BITPOS 69
+#define CFA_P70_EM_LREC_META_PROF_NUM_BITS 3
+
+/**
+ * Indicates whether the packet will be recycled to the L2 Context TCAM,
+ * the Profile TCAM. When to the Profile TCAM, PROF_FUNC is used for the
+ * search key.
+ */
+#define CFA_P70_EM_LREC_RECYCLE_DEST_BITPOS 72
+#define CFA_P70_EM_LREC_RECYCLE_DEST_NUM_BITS 1
+
+/**
+ * Flow counter pointer.
+ */
+#define CFA_P70_EM_LREC_FC_PTR_BITPOS 24
+#define CFA_P70_EM_LREC_FC_PTR_NUM_BITS 28
+
+/**
+ * Flow counter type.
+ */
+#define CFA_P70_EM_LREC_FC_TYPE_BITPOS 52
+#define CFA_P70_EM_LREC_FC_TYPE_NUM_BITS 2
+
+/**
+ * Flow counter op.
+ */
+#define CFA_P70_EM_LREC_FC_OP_BITPOS 54
+#define CFA_P70_EM_LREC_FC_OP_NUM_BITS 1
+/**
+ * Enumeration definition for field 'fc_op'
+ */
+enum cfa_p70_em_lrec_fc_op {
+ /* ingress */
+ CFA_P70_EM_LREC_FC_OP_INGRESS = 0,
+ /* egress */
+ CFA_P70_EM_LREC_FC_OP_EGRESS = 1,
+};
+
+/**
+ * When not present, a value of 0 is used which disables ECMP. The final
+ * action record location is: ! ACT_REC_PTR += (ECMP_HASH % PATHS_M1 +
+ * 1)) * ACT_REC_SIZE
+ */
+#define CFA_P70_EM_LREC_PATHS_M1_BITPOS 55
+#define CFA_P70_EM_LREC_PATHS_M1_NUM_BITS 4
+
+/**
+ * Specifies the size in 32B units of the action memory allocated for
+ * each ECMP path.
+ */
+#define CFA_P70_EM_LREC_ACT_REC_SIZE_BITPOS 59
+#define CFA_P70_EM_LREC_ACT_REC_SIZE_NUM_BITS 5
+
+/**
+ * This field is used in flow steering applications such as Linux RFS.
+ * This field is used in conjunction with the VNIC destination in the
+ * action record on RX to steer the packet to a specific ring.
+ */
+#define CFA_P70_EM_LREC_RING_TABLE_IDX_BITPOS 64
+#define CFA_P70_EM_LREC_RING_TABLE_IDX_NUM_BITS 9
+
+/**
+ * This field provides a destination for the packet, which goes directly
+ * to the output of CFA.
+ */
+#define CFA_P70_EM_LREC_DESTINATION_BITPOS 73
+#define CFA_P70_EM_LREC_DESTINATION_NUM_BITS 17
+
+/**
+ * This is the action record pointer. This value points into the current
+ * scope action table. Not that when ACT_REC_SIZE and PATHS_M1 are
+ * preset and PATHS_M1 != 0, the value may be modified using this as the
+ * base pointer for ECMP.
+ */
+#define CFA_P70_EM_LREC_ACT_REC_PTR_BITPOS 73
+#define CFA_P70_EM_LREC_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This value provides a hit of the action record size to the Action
+ * block.
+ */
+#define CFA_P70_EM_LREC_ACT_HINT_BITPOS 99
+#define CFA_P70_EM_LREC_ACT_HINT_NUM_BITS 2
+
+/**
+ * When both WC and EM have a hit, the one with the higher STRENGTH is
+ * used. If the STRENGTHs are equal, the LKUP_TIE_BREAKER register bit
+ * determines the winner. (0=WC, 1=EM)
+ */
+#define CFA_P70_EM_LREC_STRENGTH_BITPOS 101
+#define CFA_P70_EM_LREC_STRENGTH_NUM_BITS 2
+
+/**
+ * This field defines the format for the LREC and the basic thing that
+ * will be done with the packet.
+ */
+#define CFA_P70_EM_LREC_OPCODE_BITPOS 103
+#define CFA_P70_EM_LREC_OPCODE_NUM_BITS 4
+/**
+ * Enumeration definition for field 'opcode'
+ */
+enum cfa_p70_em_lrec_opcode {
+ /*
+ * This value means the packet will go to the action block for edit
+ * processing and that no RFS will be specified for the packet.
+ */
+ CFA_P70_EM_LREC_OPCODE_NORMAL = 0,
+ /*
+ * This value means the packet will go to the action block for edit
+ * processing and that RFS will be specified for the packet.
+ */
+ CFA_P70_EM_LREC_OPCODE_NORMAL_RFS = 1,
+ /*
+ * This value means the packet will go directly to the output, bypassing
+ * the action block and that no RFS will be specified for the packet.
+ */
+ CFA_P70_EM_LREC_OPCODE_FAST = 2,
+ /*
+ * This value means the packet will go directly to the output, bypassing
+ * the action block and that RFS will be specified for the packet.
+ */
+ CFA_P70_EM_LREC_OPCODE_FAST_RFS = 3,
+ /*
+ * This means the packet will go to the action block, but will have
+ * connection tracking affect the action, but no RFS. Connection
+ * tracking determines the ACTION, which is forward, miss, or copy. The
+ * default action record pointer is used when ACTION=miss.
+ */
+ CFA_P70_EM_LREC_OPCODE_CT_MISS_DEF = 4,
+ /*
+ * This means the packet will go to the action block, but will have
+ * connection tracking affect the action, but no RFS. Connection
+ * tracking determines the ACTION, which is forward, miss, or copy. The
+ * default action record pointer is used when ACTION=forward or
+ * ACTION=copy.
+ */
+ CFA_P70_EM_LREC_OPCODE_CT_HIT_DEF = 6,
+ /*
+ * This value Recycles the packet to the Profiler and provides LREC
+ * fields that determine the fields returned to the Profiler for further
+ * processing.
+ */
+ CFA_P70_EM_LREC_OPCODE_RECYCLE = 8,
+};
+
+/**
+ * In addition to requiring VALID=1, the bits indexed by epoch1 must be
+ * set to '1' in the EPOCH1_MASK table, or the LREC is invalid. This is
+ * used to invalidate rules as a group.
+ */
+#define CFA_P70_EM_LREC_EPOCH1_BITPOS 107
+#define CFA_P70_EM_LREC_EPOCH1_NUM_BITS 6
+
+/**
+ * In addition to requiring VALID=1, the bits indexed by epoch0 must be
+ * set to '1' in the EPOCH0_MASK table, or the LREC is invalid. This is
+ * used to invalidate rules as a group.
+ */
+#define CFA_P70_EM_LREC_EPOCH0_BITPOS 113
+#define CFA_P70_EM_LREC_EPOCH0_NUM_BITS 12
+
+/**
+ * Record size in 32B words minus 1 (ignored by hardware).
+ */
+#define CFA_P70_EM_LREC_REC_SIZE_BITPOS 125
+#define CFA_P70_EM_LREC_REC_SIZE_NUM_BITS 2
+
+/**
+ * When set to '0', the LREC is not valid.
+ */
+#define CFA_P70_EM_LREC_VALID_BITPOS 127
+#define CFA_P70_EM_LREC_VALID_NUM_BITS 1
+
+/**
+ * Total number of bits for em_lrec
+ */
+#define CFA_P70_EM_LREC_TOTAL_NUM_BITS 128
+
+/**
+ * This entry points to the entry associated with this bucket area. If
+ * this value is zero, then the bucket area is not valid and should be
+ * skipped.
+ */
+#define CFA_P70_EM_BUCKET_BIN0_ENTRY_BITPOS 0
+#define CFA_P70_EM_BUCKET_BIN0_ENTRY_NUM_BITS 26
+
+/**
+ * This field holds the upper 12 bits of the 36b spooky hash of the key.
+ * This part of the bucket area must match for the entry associated with
+ * the bucket area to be read.
+ */
+#define CFA_P70_EM_BUCKET_BIN0_HASH_MSBS_BITPOS 26
+#define CFA_P70_EM_BUCKET_BIN0_HASH_MSBS_NUM_BITS 12
+
+/**
+ * This entry points to the entry associated with this bucket area. If
+ * this value is zero, then the bucket area is not valid and should be
+ * skipped.
+ */
+#define CFA_P70_EM_BUCKET_BIN1_ENTRY_BITPOS 38
+#define CFA_P70_EM_BUCKET_BIN1_ENTRY_NUM_BITS 26
+
+/**
+ * This field holds the upper 12 bits of the 36b spooky hash of the key.
+ * This part of the bucket area must match for the entry associated with
+ * the bucket area to be read.
+ */
+#define CFA_P70_EM_BUCKET_BIN1_HASH_MSBS_BITPOS 64
+#define CFA_P70_EM_BUCKET_BIN1_HASH_MSBS_NUM_BITS 12
+
+/**
+ * This entry points to the entry associated with this bucket area. If
+ * this value is zero, then the bucket area is not valid and should be
+ * skipped.
+ */
+#define CFA_P70_EM_BUCKET_BIN2_ENTRY_BITPOS 76
+#define CFA_P70_EM_BUCKET_BIN2_ENTRY_NUM_BITS 26
+
+/**
+ * This field holds the upper 12 bits of the 36b spooky hash of the key.
+ * This part of the bucket area must match for the entry associated with
+ * the bucket area to be read.
+ */
+#define CFA_P70_EM_BUCKET_BIN2_HASH_MSBS_BITPOS 102
+#define CFA_P70_EM_BUCKET_BIN2_HASH_MSBS_NUM_BITS 12
+
+/**
+ * This entry points to the entry associated with this bucket area. If
+ * this value is zero, then the bucket area is not valid and should be
+ * skipped.
+ */
+#define CFA_P70_EM_BUCKET_BIN3_ENTRY_BITPOS 114
+#define CFA_P70_EM_BUCKET_BIN3_ENTRY_NUM_BITS 26
+
+/**
+ * This field holds the upper 12 bits of the 36b spooky hash of the key.
+ * This part of the bucket area must match for the entry associated with
+ * the bucket area to be read.
+ */
+#define CFA_P70_EM_BUCKET_BIN3_HASH_MSBS_BITPOS 140
+#define CFA_P70_EM_BUCKET_BIN3_HASH_MSBS_NUM_BITS 12
+
+/**
+ * This entry points to the entry associated with this bucket area. If
+ * this value is zero, then the bucket area is not valid and should be
+ * skipped.
+ */
+#define CFA_P70_EM_BUCKET_BIN4_ENTRY_BITPOS 152
+#define CFA_P70_EM_BUCKET_BIN4_ENTRY_NUM_BITS 26
+
+/**
+ * This field holds the upper 12 bits of the 36b spooky hash of the key.
+ * This part of the bucket area must match for the entry associated with
+ * the bucket area to be read.
+ */
+#define CFA_P70_EM_BUCKET_BIN4_HASH_MSBS_BITPOS 178
+#define CFA_P70_EM_BUCKET_BIN4_HASH_MSBS_NUM_BITS 12
+
+/**
+ * This entry points to the entry associated with this bucket area. If
+ * this value is zero, then the bucket area is not valid and should be
+ * skipped.
+ */
+#define CFA_P70_EM_BUCKET_BIN5_ENTRY_BITPOS 190
+#define CFA_P70_EM_BUCKET_BIN5_ENTRY_NUM_BITS 26
+
+/**
+ * This field holds the upper 12 bits of the 36b spooky hash of the key.
+ * This part of the bucket area must match for the entry associated with
+ * the bucket area to be read.
+ */
+#define CFA_P70_EM_BUCKET_BIN5_HASH_MSBS_BITPOS 216
+#define CFA_P70_EM_BUCKET_BIN5_HASH_MSBS_NUM_BITS 12
+
+/**
+ * This value points to the next bucket in the chain. When set to 0, the
+ * next bucket visit for a background thread is to the starting bucket
+ * for the thread.
+ */
+#define CFA_P70_EM_BUCKET_CHAIN_POINTER_BITPOS 228
+#define CFA_P70_EM_BUCKET_CHAIN_POINTER_NUM_BITS 26
+
+/**
+ * If this value is '1', then the pointer value must be valid and will
+ * be followed if a key match is not found in any bin in the current
+ * bucket.
+ */
+#define CFA_P70_EM_BUCKET_CHAIN_VALID_BITPOS 254
+#define CFA_P70_EM_BUCKET_CHAIN_VALID_NUM_BITS 1
+
+/**
+ * Total number of bits for em_bucket
+ */
+#define CFA_P70_EM_BUCKET_TOTAL_NUM_BITS 255
+
+/**
+ * The type field identifies the format of the action record to the
+ * hardware.
+ */
+#define CFA_P70_COMPACT_ACTION_TYPE_BITPOS 0
+#define CFA_P70_COMPACT_ACTION_TYPE_NUM_BITS 3
+/**
+ * Enumeration definition for field 'type'
+ */
+enum cfa_p70_compact_action_type {
+ /*
+ * Compact Action Record. The compact action record uses relative
+ * pointers to access needed data. This keeps the compact action record
+ * down to 64b.
+ */
+ CFA_P70_COMPACT_ACTION_TYPE_COMPACT_ACTION = 0,
+};
+
+/**
+ * When this value is '1', the packet will be dropped.
+ */
+#define CFA_P70_COMPACT_ACTION_DROP_BITPOS 3
+#define CFA_P70_COMPACT_ACTION_DROP_NUM_BITS 1
+
+/**
+ * This value controls how the VLAN Delete/Report edit works.
+ */
+#define CFA_P70_COMPACT_ACTION_VLAN_DELETE_BITPOS 4
+#define CFA_P70_COMPACT_ACTION_VLAN_DELETE_NUM_BITS 2
+/**
+ * Enumeration definition for field 'vlan_delete'
+ */
+enum cfa_p70_compact_action_vlan_delete {
+ /* The VLAN tag is left alone. */
+ CFA_P70_COMPACT_ACTION_VLAN_DELETE_DISABLED = 0,
+ /* Strip/Report the outer VLAN tag. Leave the inner VLAN tag. */
+ CFA_P70_COMPACT_ACTION_VLAN_DELETE_OUTER = 1,
+ /*
+ * Strip both the outer and inner VLAN tag. Report the inner VLAN tag.
+ */
+ CFA_P70_COMPACT_ACTION_VLAN_DELETE_BOTH = 2,
+ /*
+ * If the outer VID != 0, strip and pass the outer VLAG tag and leave
+ * the inner VLAN tag. If outer VID == 0, then strip both VLAN tags and
+ * report the inner VLAN tag.
+ */
+ CFA_P70_COMPACT_ACTION_VLAN_DELETE_COND = 3,
+};
+
+/**
+ * This value specifies the port destination mask for TX path and is the
+ * index into the VNIC Properties Table for the RX path.
+ */
+#define CFA_P70_COMPACT_ACTION_DEST_BITPOS 6
+#define CFA_P70_COMPACT_ACTION_DEST_NUM_BITS 7
+#define CFA_P70_COMPACT_ACTION_DEST_OP_BITPOS 17
+#define CFA_P70_COMPACT_ACTION_DEST_OP_NUM_BITS 2
+/**
+ * Enumeration definition for field 'dest_op'
+ */
+enum cfa_p70_compact_action_dest_op {
+ /* Use the dest field from the Action Record. */
+ CFA_P70_COMPACT_ACTION_DEST_OP_NORMAL = 0,
+ /*
+ * This value specifies that the default destination as determined by
+ * the Profiler/Lookup/MCG stages and passed into the Action Record
+ * Fetch should be used instead of the destination from the Action
+ * Record. For example this can be useful for applications where actions
+ * are desired on a packet but the destination is to be taken solely
+ * from the Profiler Input Lookup Table.
+ */
+ CFA_P70_COMPACT_ACTION_DEST_OP_DEFAULT = 1,
+ /*
+ * This value specifies that the lower order bits of the metadata should
+ * be used instead of the destination from the Action Record.
+ */
+ CFA_P70_COMPACT_ACTION_DEST_OP_METADATA = 2,
+};
+
+/**
+ * This field controls the decapsulation function for the action.
+ */
+#define CFA_P70_COMPACT_ACTION_DECAP_BITPOS 19
+#define CFA_P70_COMPACT_ACTION_DECAP_NUM_BITS 5
+/**
+ * Enumeration definition for field 'decap'
+ */
+enum cfa_p70_compact_action_decap {
+ /* Do nothing. */
+ CFA_P70_COMPACT_ACTION_DECAP_DISABLE = 0,
+ /* Decap the outer VLAN tag */
+ CFA_P70_COMPACT_ACTION_DECAP_OVLAN = 1,
+ /* Decap all the VLAN tags */
+ CFA_P70_COMPACT_ACTION_DECAP_ALL_VLAN = 2,
+ /* Decap through Tunnel L2 header */
+ CFA_P70_COMPACT_ACTION_DECAP_TO_TL2 = 3,
+ /* Decap 1 MPLS label (does not delete outer L2) */
+ CFA_P70_COMPACT_ACTION_DECAP_1MPLS = 4,
+ /* Decap 1 MPLS label and outer L2 */
+ CFA_P70_COMPACT_ACTION_DECAP_1MPLS_OL2 = 5,
+ /* Decap 2 MPLS labels (does not delete outer L2) */
+ CFA_P70_COMPACT_ACTION_DECAP_2MPLS = 6,
+ /* Decap 2 MPLS labels and outer L2 */
+ CFA_P70_COMPACT_ACTION_DECAP_2MPLS_OL2 = 7,
+ /* Decap through Tunnel L3 header */
+ CFA_P70_COMPACT_ACTION_DECAP_TO_TL3 = 8,
+ /* Decap through Tunnel L4 header */
+ CFA_P70_COMPACT_ACTION_DECAP_TO_TL4 = 9,
+ /* Decap through Tunnel header */
+ CFA_P70_COMPACT_ACTION_DECAP_TO_T = 10,
+ /* Decap through Inner L2 */
+ CFA_P70_COMPACT_ACTION_DECAP_TO_L2 = 11,
+ /* Decap through Inner L3 */
+ CFA_P70_COMPACT_ACTION_DECAP_TO_L3 = 12,
+ /* Decap through inner L4 */
+ CFA_P70_COMPACT_ACTION_DECAP_TO_L4 = 13,
+ /* Shift tunnel->inner (single shift) */
+ CFA_P70_COMPACT_ACTION_DECAP_SHIFT_SINGLE = 14,
+ /* Un-parse (treat header as payload) */
+ CFA_P70_COMPACT_ACTION_DECAP_UNPARSE = 15,
+ /* Shift outer tunnel->inner (double shift) */
+ CFA_P70_COMPACT_ACTION_DECAP_SHIFT_DOUBLE = 18,
+ /* Decap through Outer Tunnel L2 header */
+ CFA_P70_COMPACT_ACTION_DECAP_TO_OL2 = 20,
+ /* Decap through Outer Tunnel L3 header */
+ CFA_P70_COMPACT_ACTION_DECAP_TO_OL3 = 21,
+ /* Decap through Outer Tunnel L4 header */
+ CFA_P70_COMPACT_ACTION_DECAP_TO_OL4 = 22,
+ /* Decap through Outer Tunnel header */
+ CFA_P70_COMPACT_ACTION_DECAP_TO_OT = 23,
+};
+
+/**
+ * The mirroring value selects one of 31 mirror destinations for the
+ * packet. A value of zero means that there is not Action Record
+ * mirroring for the packet.
+ */
+#define CFA_P70_COMPACT_ACTION_MIRRORING_BITPOS 24
+#define CFA_P70_COMPACT_ACTION_MIRRORING_NUM_BITS 5
+
+/**
+ * This value points to one of the 1024 meter entries. If the meter has
+ * scope verification enabled, then the scope in the meter table entry
+ * must match the scope of this action record.
+ */
+#define CFA_P70_COMPACT_ACTION_METER_PTR_BITPOS 29
+#define CFA_P70_COMPACT_ACTION_METER_PTR_NUM_BITS 10
+
+/**
+ * This is the offset to the statistic structure in 8B units from the
+ * start of the Action Record. A value of zero will disable the
+ * statistics action.
+ */
+#define CFA_P70_COMPACT_ACTION_STAT0_OFF_BITPOS 39
+#define CFA_P70_COMPACT_ACTION_STAT0_OFF_NUM_BITS 3
+
+/**
+ * This value controls the packet size that is used for counted stats.
+ */
+#define CFA_P70_COMPACT_ACTION_STAT0_OP_BITPOS 42
+#define CFA_P70_COMPACT_ACTION_STAT0_OP_NUM_BITS 1
+/**
+ * Enumeration definition for field 'stat0_op'
+ */
+enum cfa_p70_compact_action_stat0_op {
+ /* Statistics count reflects packet at 'ingress' to CFA. */
+ CFA_P70_COMPACT_ACTION_STAT0_OP_INGRESS = 0,
+ /* Statistics count reflects packet at 'egress' from CFA. */
+ CFA_P70_COMPACT_ACTION_STAT0_OP_EGRESS = 1,
+};
+
+/**
+ * Selects counter type. In all cases, fields are packet little endian
+ * in the action memory.
+ */
+#define CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_BITPOS 43
+#define CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_NUM_BITS 2
+/**
+ * Enumeration definition for field 'stat0_ctr_type'
+ */
+enum cfa_p70_compact_action_stat0_ctr_type {
+ /* Forward packet count(64b)/byte count(64b) */
+ CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B16 = 0,
+ /*
+ * Forward packet count(64b)/byte count(64b) timestamp(32b) TCP
+ * Flags(16b) reserved(23b)
+ */
+ CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B24 = 1,
+ /*
+ * Forward packet count(64b)/byte count(64b) Meter (drop or red) packet
+ * count(64b)/byte count(64b)
+ */
+ CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B32A = 2,
+ /*
+ * Forward packet count(64b)/byte count(64b) Meter timestamp(32b) TCP
+ * Flags(16b) reserved(6b) (drop or red) packet count(38b)/byte
+ * count(42b)
+ */
+ CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B32B = 3,
+};
+
+/**
+ * This is an offset to the modification record. This is the offset in
+ * 8B units from the start of the Action Record to get to dependent
+ * record data. A value of zero indicates no additional actions.
+ */
+#define CFA_P70_COMPACT_ACTION_MOD_OFF_BITPOS 45
+#define CFA_P70_COMPACT_ACTION_MOD_OFF_NUM_BITS 5
+
+/**
+ * This is an offset to the encapsulation record. This is the offset in
+ * 8B units from the start of the Action Record to get to dependent
+ * record data. A value of zero indicates no additional actions.
+ */
+#define CFA_P70_COMPACT_ACTION_ENC_OFF_BITPOS 50
+#define CFA_P70_COMPACT_ACTION_ENC_OFF_NUM_BITS 6
+
+/**
+ * This is an offset to the source record. This is the offset in 8B
+ * units from the start of the Action Record to get to dependent record
+ * data. A value of zero indicates no additional actions.
+ */
+#define CFA_P70_COMPACT_ACTION_SRC_OFF_BITPOS 56
+#define CFA_P70_COMPACT_ACTION_SRC_OFF_NUM_BITS 4
+#define CFA_P70_COMPACT_ACTION_UNUSED_0_BITPOS 60
+#define CFA_P70_COMPACT_ACTION_UNUSED_0_NUM_BITS 4
+
+/**
+ * Total number of bits for compact_action
+ */
+#define CFA_P70_COMPACT_ACTION_TOTAL_NUM_BITS 64
+
+/**
+ * The type field identifies the format of the action record to the
+ * hardware.
+ */
+#define CFA_P70_FULL_ACTION_TYPE_BITPOS 0
+#define CFA_P70_FULL_ACTION_TYPE_NUM_BITS 3
+/**
+ * Enumeration definition for field 'type'
+ */
+enum cfa_p70_full_action_type {
+ /*
+ * Full Action Record. The full action record uses full pointers to
+ * access needed data. It also allows access to all the action features.
+ * The Full Action record is 192b.
+ */
+ CFA_P70_FULL_ACTION_TYPE_FULL_ACTION = 1,
+};
+
+/**
+ * When this value is '1', the packet will be dropped.
+ */
+#define CFA_P70_FULL_ACTION_DROP_BITPOS 3
+#define CFA_P70_FULL_ACTION_DROP_NUM_BITS 1
+
+/**
+ * This value controls how the VLAN Delete/Report edit works.
+ */
+#define CFA_P70_FULL_ACTION_VLAN_DELETE_BITPOS 4
+#define CFA_P70_FULL_ACTION_VLAN_DELETE_NUM_BITS 2
+/**
+ * Enumeration definition for field 'vlan_delete'
+ */
+enum cfa_p70_full_action_vlan_delete {
+ /* The VLAN tag is left alone. */
+ CFA_P70_FULL_ACTION_VLAN_DELETE_DISABLED = 0,
+ /* Strip/Report the outer VLAN tag. Leave the inner VLAN tag. */
+ CFA_P70_FULL_ACTION_VLAN_DELETE_OUTER = 1,
+ /*
+ * Strip both the outer and inner VLAN tag. Report the inner VLAN tag.
+ */
+ CFA_P70_FULL_ACTION_VLAN_DELETE_BOTH = 2,
+ /*
+ * If the outer VID != 0, strip and pass the outer VLAG tag and leave
+ * the inner VLAN tag. If outer VID == 0, then strip both VLAN tags and
+ * report the inner VLAN tag.
+ */
+ CFA_P70_FULL_ACTION_VLAN_DELETE_COND = 3,
+};
+
+/**
+ * This value specifies the port destination mask for TX path and is the
+ * index into the VNIC Properties Table for the RX path.
+ */
+#define CFA_P70_FULL_ACTION_DEST_BITPOS 6
+#define CFA_P70_FULL_ACTION_DEST_NUM_BITS 7
+#define CFA_P70_FULL_ACTION_DEST_OP_BITPOS 17
+#define CFA_P70_FULL_ACTION_DEST_OP_NUM_BITS 2
+/**
+ * Enumeration definition for field 'dest_op'
+ */
+enum cfa_p70_full_action_dest_op {
+ /* Use the dest field from the Action Record. */
+ CFA_P70_FULL_ACTION_DEST_OP_NORMAL = 0,
+ /*
+ * This value specifies that the default destination as determined by
+ * the Profiler/Lookup/MCG stages and passed into the Action Record
+ * Fetch should be used instead of the destination from the Action
+ * Record. For example this can be useful for applications where actions
+ * are desired on a packet but the destination is to be taken solely
+ * from the Profiler Input Lookup Table.
+ */
+ CFA_P70_FULL_ACTION_DEST_OP_DEFAULT = 1,
+ /*
+ * This value specifies that the lower order bits of the metadata should
+ * be used instead of the destination from the Action Record.
+ */
+ CFA_P70_FULL_ACTION_DEST_OP_METADATA = 2,
+};
+
+/**
+ * This field controls the decapsulation function for the action.
+ */
+#define CFA_P70_FULL_ACTION_DECAP_BITPOS 19
+#define CFA_P70_FULL_ACTION_DECAP_NUM_BITS 5
+/**
+ * Enumeration definition for field 'decap'
+ */
+enum cfa_p70_full_action_decap {
+ /* Do nothing. */
+ CFA_P70_FULL_ACTION_DECAP_DISABLE = 0,
+ /* Decap the outer VLAN tag */
+ CFA_P70_FULL_ACTION_DECAP_OVLAN = 1,
+ /* Decap all the VLAN tags */
+ CFA_P70_FULL_ACTION_DECAP_ALL_VLAN = 2,
+ /* Decap through Tunnel L2 header */
+ CFA_P70_FULL_ACTION_DECAP_TO_TL2 = 3,
+ /* Decap 1 MPLS label (does not delete outer L2) */
+ CFA_P70_FULL_ACTION_DECAP_1MPLS = 4,
+ /* Decap 1 MPLS label and outer L2 */
+ CFA_P70_FULL_ACTION_DECAP_1MPLS_OL2 = 5,
+ /* Decap 2 MPLS labels (does not delete outer L2) */
+ CFA_P70_FULL_ACTION_DECAP_2MPLS = 6,
+ /* Decap 2 MPLS labels and outer L2 */
+ CFA_P70_FULL_ACTION_DECAP_2MPLS_OL2 = 7,
+ /* Decap through Tunnel L3 header */
+ CFA_P70_FULL_ACTION_DECAP_TO_TL3 = 8,
+ /* Decap through Tunnel L4 header */
+ CFA_P70_FULL_ACTION_DECAP_TO_TL4 = 9,
+ /* Decap through Tunnel header */
+ CFA_P70_FULL_ACTION_DECAP_TO_T = 10,
+ /* Decap through Inner L2 */
+ CFA_P70_FULL_ACTION_DECAP_TO_L2 = 11,
+ /* Decap through Inner L3 */
+ CFA_P70_FULL_ACTION_DECAP_TO_L3 = 12,
+ /* Decap through inner L4 */
+ CFA_P70_FULL_ACTION_DECAP_TO_L4 = 13,
+ /* Shift tunnel->inner (single shift) */
+ CFA_P70_FULL_ACTION_DECAP_SHIFT_SINGLE = 14,
+ /* Un-parse (treat header as payload) */
+ CFA_P70_FULL_ACTION_DECAP_UNPARSE = 15,
+ /* Shift outer tunnel->inner (double shift) */
+ CFA_P70_FULL_ACTION_DECAP_SHIFT_DOUBLE = 18,
+ /* Decap through Outer Tunnel L2 header */
+ CFA_P70_FULL_ACTION_DECAP_TO_OL2 = 20,
+ /* Decap through Outer Tunnel L3 header */
+ CFA_P70_FULL_ACTION_DECAP_TO_OL3 = 21,
+ /* Decap through Outer Tunnel L4 header */
+ CFA_P70_FULL_ACTION_DECAP_TO_OL4 = 22,
+ /* Decap through Outer Tunnel header */
+ CFA_P70_FULL_ACTION_DECAP_TO_OT = 23,
+};
+
+/**
+ * The mirroring value selects one of 31 mirror destinations for the
+ * packet. A value of zero means that there is not Action Record
+ * mirroring for the packet.
+ */
+#define CFA_P70_FULL_ACTION_MIRRORING_BITPOS 24
+#define CFA_P70_FULL_ACTION_MIRRORING_NUM_BITS 5
+
+/**
+ * This value points to one of the 1024 meter entries. If the meter has
+ * scope verification enabled, then the scope in the meter table entry
+ * must match the scope of this action record.
+ */
+#define CFA_P70_FULL_ACTION_METER_PTR_BITPOS 29
+#define CFA_P70_FULL_ACTION_METER_PTR_NUM_BITS 10
+
+/**
+ * This is the pointer to the statistic structure in 8B units A value of
+ * zero will disable the statistics action.
+ */
+#define CFA_P70_FULL_ACTION_STAT0_PTR_BITPOS 39
+#define CFA_P70_FULL_ACTION_STAT0_PTR_NUM_BITS 28
+
+/**
+ * This value controls the packet size that is used for counted stats.
+ */
+#define CFA_P70_FULL_ACTION_STAT0_OP_BITPOS 67
+#define CFA_P70_FULL_ACTION_STAT0_OP_NUM_BITS 1
+/**
+ * Enumeration definition for field 'stat0_op'
+ */
+enum cfa_p70_full_action_stat0_op {
+ /* Statistics count reflects packet at 'ingress' to CFA. */
+ CFA_P70_FULL_ACTION_STAT0_OP_INGRESS = 0,
+ /* Statistics count reflects packet at 'egress' from CFA. */
+ CFA_P70_FULL_ACTION_STAT0_OP_EGRESS = 1,
+};
+
+/**
+ * Selects counter type. In all cases, fields are packet little endian
+ * in the action memory.
+ */
+#define CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_BITPOS 68
+#define CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_NUM_BITS 2
+/**
+ * Enumeration definition for field 'stat0_ctr_type'
+ */
+enum cfa_p70_full_action_stat0_ctr_type {
+ /* Forward packet count(64b)/byte count(64b) */
+ CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B16 = 0,
+ /*
+ * Forward packet count(64b)/byte count(64b) timestamp(32b) TCP
+ * Flags(16b) reserved(23b)
+ */
+ CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B24 = 1,
+ /*
+ * Forward packet count(64b)/byte count(64b) Meter (drop or red) packet
+ * count(64b)/byte count(64b)
+ */
+ CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B32A = 2,
+ /*
+ * Forward packet count(64b)/byte count(64b) Meter timestamp(32b) TCP
+ * Flags(16b) reserved(6b) (drop or red) packet count(38b)/byte
+ * count(42b)
+ */
+ CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B32B = 3,
+};
+
+/**
+ * This is the pointer to the statistic structure in 8B units A value of
+ * zero will disable the statistics action.
+ */
+#define CFA_P70_FULL_ACTION_STAT1_PTR_BITPOS 70
+#define CFA_P70_FULL_ACTION_STAT1_PTR_NUM_BITS 28
+
+/**
+ * This value controls the packet size that is used for counted stats.
+ */
+#define CFA_P70_FULL_ACTION_STAT1_OP_BITPOS 98
+#define CFA_P70_FULL_ACTION_STAT1_OP_NUM_BITS 1
+/**
+ * Enumeration definition for field 'stat1_op'
+ */
+enum cfa_p70_full_action_stat1_op {
+ /* Statistics count reflects packet at 'ingress' to CFA. */
+ CFA_P70_FULL_ACTION_STAT1_OP_INGRESS = 0,
+ /* Statistics count reflects packet at 'egress' from CFA. */
+ CFA_P70_FULL_ACTION_STAT1_OP_EGRESS = 1,
+};
+
+/**
+ * Selects counter type. In all cases, fields are packet little endian
+ * in the action memory.
+ */
+#define CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_BITPOS 99
+#define CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_NUM_BITS 2
+/**
+ * Enumeration definition for field 'stat1_ctr_type'
+ */
+enum cfa_p70_full_action_stat1_ctr_type {
+ /* Forward packet count(64b)/byte count(64b) */
+ CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B16 = 0,
+ /*
+ * Forward packet count(64b)/byte count(64b) timestamp(32b) TCP
+ * Flags(16b) reserved(23b)
+ */
+ CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B24 = 1,
+ /*
+ * Forward packet count(64b)/byte count(64b) Meter (drop or red) packet
+ * count(64b)/byte count(64b)
+ */
+ CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B32A = 2,
+ /*
+ * Forward packet count(64b)/byte count(64b) Meter timestamp(32b) TCP
+ * Flags(16b) reserved(6b) (drop or red) packet count(38b)/byte
+ * count(42b)
+ */
+ CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B32B = 3,
+};
+
+/**
+ * This is a pointer to the modification record. This is a pointer in 8B
+ * units directly to dependent record data. A value of zero indicates no
+ * additional actions.
+ */
+#define CFA_P70_FULL_ACTION_MOD_PTR_BITPOS 101
+#define CFA_P70_FULL_ACTION_MOD_PTR_NUM_BITS 28
+
+/**
+ * This is a pointer to the encapsulation record. This is a pointer in
+ * 8B units directly to dependent record data. A value of zero indicates
+ * no additional actions.
+ */
+#define CFA_P70_FULL_ACTION_ENC_PTR_BITPOS 129
+#define CFA_P70_FULL_ACTION_ENC_PTR_NUM_BITS 28
+
+/**
+ * This is a pointer to the source record. This is a pointer in 8B units
+ * directly to dependent record data. A value of zero indicates no
+ * additional actions.
+ */
+#define CFA_P70_FULL_ACTION_SRC_PTR_BITPOS 157
+#define CFA_P70_FULL_ACTION_SRC_PTR_NUM_BITS 28
+#define CFA_P70_FULL_ACTION_UNUSED_0_BITPOS 185
+#define CFA_P70_FULL_ACTION_UNUSED_0_NUM_BITS 7
+
+/**
+ * Total number of bits for full_action
+ */
+#define CFA_P70_FULL_ACTION_TOTAL_NUM_BITS 192
+
+/**
+ * The type field identifies the format of the action record to the
+ * hardware.
+ */
+#define CFA_P70_MCG_ACTION_TYPE_BITPOS 0
+#define CFA_P70_MCG_ACTION_TYPE_NUM_BITS 3
+/**
+ * Enumeration definition for field 'type'
+ */
+enum cfa_p70_mcg_action_type {
+ /*
+ * Multicast Group Action Record. This action is used to send the packet
+ * to multiple destinations. The MGC Action record is 256b.
+ */
+ CFA_P70_MCG_ACTION_TYPE_MCG_ACTION = 4,
+};
+
+/**
+ * When this bit is set to '1', source knockout will be supported for
+ * the MCG record. This value also applies to any chained subsequent MCG
+ * records. This is applied on the RX CFA only.
+ */
+#define CFA_P70_MCG_ACTION_SRC_KO_EN_BITPOS 3
+#define CFA_P70_MCG_ACTION_SRC_KO_EN_NUM_BITS 1
+#define CFA_P70_MCG_ACTION_UNUSED_0_BITPOS 4
+#define CFA_P70_MCG_ACTION_UNUSED_0_NUM_BITS 2
+
+/**
+ * This is a pointer to the next MGC Subsequent Entries Record. The
+ * Subsequent Entries MGC record must be on a 32B boundary. A value of
+ * zero indicates that there are not additional MGC Subsequent Entries
+ * record.
+ */
+#define CFA_P70_MCG_ACTION_NEXT_PTR_BITPOS 6
+#define CFA_P70_MCG_ACTION_NEXT_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_ACTION_PTR0_ACT_HINT_BITPOS 32
+#define CFA_P70_MCG_ACTION_PTR0_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_ACTION_PTR0_ACT_REC_PTR_BITPOS 34
+#define CFA_P70_MCG_ACTION_PTR0_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_ACTION_PTR1_ACT_HINT_BITPOS 60
+#define CFA_P70_MCG_ACTION_PTR1_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_ACTION_PTR1_ACT_REC_PTR_BITPOS 62
+#define CFA_P70_MCG_ACTION_PTR1_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_ACTION_PTR2_ACT_HINT_BITPOS 88
+#define CFA_P70_MCG_ACTION_PTR2_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_ACTION_PTR2_ACT_REC_PTR_BITPOS 90
+#define CFA_P70_MCG_ACTION_PTR2_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_ACTION_PTR3_ACT_HINT_BITPOS 116
+#define CFA_P70_MCG_ACTION_PTR3_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_ACTION_PTR3_ACT_REC_PTR_BITPOS 118
+#define CFA_P70_MCG_ACTION_PTR3_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_ACTION_PTR4_ACT_HINT_BITPOS 144
+#define CFA_P70_MCG_ACTION_PTR4_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_ACTION_PTR4_ACT_REC_PTR_BITPOS 146
+#define CFA_P70_MCG_ACTION_PTR4_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_ACTION_PTR5_ACT_HINT_BITPOS 172
+#define CFA_P70_MCG_ACTION_PTR5_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_ACTION_PTR5_ACT_REC_PTR_BITPOS 174
+#define CFA_P70_MCG_ACTION_PTR5_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_ACTION_PTR6_ACT_HINT_BITPOS 200
+#define CFA_P70_MCG_ACTION_PTR6_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_ACTION_PTR6_ACT_REC_PTR_BITPOS 202
+#define CFA_P70_MCG_ACTION_PTR6_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_ACTION_PTR7_ACT_HINT_BITPOS 228
+#define CFA_P70_MCG_ACTION_PTR7_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_ACTION_PTR7_ACT_REC_PTR_BITPOS 230
+#define CFA_P70_MCG_ACTION_PTR7_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * Total number of bits for mcg_action
+ */
+#define CFA_P70_MCG_ACTION_TOTAL_NUM_BITS 256
+
+/**
+ * The type field identifies the format of the action record to the
+ * hardware.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_TYPE_BITPOS 0
+#define CFA_P70_MCG_SUBSEQ_ACTION_TYPE_NUM_BITS 3
+/**
+ * Enumeration definition for field 'type'
+ */
+enum cfa_p70_mcg_subseq_action_type {
+ /*
+ * Multicast Group Action Record. This action is used to send the packet
+ * to multiple destinations. The MGC Action record is 256b.
+ */
+ CFA_P70_MCG_SUBSEQ_ACTION_TYPE_MCG_ACTION = 4,
+};
+#define CFA_P70_MCG_SUBSEQ_ACTION_UNUSED_0_BITPOS 3
+#define CFA_P70_MCG_SUBSEQ_ACTION_UNUSED_0_NUM_BITS 3
+
+/**
+ * This is a pointer to the next MGC Subsequent Entries Record. The
+ * Subsequent Entries MGC record must be on a 32B boundary. A value of
+ * zero indicates that there are not additional MGC Subsequent Entries
+ * record.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_NEXT_PTR_BITPOS 6
+#define CFA_P70_MCG_SUBSEQ_ACTION_NEXT_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_BITPOS 32
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_BITPOS 34
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_BITPOS 60
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_BITPOS 62
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_BITPOS 88
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_BITPOS 90
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_BITPOS 116
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_BITPOS 118
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_BITPOS 144
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_BITPOS 146
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_BITPOS 172
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_BITPOS 174
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_BITPOS 200
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_BITPOS 202
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * This is the prefetch hint that corresponds to this action record
+ * pointer. This value will index into the hint table for the current
+ * scope to determines the actual prefetch size.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_BITPOS 228
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_NUM_BITS 2
+
+/**
+ * This is an individual action record pointer for an MGC entry. This
+ * points to a action record for this particular MGC member. If this
+ * pointer is zero, then it will not be followed.
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_BITPOS 230
+#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_NUM_BITS 26
+
+/**
+ * Total number of bits for mcg_subseq_action
+ */
+#define CFA_P70_MCG_SUBSEQ_ACTION_TOTAL_NUM_BITS 256
+
+/**
+ * Current committed token bucket count.
+ */
+#define CFA_P70_METERS_BKT_C_BITPOS 0
+#define CFA_P70_METERS_BKT_C_NUM_BITS 27
+
+/**
+ * Current excess token bucket count.
+ */
+#define CFA_P70_METERS_BKT_E_BITPOS 27
+#define CFA_P70_METERS_BKT_E_NUM_BITS 27
+
+/**
+ * Meter Valid
+ */
+#define CFA_P70_METERS_FLAGS_MTR_VAL_BITPOS 54
+#define CFA_P70_METERS_FLAGS_MTR_VAL_NUM_BITS 1
+
+/**
+ * ECN Remap Enable
+ */
+#define CFA_P70_METERS_FLAGS_ECN_RMP_EN_BITPOS 55
+#define CFA_P70_METERS_FLAGS_ECN_RMP_EN_NUM_BITS 1
+
+/**
+ * Coupling Flag. Indicates that tokens being added to the committed
+ * bucket should be diverted to the excess bucket when the committed
+ * bucket is full. This bit is ignored when RFC2698=1
+ */
+#define CFA_P70_METERS_FLAGS_CF_BITPOS 56
+#define CFA_P70_METERS_FLAGS_CF_NUM_BITS 1
+
+/**
+ * Packet Mode. When set packet length is ignored and a global value is
+ * used instead.
+ */
+#define CFA_P70_METERS_FLAGS_PM_BITPOS 57
+#define CFA_P70_METERS_FLAGS_PM_NUM_BITS 1
+
+/**
+ * RFC2698 Enable - Indicates if BOTH buckets must have sufficient
+ * tokens to color a packet green per RFC2698, as opposed to just the
+ * committed bucket.
+ */
+#define CFA_P70_METERS_FLAGS_RFC2698_BITPOS 58
+#define CFA_P70_METERS_FLAGS_RFC2698_NUM_BITS 1
+
+/**
+ * Committed Bucket Strict Mode. If set, a packet conforms to the
+ * committed bucket only if the number of tokens is greater than or
+ * equal to the packet length. When not set meter conformance is
+ * independent of packet size and requires only that the token count is
+ * non-negative.
+ */
+#define CFA_P70_METERS_FLAGS_CBSM_BITPOS 59
+#define CFA_P70_METERS_FLAGS_CBSM_NUM_BITS 1
+
+/**
+ * Excess Bucket Strict Mode. If set, a packet conforms to the excess
+ * bucket only if the number of tokens is greater than or equal to the
+ * packet length. When not set, meter conformance is independent of
+ * packet size and requires only that the token count is non-negative.
+ */
+#define CFA_P70_METERS_FLAGS_EBSM_BITPOS 60
+#define CFA_P70_METERS_FLAGS_EBSM_NUM_BITS 1
+
+/**
+ * Committed Bucket No Decrement. If set, tokens are never decremented
+ * from the committed bucket, even when the packet is Green.
+ */
+#define CFA_P70_METERS_FLAGS_CBND_BITPOS 61
+#define CFA_P70_METERS_FLAGS_CBND_NUM_BITS 1
+
+/**
+ * Excess Bucket No Decrement. If set, tokens are never decremented from
+ * the excess bucket, even when the packet is Green.
+ */
+#define CFA_P70_METERS_FLAGS_EBND_BITPOS 62
+#define CFA_P70_METERS_FLAGS_EBND_NUM_BITS 1
+
+/**
+ * Committed Burst Size. Expressed in bytes in a normalized floating
+ * point format.
+ */
+#define CFA_P70_METERS_CBS_BITPOS 63
+#define CFA_P70_METERS_CBS_NUM_BITS 12
+
+/**
+ * Excess Burst Size. Expressed in bytes in a normalized floating point
+ * format.
+ */
+#define CFA_P70_METERS_EBS_BITPOS 75
+#define CFA_P70_METERS_EBS_NUM_BITS 12
+
+/**
+ * Committed Information Rate. A rate expressed in bytes per clock cycle
+ * in a normalized floating point format.
+ */
+#define CFA_P70_METERS_CIR_BITPOS 87
+#define CFA_P70_METERS_CIR_NUM_BITS 17
+
+/**
+ * Excess Information Rate. A rate expressed in bytes per clock cycle in
+ * a normalized floating point format.
+ */
+#define CFA_P70_METERS_EIR_BITPOS 104
+#define CFA_P70_METERS_EIR_NUM_BITS 17
+
+/**
+ * This is the scope whose action records will be allowed to reference
+ * this meter if the enable bit is '1'.
+ */
+#define CFA_P70_METERS_PROTECTION_SCOPE_BITPOS 121
+#define CFA_P70_METERS_PROTECTION_SCOPE_NUM_BITS 5
+
+/**
+ * Reserved.
+ */
+#define CFA_P70_METERS_PROTECTION_RSVD_BITPOS 126
+#define CFA_P70_METERS_PROTECTION_RSVD_NUM_BITS 1
+
+/**
+ * When this bit is '1', the meter will be protected from any scope
+ * action other than the one in the scope field.
+ */
+#define CFA_P70_METERS_PROTECTION_ENABLE_BITPOS 127
+#define CFA_P70_METERS_PROTECTION_ENABLE_NUM_BITS 1
+
+/**
+ * Total number of bits for meters
+ */
+#define CFA_P70_METERS_TOTAL_NUM_BITS 128
+
+/**
+ * Field length definitions for fkb
+ */
+#define CFA_P70_FKB_PROF_ID_NUM_BITS 8
+#define CFA_P70_FKB_L2CTXT_NUM_BITS 11
+#define CFA_P70_FKB_L2FUNC_NUM_BITS 8
+#define CFA_P70_FKB_PARIF_NUM_BITS 2
+#define CFA_P70_FKB_SPIF_NUM_BITS 2
+#define CFA_P70_FKB_SVIF_NUM_BITS 6
+#define CFA_P70_FKB_LCOS_NUM_BITS 3
+#define CFA_P70_FKB_META_HI_NUM_BITS 16
+#define CFA_P70_FKB_META_LO_NUM_BITS 16
+#define CFA_P70_FKB_RCYC_CNT_NUM_BITS 4
+#define CFA_P70_FKB_LOOPBACK_NUM_BITS 1
+#define CFA_P70_FKB_OTL2_TYPE_NUM_BITS 2
+#define CFA_P70_FKB_OTL2_DMAC_NUM_BITS 48
+#define CFA_P70_FKB_OTL2_SMAC_NUM_BITS 48
+#define CFA_P70_FKB_OTL2_DT_NUM_BITS 2
+#define CFA_P70_FKB_OTL2_SA_NUM_BITS 1
+#define CFA_P70_FKB_OTL2_NVT_NUM_BITS 2
+#define CFA_P70_FKB_OTL2_OVP_NUM_BITS 3
+#define CFA_P70_FKB_OTL2_OVD_NUM_BITS 1
+#define CFA_P70_FKB_OTL2_OVV_NUM_BITS 12
+#define CFA_P70_FKB_OTL2_OVT_NUM_BITS 3
+#define CFA_P70_FKB_OTL2_IVP_NUM_BITS 3
+#define CFA_P70_FKB_OTL2_IVD_NUM_BITS 1
+#define CFA_P70_FKB_OTL2_IVV_NUM_BITS 12
+#define CFA_P70_FKB_OTL2_IVT_NUM_BITS 3
+#define CFA_P70_FKB_OTL2_ETYPE_NUM_BITS 16
+#define CFA_P70_FKB_OTL3_TYPE_NUM_BITS 4
+#define CFA_P70_FKB_OTL3_SIP3_NUM_BITS 32
+#define CFA_P70_FKB_OTL3_SIP2_NUM_BITS 32
+#define CFA_P70_FKB_OTL3_SIP1_NUM_BITS 32
+#define CFA_P70_FKB_OTL3_SIP0_NUM_BITS 32
+#define CFA_P70_FKB_OTL3_DIP3_NUM_BITS 32
+#define CFA_P70_FKB_OTL3_DIP2_NUM_BITS 32
+#define CFA_P70_FKB_OTL3_DIP1_NUM_BITS 32
+#define CFA_P70_FKB_OTL3_DIP0_NUM_BITS 32
+#define CFA_P70_FKB_OTL3_TTL_NUM_BITS 8
+#define CFA_P70_FKB_OTL3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_FKB_OTL3_FID bit length is not fixed
+ * So the CFA_P70_FKB_OTL3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_FKB_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_FKB_OTL3_QOS_NUM_BITS 8
+#define CFA_P70_FKB_OTL3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_FKB_OTL3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_FKB_OTL3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_FKB_OTL3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_FKB_OTL3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_FKB_OTL3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_FKB_OTL3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_FKB_OTL3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_FKB_OTL3_DF_NUM_BITS 1
+#define CFA_P70_FKB_OTL3_L3ERR_NUM_BITS 4
+#define CFA_P70_FKB_OTL4_TYPE_NUM_BITS 4
+#define CFA_P70_FKB_OTL4_SRC_NUM_BITS 16
+#define CFA_P70_FKB_OTL4_DST_NUM_BITS 16
+#define CFA_P70_FKB_OTL4_FLAGS_NUM_BITS 9
+#define CFA_P70_FKB_OTL4_SEQ_NUM_BITS 32
+#define CFA_P70_FKB_OTL4_PA_NUM_BITS 1
+#define CFA_P70_FKB_OTL4_OPT_NUM_BITS 1
+#define CFA_P70_FKB_OTL4_TCPTS_NUM_BITS 1
+#define CFA_P70_FKB_OTL4_ERR_NUM_BITS 4
+#define CFA_P70_FKB_OT_TYPE_NUM_BITS 5
+#define CFA_P70_FKB_OT_FLAGS_NUM_BITS 8
+#define CFA_P70_FKB_OT_IDS_NUM_BITS 24
+#define CFA_P70_FKB_OT_ID_NUM_BITS 32
+#define CFA_P70_FKB_OT_CTXTS_NUM_BITS 24
+#define CFA_P70_FKB_OT_CTXT_NUM_BITS 32
+#define CFA_P70_FKB_OT_QOS_NUM_BITS 3
+#define CFA_P70_FKB_OT_ERR_NUM_BITS 4
+#define CFA_P70_FKB_TL2_TYPE_NUM_BITS 2
+#define CFA_P70_FKB_TL2_DMAC_NUM_BITS 48
+#define CFA_P70_FKB_TL2_SMAC_NUM_BITS 48
+#define CFA_P70_FKB_TL2_DT_NUM_BITS 2
+#define CFA_P70_FKB_TL2_SA_NUM_BITS 1
+#define CFA_P70_FKB_TL2_NVT_NUM_BITS 2
+#define CFA_P70_FKB_TL2_OVP_NUM_BITS 3
+#define CFA_P70_FKB_TL2_OVD_NUM_BITS 1
+#define CFA_P70_FKB_TL2_OVV_NUM_BITS 12
+#define CFA_P70_FKB_TL2_OVT_NUM_BITS 3
+#define CFA_P70_FKB_TL2_IVP_NUM_BITS 3
+#define CFA_P70_FKB_TL2_IVD_NUM_BITS 1
+#define CFA_P70_FKB_TL2_IVV_NUM_BITS 12
+#define CFA_P70_FKB_TL2_IVT_NUM_BITS 3
+#define CFA_P70_FKB_TL2_ETYPE_NUM_BITS 16
+#define CFA_P70_FKB_TL3_TYPE_NUM_BITS 4
+#define CFA_P70_FKB_TL3_SIP3_NUM_BITS 32
+#define CFA_P70_FKB_TL3_SIP2_NUM_BITS 32
+#define CFA_P70_FKB_TL3_SIP1_NUM_BITS 32
+#define CFA_P70_FKB_TL3_SIP0_NUM_BITS 32
+#define CFA_P70_FKB_TL3_DIP3_NUM_BITS 32
+#define CFA_P70_FKB_TL3_DIP2_NUM_BITS 32
+#define CFA_P70_FKB_TL3_DIP1_NUM_BITS 32
+#define CFA_P70_FKB_TL3_DIP0_NUM_BITS 32
+#define CFA_P70_FKB_TL3_TTL_NUM_BITS 8
+#define CFA_P70_FKB_TL3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_FKB_TL3_FID bit length is not fixed
+ * So the CFA_P70_FKB_TL3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_FKB_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_FKB_TL3_QOS_NUM_BITS 8
+#define CFA_P70_FKB_TL3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_FKB_TL3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_FKB_TL3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_FKB_TL3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_FKB_TL3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_FKB_TL3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_FKB_TL3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_FKB_TL3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_FKB_TL3_DF_NUM_BITS 1
+#define CFA_P70_FKB_TL3_L3ERR_NUM_BITS 4
+#define CFA_P70_FKB_TL4_TYPE_NUM_BITS 4
+#define CFA_P70_FKB_TL4_SRC_NUM_BITS 16
+#define CFA_P70_FKB_TL4_DST_NUM_BITS 16
+#define CFA_P70_FKB_TL4_FLAGS_NUM_BITS 9
+#define CFA_P70_FKB_TL4_SEQ_NUM_BITS 32
+#define CFA_P70_FKB_TL4_PA_NUM_BITS 1
+#define CFA_P70_FKB_TL4_OPT_NUM_BITS 1
+#define CFA_P70_FKB_TL4_TCPTS_NUM_BITS 1
+#define CFA_P70_FKB_TL4_ERR_NUM_BITS 4
+#define CFA_P70_FKB_T_TYPE_NUM_BITS 5
+#define CFA_P70_FKB_T_FLAGS_NUM_BITS 8
+#define CFA_P70_FKB_T_IDS_NUM_BITS 24
+#define CFA_P70_FKB_T_ID_NUM_BITS 32
+#define CFA_P70_FKB_T_CTXTS_NUM_BITS 24
+#define CFA_P70_FKB_T_CTXT_NUM_BITS 32
+#define CFA_P70_FKB_T_QOS_NUM_BITS 3
+#define CFA_P70_FKB_T_ERR_NUM_BITS 4
+#define CFA_P70_FKB_L2_TYPE_NUM_BITS 2
+#define CFA_P70_FKB_L2_DMAC_NUM_BITS 48
+#define CFA_P70_FKB_L2_SMAC_NUM_BITS 48
+#define CFA_P70_FKB_L2_DT_NUM_BITS 2
+#define CFA_P70_FKB_L2_SA_NUM_BITS 1
+#define CFA_P70_FKB_L2_NVT_NUM_BITS 2
+#define CFA_P70_FKB_L2_OVP_NUM_BITS 3
+#define CFA_P70_FKB_L2_OVD_NUM_BITS 1
+#define CFA_P70_FKB_L2_OVV_NUM_BITS 12
+#define CFA_P70_FKB_L2_OVT_NUM_BITS 3
+#define CFA_P70_FKB_L2_IVP_NUM_BITS 3
+#define CFA_P70_FKB_L2_IVD_NUM_BITS 1
+#define CFA_P70_FKB_L2_IVV_NUM_BITS 12
+#define CFA_P70_FKB_L2_IVT_NUM_BITS 3
+#define CFA_P70_FKB_L2_ETYPE_NUM_BITS 16
+#define CFA_P70_FKB_L3_TYPE_NUM_BITS 4
+#define CFA_P70_FKB_L3_SIP3_NUM_BITS 32
+#define CFA_P70_FKB_L3_SIP2_NUM_BITS 32
+#define CFA_P70_FKB_L3_SIP1_NUM_BITS 32
+#define CFA_P70_FKB_L3_SIP0_NUM_BITS 32
+#define CFA_P70_FKB_L3_DIP3_NUM_BITS 32
+#define CFA_P70_FKB_L3_DIP2_NUM_BITS 32
+#define CFA_P70_FKB_L3_DIP1_NUM_BITS 32
+#define CFA_P70_FKB_L3_DIP0_NUM_BITS 32
+#define CFA_P70_FKB_L3_TTL_NUM_BITS 8
+#define CFA_P70_FKB_L3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_FKB_L3_FID bit length is not fixed
+ * So the CFA_P70_FKB_L3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_FKB_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_FKB_L3_QOS_NUM_BITS 8
+#define CFA_P70_FKB_L3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_FKB_L3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_FKB_L3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_FKB_L3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_FKB_L3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_FKB_L3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_FKB_L3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_FKB_L3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_FKB_L3_DF_NUM_BITS 1
+#define CFA_P70_FKB_L3_L3ERR_NUM_BITS 4
+#define CFA_P70_FKB_L4_TYPE_NUM_BITS 4
+#define CFA_P70_FKB_L4_SRC_NUM_BITS 16
+#define CFA_P70_FKB_L4_DST_NUM_BITS 16
+#define CFA_P70_FKB_L4_FLAGS_NUM_BITS 9
+#define CFA_P70_FKB_L4_SEQ_NUM_BITS 32
+#define CFA_P70_FKB_L4_ACK_NUM_BITS 32
+#define CFA_P70_FKB_L4_WIN_NUM_BITS 16
+#define CFA_P70_FKB_L4_PA_NUM_BITS 1
+#define CFA_P70_FKB_L4_OPT_NUM_BITS 1
+#define CFA_P70_FKB_L4_TCPTS_NUM_BITS 1
+#define CFA_P70_FKB_L4_TSVAL_NUM_BITS 32
+#define CFA_P70_FKB_L4_TXECR_NUM_BITS 32
+#define CFA_P70_FKB_L4_ERR_NUM_BITS 4
+
+/**
+ * Field length definitions for wc tcam fkb
+ */
+#define CFA_P70_WC_TCAM_FKB_PROF_ID_NUM_BITS 8
+#define CFA_P70_WC_TCAM_FKB_L2CTXT_NUM_BITS 11
+#define CFA_P70_WC_TCAM_FKB_L2FUNC_NUM_BITS 8
+#define CFA_P70_WC_TCAM_FKB_PARIF_NUM_BITS 2
+#define CFA_P70_WC_TCAM_FKB_SPIF_NUM_BITS 2
+#define CFA_P70_WC_TCAM_FKB_SVIF_NUM_BITS 6
+#define CFA_P70_WC_TCAM_FKB_LCOS_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_META_HI_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_META_LO_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_RCYC_CNT_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_LOOPBACK_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL2_TYPE_NUM_BITS 2
+#define CFA_P70_WC_TCAM_FKB_OTL2_DMAC_NUM_BITS 48
+#define CFA_P70_WC_TCAM_FKB_OTL2_SMAC_NUM_BITS 48
+#define CFA_P70_WC_TCAM_FKB_OTL2_DT_NUM_BITS 2
+#define CFA_P70_WC_TCAM_FKB_OTL2_SA_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL2_NVT_NUM_BITS 2
+#define CFA_P70_WC_TCAM_FKB_OTL2_OVP_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_OTL2_OVD_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL2_OVV_NUM_BITS 12
+#define CFA_P70_WC_TCAM_FKB_OTL2_OVT_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_OTL2_IVP_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_OTL2_IVD_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL2_IVV_NUM_BITS 12
+#define CFA_P70_WC_TCAM_FKB_OTL2_IVT_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_OTL2_ETYPE_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_OTL3_TYPE_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_OTL3_SIP3_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_OTL3_SIP2_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_OTL3_SIP1_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_OTL3_SIP0_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_OTL3_DIP3_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_OTL3_DIP2_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_OTL3_DIP1_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_OTL3_DIP0_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_OTL3_TTL_NUM_BITS 8
+#define CFA_P70_WC_TCAM_FKB_OTL3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_WC_TCAM_FKB_OTL3_FID bit length is not fixed
+ * So the CFA_P70_WC_TCAM_FKB_OTL3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_WC_TCAM_FKB_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_WC_TCAM_FKB_OTL3_QOS_NUM_BITS 8
+#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL3_DF_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL3_L3ERR_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_OTL4_TYPE_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_OTL4_SRC_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_OTL4_DST_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_OTL4_FLAGS_NUM_BITS 9
+#define CFA_P70_WC_TCAM_FKB_OTL4_SEQ_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_OTL4_PA_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL4_OPT_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL4_TCPTS_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_OTL4_ERR_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_OT_TYPE_NUM_BITS 5
+#define CFA_P70_WC_TCAM_FKB_OT_FLAGS_NUM_BITS 8
+#define CFA_P70_WC_TCAM_FKB_OT_IDS_NUM_BITS 24
+#define CFA_P70_WC_TCAM_FKB_OT_ID_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_OT_CTXTS_NUM_BITS 24
+#define CFA_P70_WC_TCAM_FKB_OT_CTXT_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_OT_QOS_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_OT_ERR_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_TL2_TYPE_NUM_BITS 2
+#define CFA_P70_WC_TCAM_FKB_TL2_DMAC_NUM_BITS 48
+#define CFA_P70_WC_TCAM_FKB_TL2_SMAC_NUM_BITS 48
+#define CFA_P70_WC_TCAM_FKB_TL2_DT_NUM_BITS 2
+#define CFA_P70_WC_TCAM_FKB_TL2_SA_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL2_NVT_NUM_BITS 2
+#define CFA_P70_WC_TCAM_FKB_TL2_OVP_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_TL2_OVD_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL2_OVV_NUM_BITS 12
+#define CFA_P70_WC_TCAM_FKB_TL2_OVT_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_TL2_IVP_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_TL2_IVD_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL2_IVV_NUM_BITS 12
+#define CFA_P70_WC_TCAM_FKB_TL2_IVT_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_TL2_ETYPE_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_TL3_TYPE_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_TL3_SIP3_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_TL3_SIP2_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_TL3_SIP1_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_TL3_SIP0_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_TL3_DIP3_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_TL3_DIP2_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_TL3_DIP1_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_TL3_DIP0_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_TL3_TTL_NUM_BITS 8
+#define CFA_P70_WC_TCAM_FKB_TL3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_WC_TCAM_FKB_TL3_FID bit length is not fixed
+ * So the CFA_P70_WC_TCAM_FKB_TL3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_WC_TCAM_FKB_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_WC_TCAM_FKB_TL3_QOS_NUM_BITS 8
+#define CFA_P70_WC_TCAM_FKB_TL3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL3_DF_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL3_L3ERR_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_TL4_TYPE_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_TL4_SRC_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_TL4_DST_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_TL4_FLAGS_NUM_BITS 9
+#define CFA_P70_WC_TCAM_FKB_TL4_SEQ_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_TL4_PA_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL4_OPT_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL4_TCPTS_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_TL4_ERR_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_T_TYPE_NUM_BITS 5
+#define CFA_P70_WC_TCAM_FKB_T_FLAGS_NUM_BITS 8
+#define CFA_P70_WC_TCAM_FKB_T_IDS_NUM_BITS 24
+#define CFA_P70_WC_TCAM_FKB_T_ID_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_T_CTXTS_NUM_BITS 24
+#define CFA_P70_WC_TCAM_FKB_T_CTXT_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_T_QOS_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_T_ERR_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_L2_TYPE_NUM_BITS 2
+#define CFA_P70_WC_TCAM_FKB_L2_DMAC_NUM_BITS 48
+#define CFA_P70_WC_TCAM_FKB_L2_SMAC_NUM_BITS 48
+#define CFA_P70_WC_TCAM_FKB_L2_DT_NUM_BITS 2
+#define CFA_P70_WC_TCAM_FKB_L2_SA_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L2_NVT_NUM_BITS 2
+#define CFA_P70_WC_TCAM_FKB_L2_OVP_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_L2_OVD_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L2_OVV_NUM_BITS 12
+#define CFA_P70_WC_TCAM_FKB_L2_OVT_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_L2_IVP_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_L2_IVD_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L2_IVV_NUM_BITS 12
+#define CFA_P70_WC_TCAM_FKB_L2_IVT_NUM_BITS 3
+#define CFA_P70_WC_TCAM_FKB_L2_ETYPE_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_L3_TYPE_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_L3_SIP3_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L3_SIP2_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L3_SIP1_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L3_SIP0_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L3_DIP3_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L3_DIP2_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L3_DIP1_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L3_DIP0_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L3_TTL_NUM_BITS 8
+#define CFA_P70_WC_TCAM_FKB_L3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_WC_TCAM_FKB_L3_FID bit length is not fixed
+ * So the CFA_P70_WC_TCAM_FKB_L3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_WC_TCAM_FKB_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_WC_TCAM_FKB_L3_QOS_NUM_BITS 8
+#define CFA_P70_WC_TCAM_FKB_L3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L3_DF_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L3_L3ERR_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_L4_TYPE_NUM_BITS 4
+#define CFA_P70_WC_TCAM_FKB_L4_SRC_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_L4_DST_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_L4_FLAGS_NUM_BITS 9
+#define CFA_P70_WC_TCAM_FKB_L4_SEQ_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L4_ACK_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L4_WIN_NUM_BITS 16
+#define CFA_P70_WC_TCAM_FKB_L4_PA_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L4_OPT_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L4_TCPTS_NUM_BITS 1
+#define CFA_P70_WC_TCAM_FKB_L4_TSVAL_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L4_TXECR_NUM_BITS 32
+#define CFA_P70_WC_TCAM_FKB_L4_ERR_NUM_BITS 4
+
+/**
+ * Field length definitions for em fkb
+ */
+#define CFA_P70_EM_FKB_PROF_ID_NUM_BITS 8
+#define CFA_P70_EM_FKB_L2CTXT_NUM_BITS 11
+#define CFA_P70_EM_FKB_L2FUNC_NUM_BITS 8
+#define CFA_P70_EM_FKB_PARIF_NUM_BITS 2
+#define CFA_P70_EM_FKB_SPIF_NUM_BITS 2
+#define CFA_P70_EM_FKB_SVIF_NUM_BITS 6
+#define CFA_P70_EM_FKB_LCOS_NUM_BITS 3
+#define CFA_P70_EM_FKB_META_HI_NUM_BITS 16
+#define CFA_P70_EM_FKB_META_LO_NUM_BITS 16
+#define CFA_P70_EM_FKB_RCYC_CNT_NUM_BITS 4
+#define CFA_P70_EM_FKB_LOOPBACK_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL2_TYPE_NUM_BITS 2
+#define CFA_P70_EM_FKB_OTL2_DMAC_NUM_BITS 48
+#define CFA_P70_EM_FKB_OTL2_SMAC_NUM_BITS 48
+#define CFA_P70_EM_FKB_OTL2_DT_NUM_BITS 2
+#define CFA_P70_EM_FKB_OTL2_SA_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL2_NVT_NUM_BITS 2
+#define CFA_P70_EM_FKB_OTL2_OVP_NUM_BITS 3
+#define CFA_P70_EM_FKB_OTL2_OVD_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL2_OVV_NUM_BITS 12
+#define CFA_P70_EM_FKB_OTL2_OVT_NUM_BITS 3
+#define CFA_P70_EM_FKB_OTL2_IVP_NUM_BITS 3
+#define CFA_P70_EM_FKB_OTL2_IVD_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL2_IVV_NUM_BITS 12
+#define CFA_P70_EM_FKB_OTL2_IVT_NUM_BITS 3
+#define CFA_P70_EM_FKB_OTL2_ETYPE_NUM_BITS 16
+#define CFA_P70_EM_FKB_OTL3_TYPE_NUM_BITS 4
+#define CFA_P70_EM_FKB_OTL3_SIP3_NUM_BITS 32
+#define CFA_P70_EM_FKB_OTL3_SIP2_NUM_BITS 32
+#define CFA_P70_EM_FKB_OTL3_SIP1_NUM_BITS 32
+#define CFA_P70_EM_FKB_OTL3_SIP0_NUM_BITS 32
+#define CFA_P70_EM_FKB_OTL3_DIP3_NUM_BITS 32
+#define CFA_P70_EM_FKB_OTL3_DIP2_NUM_BITS 32
+#define CFA_P70_EM_FKB_OTL3_DIP1_NUM_BITS 32
+#define CFA_P70_EM_FKB_OTL3_DIP0_NUM_BITS 32
+#define CFA_P70_EM_FKB_OTL3_TTL_NUM_BITS 8
+#define CFA_P70_EM_FKB_OTL3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_EM_FKB_OTL3_FID bit length is not fixed
+ * So the CFA_P70_EM_FKB_OTL3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_EM_FKB_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_EM_FKB_OTL3_QOS_NUM_BITS 8
+#define CFA_P70_EM_FKB_OTL3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL3_DF_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL3_L3ERR_NUM_BITS 4
+#define CFA_P70_EM_FKB_OTL4_TYPE_NUM_BITS 4
+#define CFA_P70_EM_FKB_OTL4_SRC_NUM_BITS 16
+#define CFA_P70_EM_FKB_OTL4_DST_NUM_BITS 16
+#define CFA_P70_EM_FKB_OTL4_FLAGS_NUM_BITS 9
+#define CFA_P70_EM_FKB_OTL4_SEQ_NUM_BITS 32
+#define CFA_P70_EM_FKB_OTL4_PA_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL4_OPT_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL4_TCPTS_NUM_BITS 1
+#define CFA_P70_EM_FKB_OTL4_ERR_NUM_BITS 4
+#define CFA_P70_EM_FKB_OT_TYPE_NUM_BITS 5
+#define CFA_P70_EM_FKB_OT_FLAGS_NUM_BITS 8
+#define CFA_P70_EM_FKB_OT_IDS_NUM_BITS 24
+#define CFA_P70_EM_FKB_OT_ID_NUM_BITS 32
+#define CFA_P70_EM_FKB_OT_CTXTS_NUM_BITS 24
+#define CFA_P70_EM_FKB_OT_CTXT_NUM_BITS 32
+#define CFA_P70_EM_FKB_OT_QOS_NUM_BITS 3
+#define CFA_P70_EM_FKB_OT_ERR_NUM_BITS 4
+#define CFA_P70_EM_FKB_TL2_TYPE_NUM_BITS 2
+#define CFA_P70_EM_FKB_TL2_DMAC_NUM_BITS 48
+#define CFA_P70_EM_FKB_TL2_SMAC_NUM_BITS 48
+#define CFA_P70_EM_FKB_TL2_DT_NUM_BITS 2
+#define CFA_P70_EM_FKB_TL2_SA_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL2_NVT_NUM_BITS 2
+#define CFA_P70_EM_FKB_TL2_OVP_NUM_BITS 3
+#define CFA_P70_EM_FKB_TL2_OVD_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL2_OVV_NUM_BITS 12
+#define CFA_P70_EM_FKB_TL2_OVT_NUM_BITS 3
+#define CFA_P70_EM_FKB_TL2_IVP_NUM_BITS 3
+#define CFA_P70_EM_FKB_TL2_IVD_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL2_IVV_NUM_BITS 12
+#define CFA_P70_EM_FKB_TL2_IVT_NUM_BITS 3
+#define CFA_P70_EM_FKB_TL2_ETYPE_NUM_BITS 16
+#define CFA_P70_EM_FKB_TL3_TYPE_NUM_BITS 4
+#define CFA_P70_EM_FKB_TL3_SIP3_NUM_BITS 32
+#define CFA_P70_EM_FKB_TL3_SIP2_NUM_BITS 32
+#define CFA_P70_EM_FKB_TL3_SIP1_NUM_BITS 32
+#define CFA_P70_EM_FKB_TL3_SIP0_NUM_BITS 32
+#define CFA_P70_EM_FKB_TL3_DIP3_NUM_BITS 32
+#define CFA_P70_EM_FKB_TL3_DIP2_NUM_BITS 32
+#define CFA_P70_EM_FKB_TL3_DIP1_NUM_BITS 32
+#define CFA_P70_EM_FKB_TL3_DIP0_NUM_BITS 32
+#define CFA_P70_EM_FKB_TL3_TTL_NUM_BITS 8
+#define CFA_P70_EM_FKB_TL3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_EM_FKB_TL3_FID bit length is not fixed
+ * So the CFA_P70_EM_FKB_TL3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_EM_FKB_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_EM_FKB_TL3_QOS_NUM_BITS 8
+#define CFA_P70_EM_FKB_TL3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL3_DF_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL3_L3ERR_NUM_BITS 4
+#define CFA_P70_EM_FKB_TL4_TYPE_NUM_BITS 4
+#define CFA_P70_EM_FKB_TL4_SRC_NUM_BITS 16
+#define CFA_P70_EM_FKB_TL4_DST_NUM_BITS 16
+#define CFA_P70_EM_FKB_TL4_FLAGS_NUM_BITS 9
+#define CFA_P70_EM_FKB_TL4_SEQ_NUM_BITS 32
+#define CFA_P70_EM_FKB_TL4_PA_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL4_OPT_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL4_TCPTS_NUM_BITS 1
+#define CFA_P70_EM_FKB_TL4_ERR_NUM_BITS 4
+#define CFA_P70_EM_FKB_T_TYPE_NUM_BITS 5
+#define CFA_P70_EM_FKB_T_FLAGS_NUM_BITS 8
+#define CFA_P70_EM_FKB_T_IDS_NUM_BITS 24
+#define CFA_P70_EM_FKB_T_ID_NUM_BITS 32
+#define CFA_P70_EM_FKB_T_CTXTS_NUM_BITS 24
+#define CFA_P70_EM_FKB_T_CTXT_NUM_BITS 32
+#define CFA_P70_EM_FKB_T_QOS_NUM_BITS 3
+#define CFA_P70_EM_FKB_T_ERR_NUM_BITS 4
+#define CFA_P70_EM_FKB_L2_TYPE_NUM_BITS 2
+#define CFA_P70_EM_FKB_L2_DMAC_NUM_BITS 48
+#define CFA_P70_EM_FKB_L2_SMAC_NUM_BITS 48
+#define CFA_P70_EM_FKB_L2_DT_NUM_BITS 2
+#define CFA_P70_EM_FKB_L2_SA_NUM_BITS 1
+#define CFA_P70_EM_FKB_L2_NVT_NUM_BITS 2
+#define CFA_P70_EM_FKB_L2_OVP_NUM_BITS 3
+#define CFA_P70_EM_FKB_L2_OVD_NUM_BITS 1
+#define CFA_P70_EM_FKB_L2_OVV_NUM_BITS 12
+#define CFA_P70_EM_FKB_L2_OVT_NUM_BITS 3
+#define CFA_P70_EM_FKB_L2_IVP_NUM_BITS 3
+#define CFA_P70_EM_FKB_L2_IVD_NUM_BITS 1
+#define CFA_P70_EM_FKB_L2_IVV_NUM_BITS 12
+#define CFA_P70_EM_FKB_L2_IVT_NUM_BITS 3
+#define CFA_P70_EM_FKB_L2_ETYPE_NUM_BITS 16
+#define CFA_P70_EM_FKB_L3_TYPE_NUM_BITS 4
+#define CFA_P70_EM_FKB_L3_SIP3_NUM_BITS 32
+#define CFA_P70_EM_FKB_L3_SIP2_NUM_BITS 32
+#define CFA_P70_EM_FKB_L3_SIP1_NUM_BITS 32
+#define CFA_P70_EM_FKB_L3_SIP0_NUM_BITS 32
+#define CFA_P70_EM_FKB_L3_DIP3_NUM_BITS 32
+#define CFA_P70_EM_FKB_L3_DIP2_NUM_BITS 32
+#define CFA_P70_EM_FKB_L3_DIP1_NUM_BITS 32
+#define CFA_P70_EM_FKB_L3_DIP0_NUM_BITS 32
+#define CFA_P70_EM_FKB_L3_TTL_NUM_BITS 8
+#define CFA_P70_EM_FKB_L3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_EM_FKB_L3_FID bit length is not fixed
+ * So the CFA_P70_EM_FKB_L3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_EM_FKB_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_EM_FKB_L3_QOS_NUM_BITS 8
+#define CFA_P70_EM_FKB_L3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_EM_FKB_L3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_EM_FKB_L3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_EM_FKB_L3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_EM_FKB_L3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_EM_FKB_L3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_EM_FKB_L3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_EM_FKB_L3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_EM_FKB_L3_DF_NUM_BITS 1
+#define CFA_P70_EM_FKB_L3_L3ERR_NUM_BITS 4
+#define CFA_P70_EM_FKB_L4_TYPE_NUM_BITS 4
+#define CFA_P70_EM_FKB_L4_SRC_NUM_BITS 16
+#define CFA_P70_EM_FKB_L4_DST_NUM_BITS 16
+#define CFA_P70_EM_FKB_L4_FLAGS_NUM_BITS 9
+#define CFA_P70_EM_FKB_L4_SEQ_NUM_BITS 32
+#define CFA_P70_EM_FKB_L4_ACK_NUM_BITS 32
+#define CFA_P70_EM_FKB_L4_WIN_NUM_BITS 16
+#define CFA_P70_EM_FKB_L4_PA_NUM_BITS 1
+#define CFA_P70_EM_FKB_L4_OPT_NUM_BITS 1
+#define CFA_P70_EM_FKB_L4_TCPTS_NUM_BITS 1
+#define CFA_P70_EM_FKB_L4_TSVAL_NUM_BITS 32
+#define CFA_P70_EM_FKB_L4_TXECR_NUM_BITS 32
+#define CFA_P70_EM_FKB_L4_ERR_NUM_BITS 4
+
+/**
+ * Field length definitions for em key layout
+ */
+#define CFA_P70_EM_KL_RANGE_IDX_NUM_BITS 16
+#define CFA_P70_EM_KL_RANGE_PROFILE_NUM_BITS 4
+#define CFA_P70_EM_KL_CREC_TIMER_VALUE_NUM_BITS 4
+#define CFA_P70_EM_KL_CREC_STATE_NUM_BITS 5
+#define CFA_P70_EM_KL_CREC_TCP_MSB_OPP_INIT_NUM_BITS 1
+#define CFA_P70_EM_KL_CREC_TCP_MSB_OPP_NUM_BITS 18
+#define CFA_P70_EM_KL_CREC_TCP_MSB_LOC_NUM_BITS 18
+#define CFA_P70_EM_KL_CREC_TCP_WIN_NUM_BITS 5
+#define CFA_P70_EM_KL_CREC_TCP_UPDT_EN_NUM_BITS 1
+#define CFA_P70_EM_KL_CREC_TCP_DIR_NUM_BITS 1
+#define CFA_P70_EM_KL_METADATA_NUM_BITS 32
+#define CFA_P70_EM_KL_PROF_FUNC_NUM_BITS 8
+#define CFA_P70_EM_KL_META_PROF_NUM_BITS 3
+#define CFA_P70_EM_KL_RECYCLE_DEST_NUM_BITS 1
+#define CFA_P70_EM_KL_FC_PTR_NUM_BITS 28
+#define CFA_P70_EM_KL_FC_TYPE_NUM_BITS 2
+#define CFA_P70_EM_KL_FC_OP_NUM_BITS 1
+#define CFA_P70_EM_KL_PATHS_M1_NUM_BITS 4
+#define CFA_P70_EM_KL_ACT_REC_SIZE_NUM_BITS 5
+#define CFA_P70_EM_KL_RING_TABLE_IDX_NUM_BITS 9
+#define CFA_P70_EM_KL_DESTINATION_NUM_BITS 17
+#define CFA_P70_EM_KL_ACT_REC_PTR_NUM_BITS 26
+#define CFA_P70_EM_KL_ACT_HINT_NUM_BITS 2
+#define CFA_P70_EM_KL_STRENGTH_NUM_BITS 2
+#define CFA_P70_EM_KL_OPCODE_NUM_BITS 4
+#define CFA_P70_EM_KL_EPOCH1_NUM_BITS 6
+#define CFA_P70_EM_KL_EPOCH0_NUM_BITS 12
+#define CFA_P70_EM_KL_REC_SIZE_NUM_BITS 2
+#define CFA_P70_EM_KL_VALID_NUM_BITS 1
+#define CFA_P70_EM_KL_PROF_ID_NUM_BITS 8
+#define CFA_P70_EM_KL_L2CTXT_NUM_BITS 11
+#define CFA_P70_EM_KL_L2FUNC_NUM_BITS 8
+#define CFA_P70_EM_KL_PARIF_NUM_BITS 2
+#define CFA_P70_EM_KL_SPIF_NUM_BITS 2
+#define CFA_P70_EM_KL_SVIF_NUM_BITS 6
+#define CFA_P70_EM_KL_LCOS_NUM_BITS 3
+#define CFA_P70_EM_KL_META_HI_NUM_BITS 16
+#define CFA_P70_EM_KL_META_LO_NUM_BITS 16
+#define CFA_P70_EM_KL_RCYC_CNT_NUM_BITS 4
+#define CFA_P70_EM_KL_LOOPBACK_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL2_TYPE_NUM_BITS 2
+#define CFA_P70_EM_KL_OTL2_DMAC_NUM_BITS 48
+#define CFA_P70_EM_KL_OTL2_SMAC_NUM_BITS 48
+#define CFA_P70_EM_KL_OTL2_DT_NUM_BITS 2
+#define CFA_P70_EM_KL_OTL2_SA_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL2_NVT_NUM_BITS 2
+#define CFA_P70_EM_KL_OTL2_OVP_NUM_BITS 3
+#define CFA_P70_EM_KL_OTL2_OVD_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL2_OVV_NUM_BITS 12
+#define CFA_P70_EM_KL_OTL2_OVT_NUM_BITS 3
+#define CFA_P70_EM_KL_OTL2_IVP_NUM_BITS 3
+#define CFA_P70_EM_KL_OTL2_IVD_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL2_IVV_NUM_BITS 12
+#define CFA_P70_EM_KL_OTL2_IVT_NUM_BITS 3
+#define CFA_P70_EM_KL_OTL2_ETYPE_NUM_BITS 16
+#define CFA_P70_EM_KL_OTL3_TYPE_NUM_BITS 4
+#define CFA_P70_EM_KL_OTL3_SIP3_NUM_BITS 32
+#define CFA_P70_EM_KL_OTL3_SIP2_NUM_BITS 32
+#define CFA_P70_EM_KL_OTL3_SIP1_NUM_BITS 32
+#define CFA_P70_EM_KL_OTL3_SIP0_NUM_BITS 32
+#define CFA_P70_EM_KL_OTL3_DIP3_NUM_BITS 32
+#define CFA_P70_EM_KL_OTL3_DIP2_NUM_BITS 32
+#define CFA_P70_EM_KL_OTL3_DIP1_NUM_BITS 32
+#define CFA_P70_EM_KL_OTL3_DIP0_NUM_BITS 32
+#define CFA_P70_EM_KL_OTL3_TTL_NUM_BITS 8
+#define CFA_P70_EM_KL_OTL3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_EM_KL_OTL3_FID bit length is not fixed
+ * So the CFA_P70_EM_KL_OTL3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_EM_KL_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_EM_KL_OTL3_QOS_NUM_BITS 8
+#define CFA_P70_EM_KL_OTL3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL3_DF_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL3_L3ERR_NUM_BITS 4
+#define CFA_P70_EM_KL_OTL4_TYPE_NUM_BITS 4
+#define CFA_P70_EM_KL_OTL4_SRC_NUM_BITS 16
+#define CFA_P70_EM_KL_OTL4_DST_NUM_BITS 16
+#define CFA_P70_EM_KL_OTL4_FLAGS_NUM_BITS 9
+#define CFA_P70_EM_KL_OTL4_SEQ_NUM_BITS 32
+#define CFA_P70_EM_KL_OTL4_PA_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL4_OPT_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL4_TCPTS_NUM_BITS 1
+#define CFA_P70_EM_KL_OTL4_ERR_NUM_BITS 4
+#define CFA_P70_EM_KL_OT_TYPE_NUM_BITS 5
+#define CFA_P70_EM_KL_OT_FLAGS_NUM_BITS 8
+#define CFA_P70_EM_KL_OT_IDS_NUM_BITS 24
+#define CFA_P70_EM_KL_OT_ID_NUM_BITS 32
+#define CFA_P70_EM_KL_OT_CTXTS_NUM_BITS 24
+#define CFA_P70_EM_KL_OT_CTXT_NUM_BITS 32
+#define CFA_P70_EM_KL_OT_QOS_NUM_BITS 3
+#define CFA_P70_EM_KL_OT_ERR_NUM_BITS 4
+#define CFA_P70_EM_KL_TL2_TYPE_NUM_BITS 2
+#define CFA_P70_EM_KL_TL2_DMAC_NUM_BITS 48
+#define CFA_P70_EM_KL_TL2_SMAC_NUM_BITS 48
+#define CFA_P70_EM_KL_TL2_DT_NUM_BITS 2
+#define CFA_P70_EM_KL_TL2_SA_NUM_BITS 1
+#define CFA_P70_EM_KL_TL2_NVT_NUM_BITS 2
+#define CFA_P70_EM_KL_TL2_OVP_NUM_BITS 3
+#define CFA_P70_EM_KL_TL2_OVD_NUM_BITS 1
+#define CFA_P70_EM_KL_TL2_OVV_NUM_BITS 12
+#define CFA_P70_EM_KL_TL2_OVT_NUM_BITS 3
+#define CFA_P70_EM_KL_TL2_IVP_NUM_BITS 3
+#define CFA_P70_EM_KL_TL2_IVD_NUM_BITS 1
+#define CFA_P70_EM_KL_TL2_IVV_NUM_BITS 12
+#define CFA_P70_EM_KL_TL2_IVT_NUM_BITS 3
+#define CFA_P70_EM_KL_TL2_ETYPE_NUM_BITS 16
+#define CFA_P70_EM_KL_TL3_TYPE_NUM_BITS 4
+#define CFA_P70_EM_KL_TL3_SIP3_NUM_BITS 32
+#define CFA_P70_EM_KL_TL3_SIP2_NUM_BITS 32
+#define CFA_P70_EM_KL_TL3_SIP1_NUM_BITS 32
+#define CFA_P70_EM_KL_TL3_SIP0_NUM_BITS 32
+#define CFA_P70_EM_KL_TL3_DIP3_NUM_BITS 32
+#define CFA_P70_EM_KL_TL3_DIP2_NUM_BITS 32
+#define CFA_P70_EM_KL_TL3_DIP1_NUM_BITS 32
+#define CFA_P70_EM_KL_TL3_DIP0_NUM_BITS 32
+#define CFA_P70_EM_KL_TL3_TTL_NUM_BITS 8
+#define CFA_P70_EM_KL_TL3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_EM_KL_TL3_FID bit length is not fixed
+ * So the CFA_P70_EM_KL_TL3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_EM_KL_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_EM_KL_TL3_QOS_NUM_BITS 8
+#define CFA_P70_EM_KL_TL3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_EM_KL_TL3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_EM_KL_TL3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_EM_KL_TL3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_EM_KL_TL3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_EM_KL_TL3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_EM_KL_TL3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_EM_KL_TL3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_EM_KL_TL3_DF_NUM_BITS 1
+#define CFA_P70_EM_KL_TL3_L3ERR_NUM_BITS 4
+#define CFA_P70_EM_KL_TL4_TYPE_NUM_BITS 4
+#define CFA_P70_EM_KL_TL4_SRC_NUM_BITS 16
+#define CFA_P70_EM_KL_TL4_DST_NUM_BITS 16
+#define CFA_P70_EM_KL_TL4_FLAGS_NUM_BITS 9
+#define CFA_P70_EM_KL_TL4_SEQ_NUM_BITS 32
+#define CFA_P70_EM_KL_TL4_PA_NUM_BITS 1
+#define CFA_P70_EM_KL_TL4_OPT_NUM_BITS 1
+#define CFA_P70_EM_KL_TL4_TCPTS_NUM_BITS 1
+#define CFA_P70_EM_KL_TL4_ERR_NUM_BITS 4
+#define CFA_P70_EM_KL_T_TYPE_NUM_BITS 5
+#define CFA_P70_EM_KL_T_FLAGS_NUM_BITS 8
+#define CFA_P70_EM_KL_T_IDS_NUM_BITS 24
+#define CFA_P70_EM_KL_T_ID_NUM_BITS 32
+#define CFA_P70_EM_KL_T_CTXTS_NUM_BITS 24
+#define CFA_P70_EM_KL_T_CTXT_NUM_BITS 32
+#define CFA_P70_EM_KL_T_QOS_NUM_BITS 3
+#define CFA_P70_EM_KL_T_ERR_NUM_BITS 4
+#define CFA_P70_EM_KL_L2_TYPE_NUM_BITS 2
+#define CFA_P70_EM_KL_L2_DMAC_NUM_BITS 48
+#define CFA_P70_EM_KL_L2_SMAC_NUM_BITS 48
+#define CFA_P70_EM_KL_L2_DT_NUM_BITS 2
+#define CFA_P70_EM_KL_L2_SA_NUM_BITS 1
+#define CFA_P70_EM_KL_L2_NVT_NUM_BITS 2
+#define CFA_P70_EM_KL_L2_OVP_NUM_BITS 3
+#define CFA_P70_EM_KL_L2_OVD_NUM_BITS 1
+#define CFA_P70_EM_KL_L2_OVV_NUM_BITS 12
+#define CFA_P70_EM_KL_L2_OVT_NUM_BITS 3
+#define CFA_P70_EM_KL_L2_IVP_NUM_BITS 3
+#define CFA_P70_EM_KL_L2_IVD_NUM_BITS 1
+#define CFA_P70_EM_KL_L2_IVV_NUM_BITS 12
+#define CFA_P70_EM_KL_L2_IVT_NUM_BITS 3
+#define CFA_P70_EM_KL_L2_ETYPE_NUM_BITS 16
+#define CFA_P70_EM_KL_L3_TYPE_NUM_BITS 4
+#define CFA_P70_EM_KL_L3_SIP3_NUM_BITS 32
+#define CFA_P70_EM_KL_L3_SIP2_NUM_BITS 32
+#define CFA_P70_EM_KL_L3_SIP1_NUM_BITS 32
+#define CFA_P70_EM_KL_L3_SIP0_NUM_BITS 32
+#define CFA_P70_EM_KL_L3_DIP3_NUM_BITS 32
+#define CFA_P70_EM_KL_L3_DIP2_NUM_BITS 32
+#define CFA_P70_EM_KL_L3_DIP1_NUM_BITS 32
+#define CFA_P70_EM_KL_L3_DIP0_NUM_BITS 32
+#define CFA_P70_EM_KL_L3_TTL_NUM_BITS 8
+#define CFA_P70_EM_KL_L3_PROT_NUM_BITS 8
+/**
+ * CFA_P70_EM_KL_L3_FID bit length is not fixed
+ * So the CFA_P70_EM_KL_L3_FID_NUMBITS macro is defined with arguments
+ */
+#define CFA_P70_EM_KL_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20)
+#define CFA_P70_EM_KL_L3_QOS_NUM_BITS 8
+#define CFA_P70_EM_KL_L3_IEH_NONEXT_NUM_BITS 1
+#define CFA_P70_EM_KL_L3_IEH_SEP_NUM_BITS 1
+#define CFA_P70_EM_KL_L3_IEH_AUTH_NUM_BITS 1
+#define CFA_P70_EM_KL_L3_IEH_DEST_NUM_BITS 1
+#define CFA_P70_EM_KL_L3_IEH_FRAG_NUM_BITS 1
+#define CFA_P70_EM_KL_L3_IEH_RTHDR_NUM_BITS 1
+#define CFA_P70_EM_KL_L3_IEH_HOP_NUM_BITS 1
+#define CFA_P70_EM_KL_L3_IEH_1FRAG_NUM_BITS 1
+#define CFA_P70_EM_KL_L3_DF_NUM_BITS 1
+#define CFA_P70_EM_KL_L3_L3ERR_NUM_BITS 4
+#define CFA_P70_EM_KL_L4_TYPE_NUM_BITS 4
+#define CFA_P70_EM_KL_L4_SRC_NUM_BITS 16
+#define CFA_P70_EM_KL_L4_DST_NUM_BITS 16
+#define CFA_P70_EM_KL_L4_FLAGS_NUM_BITS 9
+#define CFA_P70_EM_KL_L4_SEQ_NUM_BITS 32
+#define CFA_P70_EM_KL_L4_ACK_NUM_BITS 32
+#define CFA_P70_EM_KL_L4_WIN_NUM_BITS 16
+#define CFA_P70_EM_KL_L4_PA_NUM_BITS 1
+#define CFA_P70_EM_KL_L4_OPT_NUM_BITS 1
+#define CFA_P70_EM_KL_L4_TCPTS_NUM_BITS 1
+#define CFA_P70_EM_KL_L4_TSVAL_NUM_BITS 32
+#define CFA_P70_EM_KL_L4_TXECR_NUM_BITS 32
+#define CFA_P70_EM_KL_L4_ERR_NUM_BITS 4
+
+/**
+ * Field length definitions for action
+ */
+#define CFA_P70_ACT_TYPE_NUM_BITS 3
+#define CFA_P70_ACT_DROP_NUM_BITS 1
+#define CFA_P70_ACT_VLAN_DELETE_NUM_BITS 2
+#define CFA_P70_ACT_DEST_NUM_BITS 7
+#define CFA_P70_ACT_DEST_OP_NUM_BITS 2
+#define CFA_P70_ACT_DECAP_NUM_BITS 5
+#define CFA_P70_ACT_MIRRORING_NUM_BITS 5
+#define CFA_P70_ACT_METER_PTR_NUM_BITS 10
+#define CFA_P70_ACT_STAT0_OFF_NUM_BITS 3
+#define CFA_P70_ACT_STAT0_OP_NUM_BITS 1
+#define CFA_P70_ACT_STAT0_CTR_TYPE_NUM_BITS 2
+#define CFA_P70_ACT_MOD_OFF_NUM_BITS 5
+#define CFA_P70_ACT_ENC_OFF_NUM_BITS 6
+#define CFA_P70_ACT_SRC_OFF_NUM_BITS 4
+#define CFA_P70_ACT_COMPACT_RSVD_0_NUM_BITS 4
+#define CFA_P70_ACT_STAT0_PTR_NUM_BITS 28
+#define CFA_P70_ACT_STAT1_PTR_NUM_BITS 28
+#define CFA_P70_ACT_STAT1_OP_NUM_BITS 1
+#define CFA_P70_ACT_STAT1_CTR_TYPE_NUM_BITS 2
+#define CFA_P70_ACT_MOD_PTR_NUM_BITS 28
+#define CFA_P70_ACT_ENC_PTR_NUM_BITS 28
+#define CFA_P70_ACT_SRC_PTR_NUM_BITS 28
+#define CFA_P70_ACT_FULL_RSVD_0_NUM_BITS 7
+#define CFA_P70_ACT_SRC_KO_EN_NUM_BITS 1
+#define CFA_P70_ACT_MCG_RSVD_0_NUM_BITS 2
+#define CFA_P70_ACT_NEXT_PTR_NUM_BITS 26
+#define CFA_P70_ACT_PTR0_ACT_HINT_NUM_BITS 2
+#define CFA_P70_ACT_PTR0_ACT_REC_PTR_NUM_BITS 26
+#define CFA_P70_ACT_PTR1_ACT_HINT_NUM_BITS 2
+#define CFA_P70_ACT_PTR1_ACT_REC_PTR_NUM_BITS 26
+#define CFA_P70_ACT_PTR2_ACT_HINT_NUM_BITS 2
+#define CFA_P70_ACT_PTR2_ACT_REC_PTR_NUM_BITS 26
+#define CFA_P70_ACT_PTR3_ACT_HINT_NUM_BITS 2
+#define CFA_P70_ACT_PTR3_ACT_REC_PTR_NUM_BITS 26
+#define CFA_P70_ACT_PTR4_ACT_HINT_NUM_BITS 2
+#define CFA_P70_ACT_PTR4_ACT_REC_PTR_NUM_BITS 26
+#define CFA_P70_ACT_PTR5_ACT_HINT_NUM_BITS 2
+#define CFA_P70_ACT_PTR5_ACT_REC_PTR_NUM_BITS 26
+#define CFA_P70_ACT_PTR6_ACT_HINT_NUM_BITS 2
+#define CFA_P70_ACT_PTR6_ACT_REC_PTR_NUM_BITS 26
+#define CFA_P70_ACT_PTR7_ACT_HINT_NUM_BITS 2
+#define CFA_P70_ACT_PTR7_ACT_REC_PTR_NUM_BITS 26
+#define CFA_P70_ACT_MCG_SUBSEQ_RSVD_0_NUM_BITS 3
+#define CFA_P70_ACT_MOD_MODIFY_ACT_HDR_NUM_BITS 16
+#define CFA_P70_ACT_MOD_MD_UPDT_DATA_NUM_BITS 32
+#define CFA_P70_ACT_MOD_MD_UPDT_PROF_NUM_BITS 4
+
+/**
+ * Enumeration definition for field 'md_op'
+ */
+enum cfa_p70_md_op {
+ /*
+ * Normal Metadata update: ! md = (md & ~md_prof.mask) | (md_prof.mask &
+ * md_data)
+ */
+ CFA_P70_MD_OP_NORMAL = 0,
+ /*
+ * L2 Hash Metadata update: ! md = (md & ~md_prof.mask) | (md_prof.mask
+ * & hash_l2(seed,packet))
+ */
+ CFA_P70_MD_OP_L2_HASH = 1,
+ /*
+ * L4 Hash Metadata update: ! md = (md & ~ md_prof.mask) | (md_prof.mask
+ * & hash_l3l4(seed,packet))
+ */
+ CFA_P70_MD_OP_L4_HASH = 2,
+ /*
+ * SVIF insert Metadata update: ! md = (md & ~ md_prof.mask) |
+ * (md_prof.mask & zero_extend(svif))
+ */
+ CFA_P70_MD_OP_SVIF = 3,
+};
+#define CFA_P70_ACT_MOD_MD_UPDT_OP_NUM_BITS 2
+#define CFA_P70_ACT_MOD_MD_UPDT_RSVD_0_NUM_BITS 10
+#define CFA_P70_ACT_MOD_MD_UPDT_TOP_NUM_BITS 48
+#define CFA_P70_ACT_MOD_RM_OVLAN_NUM_BITS 32
+#define CFA_P70_ACT_MOD_RM_IVLAN_NUM_BITS 32
+#define CFA_P70_ACT_MOD_RPL_IVLAN_NUM_BITS 32
+#define CFA_P70_ACT_MOD_RPL_OVLAN_NUM_BITS 32
+#define CFA_P70_ACT_MOD_TTL_UPDT_OP_NUM_BITS 15
+#define CFA_P70_ACT_MOD_TTL_UPDT_ALT_VID_NUM_BITS 12
+#define CFA_P70_ACT_MOD_TTL_UPDT_ALT_PFID_NUM_BITS 5
+#define CFA_P70_ACT_MOD_TTL_UPDT_TOP_NUM_BITS 32
+#define CFA_P70_ACT_MOD_TNL_MODIFY_DEL_NUM_BITS 16
+#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_NEW_PROT_NUM_BITS 8
+#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_EXIST_PROT_NUM_BITS 8
+#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_VEC_NUM_BITS 16
+#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_TOP_NUM_BITS 32
+#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_NEW_PROT_NUM_BITS 16
+#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_EXIST_PROT_NUM_BITS 16
+#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_VEC_NUM_BITS 16
+#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_TOP_NUM_BITS 48
+#define CFA_P70_ACT_MOD_UPDT_FIELD_DATA0_NUM_BITS 32
+#define CFA_P70_ACT_MOD_UPDT_FIELD_VEC_RSVD_NUM_BITS 15
+#define CFA_P70_ACT_MOD_UPDT_FIELD_VEC_KID_NUM_BITS 1
+#define CFA_P70_ACT_MOD_UPDT_FIELD_TOP_NUM_BITS 48
+#define CFA_P70_ACT_MOD_SMAC_NUM_BITS 48
+#define CFA_P70_ACT_MOD_DMAC_NUM_BITS 48
+#define CFA_P70_ACT_MOD_SIPV6_NUM_BITS 128
+#define CFA_P70_ACT_MOD_DIPV6_NUM_BITS 128
+#define CFA_P70_ACT_MOD_SIPV4_NUM_BITS 32
+#define CFA_P70_ACT_MOD_DIPV4_NUM_BITS 32
+#define CFA_P70_ACT_MOD_SPORT_NUM_BITS 16
+#define CFA_P70_ACT_MOD_DPORT_NUM_BITS 16
+
+/**
+ * Enumeration definition for field 'ecv_tnl'
+ */
+enum cfa_p70_ecv_tnl {
+ /* No tunnel header will be added. */
+ CFA_P70_ECV_TNL_NOP = 0,
+ /*
+ * Generic full header will be added after inserted L2, L3, or L4
+ * header. The first byte of the tunnel body will be the length of the
+ * inserted tunnel.
+ */
+ CFA_P70_ECV_TNL_GENERIC = 1,
+ /* VXLAN tunnel header will be added. */
+ CFA_P70_ECV_TNL_VXLAN = 2,
+ /* NGE (VXLAN2) Header will be added. */
+ CFA_P70_ECV_TNL_NGE = 3,
+ /* NVGRE Header will be added. */
+ CFA_P70_ECV_TNL_NVGRE = 4,
+ /* GRE Header will be added. */
+ CFA_P70_ECV_TNL_GRE = 5,
+ /*
+ * Generic header after existing L4 header will be added. The first byte
+ * of the tunnel body will be the length of the inserted tunnel.
+ */
+ CFA_P70_ECV_TNL_GENERIC_L4 = 6,
+ /*
+ * Generic header after existing tunnel will be added. The first byte of
+ * the tunnel body will be the length of the inserted tunnel.
+ */
+ CFA_P70_ECV_TNL_GENERIC_TUN = 7,
+};
+#define CFA_P70_ACT_ENC_ECV_TNL_NUM_BITS 3
+
+/**
+ * Enumeration definition for field 'ecv_l4'
+ */
+enum cfa_p70_ecv_l4 {
+ /* No L4 Header */
+ CFA_P70_ECV_L4_NOP = 0,
+ /* No L4 Header */
+ CFA_P70_ECV_L4_NOP1 = 1,
+ /* No L4 Header */
+ CFA_P70_ECV_L4_NOP2 = 2,
+ /* No L4 Header */
+ CFA_P70_ECV_L4_NOP3 = 3,
+ /* Add L4 Header without entropy and with CS=0. */
+ CFA_P70_ECV_L4_L4 = 4,
+ /* Add L4 Header without entropy and with CS=calculated. */
+ CFA_P70_ECV_L4_L4_CS = 5,
+ /* Add L4 Header with entropy and with CS=0. */
+ CFA_P70_ECV_L4_L4_ENT = 6,
+ /* Add L4 Header with entropy and with CS=calculated. */
+ CFA_P70_ECV_L4_L4_ENT_CS = 7,
+};
+#define CFA_P70_ACT_ENC_ECV_L4_NUM_BITS 3
+
+/**
+ * Enumeration definition for field 'ecv_l3'
+ */
+enum cfa_p70_ecv_l3 {
+ /* No L3 Header */
+ CFA_P70_ECV_L3_NOP = 0,
+ /* No L3 Header */
+ CFA_P70_ECV_L3_NOP1 = 1,
+ /* No L3 Header */
+ CFA_P70_ECV_L3_NOP2 = 2,
+ /* No L3 Header */
+ CFA_P70_ECV_L3_NOP3 = 3,
+ /* Add IPV4 Header */
+ CFA_P70_ECV_L3_IPV4 = 4,
+ /* Add IPV4 Header */
+ CFA_P70_ECV_L3_IPV6 = 5,
+ /* Add MPLS (8847) Header */
+ CFA_P70_ECV_L3_MPLS8847 = 6,
+ /* Add MPLS (8848) Header */
+ CFA_P70_ECV_L3_MPLS8848 = 7,
+};
+#define CFA_P70_ACT_ENC_ECV_L3_NUM_BITS 3
+#define CFA_P70_ACT_ENC_ECV_L2_NUM_BITS 1
+
+/**
+ * Enumeration definition for field 'ecv_vtag'
+ */
+enum cfa_p70_ecv_vtag {
+ /* No VLAN tag will be added. */
+ CFA_P70_ECV_VTAG_NOP = 0,
+ /* Add one VLAN tag using the PRI field from the encap record. */
+ CFA_P70_ECV_VTAG_ADD1_USE_PRI = 1,
+ /* Add one VLAN tag remap wit inner VLAN Tag PRI field. */
+ CFA_P70_ECV_VTAG_ADD1_REMAP_INNER_PRI = 2,
+ /* Add one VLAN tag remap with diff serve field. */
+ CFA_P70_ECV_VTAG_ADD1_REMAP_DIFF = 3,
+ /* Add two VLAN tags using the PRI field from the encap record. */
+ CFA_P70_ECV_VTAG_ADD2_USE_PRI = 4,
+ /* Add two VLAN tag remap with diff serve field. */
+ CFA_P70_ECV_VTAG_ADD2_REMAP_DIFF = 5,
+ /* Add zero VLAN tags remap with inner VLAN Tag PRI Field. */
+ CFA_P70_ECV_VTAG_ADD0_REMAP_INNER_PRI = 6,
+ /* Add zero VLAN tags remap with diff serve field. */
+ CFA_P70_ECV_VTAG_ADD0_REMAP_DIFF = 7,
+ /* Add zero VLAG tags remap with immediate PRI=0. */
+ CFA_P70_ECV_VTAG_ADD0_IMMED_PRI0 = 8,
+ /* Add zero VLAG tags remap with immediate PRI=1. */
+ CFA_P70_ECV_VTAG_ADD0_IMMED_PRI1 = 9,
+ /* Add zero VLAG tags remap with immediate PRI=2. */
+ CFA_P70_ECV_VTAG_ADD0_IMMED_PRI2 = 10,
+ /* Add zero VLAG tags remap with immediate PRI=3. */
+ CFA_P70_ECV_VTAG_ADD0_IMMED_PRI3 = 11,
+ /* Add zero VLAG tags remap with immediate PRI=4. */
+ CFA_P70_ECV_VTAG_ADD0_IMMED_PRI4 = 12,
+ /* Add zero VLAG tags remap with immediate PRI=5. */
+ CFA_P70_ECV_VTAG_ADD0_IMMED_PRI5 = 13,
+ /* Add zero VLAG tags remap with immediate PRI=6. */
+ CFA_P70_ECV_VTAG_ADD0_IMMED_PRI6 = 14,
+ /* Add zero VLAG tags remap with immediate PRI=7. */
+ CFA_P70_ECV_VTAG_ADD0_IMMED_PRI7 = 15,
+};
+#define CFA_P70_ACT_ENC_ECV_VTAG_NUM_BITS 4
+#define CFA_P70_ACT_ENC_ECV_EC_NUM_BITS 1
+#define CFA_P70_ACT_ENC_ECV_VALID_NUM_BITS 1
+#define CFA_P70_ACT_ENC_EC_IP_TTL_IH_NUM_BITS 1
+#define CFA_P70_ACT_ENC_EC_IP_TOS_IH_NUM_BITS 1
+#define CFA_P70_ACT_ENC_EC_TUN_QOS_NUM_BITS 3
+#define CFA_P70_ACT_ENC_EC_GRE_SET_K_NUM_BITS 1
+
+/**
+ * Enumeration definition for field 'enccfg_dmac_ovr'
+ */
+enum cfa_p70_enccfg_dmac_ovr {
+ /* use encap record DMAC */
+ CFA_P70_ENCCFG_DMAC_OVR_ENCAP = 0,
+ /* re-use existing inner L2 header DMAC */
+ CFA_P70_ENCCFG_DMAC_OVR_INNER_DMAC = 1,
+ /* re-use existing tunnel L2 header DMAC */
+ CFA_P70_ENCCFG_DMAC_OVR_TUNNEL_DMAC = 2,
+ /* re-use existing outer-most L2 header DMAC */
+ CFA_P70_ENCCFG_DMAC_OVR_OUTER_DMAC = 3,
+};
+#define CFA_P70_ACT_ENC_EC_DMAC_OVR_NUM_BITS 2
+
+/**
+ * Enumeration definition for field 'enccfg_vlan_ovr'
+ */
+enum cfa_p70_enccfg_vlan_ovr {
+ /* use only encap record VLAN tags */
+ CFA_P70_ENCCFG_VLAN_OVR_ENCAP = 0,
+ /* use only existing inner L2 header VLAN tags */
+ CFA_P70_ENCCFG_VLAN_OVR_INNER_L2 = 1,
+ /* use only existing tunnel L2 header VLAN tags */
+ CFA_P70_ENCCFG_VLAN_OVR_TUNNEL_L2 = 2,
+ /* use only existing outer-most L2 header VLAN tags */
+ CFA_P70_ENCCFG_VLAN_OVR_OUTER_L2 = 3,
+ /* include inner VLAN Tag from existing inner L2 header (keeps 1 TAG) */
+ CFA_P70_ENCCFG_VLAN_OVR_INNER_INNER = 4,
+ /* include outer VLAN Tag from existing inner L2 header (keeps 1 TAG) */
+ CFA_P70_ENCCFG_VLAN_OVR_INNER_OUTER = 5,
+ /*
+ * include inner VLAN Tag from existing outer-most L2 header (keeps 1
+ * TAG)
+ */
+ CFA_P70_ENCCFG_VLAN_OVR_OUTER_INNER = 6,
+ /*
+ * include outer VLAN Tag from existing outer-most L2 header (keeps 1
+ * TAG)
+ */
+ CFA_P70_ENCCFG_VLAN_OVR_OUTER_OUTER = 7,
+};
+#define CFA_P70_ACT_ENC_EC_VLAN_OVR_NUM_BITS 3
+
+/**
+ * Enumeration definition for field 'enccfg_smac_ovr'
+ */
+enum cfa_p70_enccfg_smac_ovr {
+ /* use only source property record SMAC */
+ CFA_P70_ENCCFG_SMAC_OVR_ENCAP = 0,
+ /* re-use existing inner L2 header SMAC */
+ CFA_P70_ENCCFG_SMAC_OVR_INNER_SMAC = 1,
+ /* re-use existing tunnel L2 header SMAC */
+ CFA_P70_ENCCFG_SMAC_OVR_TUNNEL_SMAC = 2,
+ /* re-use existing outer-most L2 header SMAC */
+ CFA_P70_ENCCFG_SMAC_OVR_OUTER_SMAC = 3,
+ /* re-use existing inner L2 header DMAC */
+ CFA_P70_ENCCFG_SMAC_OVR_INNER_DMAC = 5,
+ /* re-use existing tunnel L2 header DMAC */
+ CFA_P70_ENCCFG_SMAC_OVR_TUNNEL_DMAC = 6,
+ /* re-use existing outer-most L2 header DMAC */
+ CFA_P70_ENCCFG_SMAC_OVR_OUTER_DMAC = 7,
+};
+#define CFA_P70_ACT_ENC_EC_SMAC_OVR_NUM_BITS 3
+
+/**
+ * Enumeration definition for field 'enccfg_ipv4_id_ctrl'
+ */
+enum cfa_p70_enccfg_ipv4_id_ctrl {
+ /* use encap record IPv4 ID field */
+ CFA_P70_ENCCFG_IPV4_ID_CTRL_ENCAP = 0,
+ /* inherit from next existing IPv4 header ID field */
+ CFA_P70_ENCCFG_IPV4_ID_CTRL_INHERIT = 2,
+ /* use CFA incrementing IPv4 ID counter */
+ CFA_P70_ENCCFG_IPV4_ID_CTRL_INCREMENT = 3,
+};
+#define CFA_P70_ACT_ENC_EC_IPV4_ID_CTRL_NUM_BITS 2
+#define CFA_P70_ACT_ENC_L2_DMAC_NUM_BITS 48
+#define CFA_P70_ACT_ENC_VLAN1_TAG_VID_NUM_BITS 12
+#define CFA_P70_ACT_ENC_VLAN1_TAG_DE_NUM_BITS 1
+#define CFA_P70_ACT_ENC_VLAN1_TAG_PRI_NUM_BITS 3
+#define CFA_P70_ACT_ENC_VLAN1_TAG_TPID_NUM_BITS 16
+#define CFA_P70_ACT_ENC_VLAN2_IT_VID_NUM_BITS 12
+#define CFA_P70_ACT_ENC_VLAN2_IT_DE_NUM_BITS 1
+#define CFA_P70_ACT_ENC_VLAN2_IT_PRI_NUM_BITS 3
+#define CFA_P70_ACT_ENC_VLAN2_IT_TPID_NUM_BITS 16
+#define CFA_P70_ACT_ENC_VLAN2_OT_VID_NUM_BITS 12
+#define CFA_P70_ACT_ENC_VLAN2_OT_DE_NUM_BITS 1
+#define CFA_P70_ACT_ENC_VLAN2_OT_PRI_NUM_BITS 3
+#define CFA_P70_ACT_ENC_VLAN2_OT_TPID_NUM_BITS 16
+#define CFA_P70_ACT_ENC_IPV4_ID_NUM_BITS 16
+#define CFA_P70_ACT_ENC_IPV4_TOS_NUM_BITS 8
+#define CFA_P70_ACT_ENC_IPV4_HLEN_NUM_BITS 4
+#define CFA_P70_ACT_ENC_IPV4_VER_NUM_BITS 4
+#define CFA_P70_ACT_ENC_IPV4_PROT_NUM_BITS 8
+#define CFA_P70_ACT_ENC_IPV4_TTL_NUM_BITS 8
+#define CFA_P70_ACT_ENC_IPV4_FRAG_NUM_BITS 13
+#define CFA_P70_ACT_ENC_IPV4_FLAGS_NUM_BITS 3
+#define CFA_P70_ACT_ENC_IPV4_DEST_NUM_BITS 32
+#define CFA_P70_ACT_ENC_IPV6_FLOW_LABEL_NUM_BITS 20
+#define CFA_P70_ACT_ENC_IPV6_TRAFFIC_CLASS_NUM_BITS 8
+#define CFA_P70_ACT_ENC_IPV6_VER_NUM_BITS 4
+#define CFA_P70_ACT_ENC_IPV6_HOP_LIMIT_NUM_BITS 8
+#define CFA_P70_ACT_ENC_IPV6_NEXT_HEADER_NUM_BITS 8
+#define CFA_P70_ACT_ENC_IPV6_PAYLOAD_LENGTH_NUM_BITS 16
+#define CFA_P70_ACT_ENC_IPV6_DEST_NUM_BITS 128
+#define CFA_P70_ACT_ENC_MPLS_TAG1_NUM_BITS 32
+#define CFA_P70_ACT_ENC_MPLS_TAG2_NUM_BITS 32
+#define CFA_P70_ACT_ENC_MPLS_TAG3_NUM_BITS 32
+#define CFA_P70_ACT_ENC_MPLS_TAG4_NUM_BITS 32
+#define CFA_P70_ACT_ENC_MPLS_TAG5_NUM_BITS 32
+#define CFA_P70_ACT_ENC_MPLS_TAG6_NUM_BITS 32
+#define CFA_P70_ACT_ENC_MPLS_TAG7_NUM_BITS 32
+#define CFA_P70_ACT_ENC_MPLS_TAG8_NUM_BITS 32
+#define CFA_P70_ACT_ENC_L4_DEST_PORT_NUM_BITS 16
+#define CFA_P70_ACT_ENC_L4_SRC_PORT_NUM_BITS 16
+#define CFA_P70_ACT_ENC_TNL_VXLAN_NEXT_PROT_NUM_BITS 8
+#define CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_0_NUM_BITS 16
+#define CFA_P70_ACT_ENC_TNL_VXLAN_FLAGS_NUM_BITS 8
+#define CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_1_NUM_BITS 8
+#define CFA_P70_ACT_ENC_TNL_VXLAN_VNI_NUM_BITS 24
+#define CFA_P70_ACT_ENC_TNL_NGE_PROT_TYPE_NUM_BITS 16
+#define CFA_P70_ACT_ENC_TNL_NGE_RSVD_0_NUM_BITS 6
+#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_C_NUM_BITS 1
+#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_O_NUM_BITS 1
+#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_OPT_LEN_NUM_BITS 6
+#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_VER_NUM_BITS 2
+#define CFA_P70_ACT_ENC_TNL_NGE_RSVD_1_NUM_BITS 8
+#define CFA_P70_ACT_ENC_TNL_NGE_VNI_NUM_BITS 24
+#define CFA_P70_ACT_ENC_TNL_NGE_OPTIONS_NUM_BITS 64
+#define CFA_P70_ACT_ENC_TNL_NVGRE_FLOW_ID_NUM_BITS 8
+#define CFA_P70_ACT_ENC_TNL_NVGRE_VSID_NUM_BITS 24
+#define CFA_P70_ACT_ENC_TNL_GRE_KEY_NUM_BITS 32
+#define CFA_P70_ACT_ENC_TNL_GENERIC_TID_NUM_BITS 8
+#define CFA_P70_ACT_ENC_TNL_GENERIC_LENGTH_NUM_BITS 8
+#define CFA_P70_ACT_ENC_TNL_GENERIC_HEADER_NUM_BITS 32
+#define CFA_P70_ACT_SRC_MAC_NUM_BITS 48
+#define CFA_P70_ACT_SRC_IPV4_ADDR_NUM_BITS 32
+#define CFA_P70_ACT_SRC_IPV6_ADDR_NUM_BITS 128
+#define CFA_P70_ACT_STAT0_B16_FPC_NUM_BITS 64
+#define CFA_P70_ACT_STAT1_B16_FPC_NUM_BITS 64
+#define CFA_P70_ACT_STAT0_B16_FBC_NUM_BITS 64
+#define CFA_P70_ACT_STAT1_B16_FBC_NUM_BITS 64
+#define CFA_P70_ACT_STAT0_B24_FPC_NUM_BITS 64
+#define CFA_P70_ACT_STAT1_B24_FPC_NUM_BITS 64
+#define CFA_P70_ACT_STAT0_B24_FBC_NUM_BITS 64
+#define CFA_P70_ACT_STAT1_B24_FBC_NUM_BITS 64
+#define CFA_P70_ACT_STAT0_B24_TIMESTAMP_NUM_BITS 32
+#define CFA_P70_ACT_STAT1_B24_TIMESTAMP_NUM_BITS 32
+#define CFA_P70_ACT_STAT0_B24_TCP_FLAGS_NUM_BITS 9
+#define CFA_P70_ACT_STAT1_B24_TCP_FLAGS_NUM_BITS 9
+#define CFA_P70_ACT_STAT0_B24_UNUSED_0_NUM_BITS 23
+#define CFA_P70_ACT_STAT1_B24_UNUSED_0_NUM_BITS 23
+#define CFA_P70_ACT_STAT0_B32A_FPC_NUM_BITS 64
+#define CFA_P70_ACT_STAT1_B32A_FPC_NUM_BITS 64
+#define CFA_P70_ACT_STAT0_B32A_FBC_NUM_BITS 64
+#define CFA_P70_ACT_STAT1_B32A_FBC_NUM_BITS 64
+#define CFA_P70_ACT_STAT0_B32A_MPC_NUM_BITS 64
+#define CFA_P70_ACT_STAT1_B32A_MPC_NUM_BITS 64
+#define CFA_P70_ACT_STAT0_B32A_MBC_NUM_BITS 64
+#define CFA_P70_ACT_STAT1_B32A_MBC_NUM_BITS 64
+#define CFA_P70_ACT_STAT0_B32B_FPC_NUM_BITS 64
+#define CFA_P70_ACT_STAT1_B32B_FPC_NUM_BITS 64
+#define CFA_P70_ACT_STAT0_B32B_FBC_NUM_BITS 64
+#define CFA_P70_ACT_STAT1_B32B_FBC_NUM_BITS 64
+#define CFA_P70_ACT_STAT0_B32B_TIMESTAMP_NUM_BITS 32
+#define CFA_P70_ACT_STAT1_B32B_TIMESTAMP_NUM_BITS 32
+#define CFA_P70_ACT_STAT0_B32B_TCP_FLAGS_NUM_BITS 9
+#define CFA_P70_ACT_STAT1_B32B_TCP_FLAGS_NUM_BITS 9
+#define CFA_P70_ACT_STAT0_B32B_UNUSED_0_NUM_BITS 7
+#define CFA_P70_ACT_STAT1_B32B_UNUSED_0_NUM_BITS 7
+#define CFA_P70_ACT_STAT0_B32B_MPC15_0_NUM_BITS 16
+#define CFA_P70_ACT_STAT1_B32B_MPC15_0_NUM_BITS 16
+#define CFA_P70_ACT_STAT0_B32B_MPC37_16_NUM_BITS 22
+#define CFA_P70_ACT_STAT1_B32B_MPC37_16_NUM_BITS 22
+#define CFA_P70_ACT_STAT0_B32B_MBC_NUM_BITS 42
+#define CFA_P70_ACT_STAT1_B32B_MBC_NUM_BITS 42
+
+#define CFA_P70_CACHE_LINE_BYTES 32
+#define CFA_P70_CACHE_LINE_BITS \
+ (CFA_P70_CACHE_LINE_BYTES * BITS_PER_BYTE)
+
+/* clang-format on */
+
+#endif /* _CFA_P70_HW_H_ */
new file mode 100644
@@ -0,0 +1,1496 @@
+/****************************************************************************
+ * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * Name: cfa_p70_mpc_structs.h
+ *
+ * Description: MPC CFA command and completion structure definitions
+ *
+ * Date: 09/29/22 11:50:38
+ *
+ * Note: This file is scripted generated by ./cfa_header_gen.py.
+ * DO NOT modify this file manually !!!!
+ *
+ ****************************************************************************/
+#ifndef _CFA_P70_MPC_STRUCTS_H_
+#define _CFA_P70_MPC_STRUCTS_H_
+
+/* clang-format off */
+
+/**
+ * READ_CMD: This command reads 1-4 consecutive 32B words from the
+ * specified address within a table scope.
+ */
+struct cfa_mpc_read_cmd {
+ /*
+ * This value selects the format for the mid-path command for the CFA.
+ */
+ uint32_t opcode:8;
+ #define READ_CMD_OPCODE_READ 0
+ /* This value selects the table type to be acted upon. */
+ uint32_t table_type:4;
+ #define READ_CMD_TABLE_TYPE_ACTION 0
+ #define READ_CMD_TABLE_TYPE_EM 1
+ /* Unused field [4] */
+ uint32_t unused0:4;
+ /* Table scope to access. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused1:3;
+ /*
+ * Number of 32B units in access. If value is outside the range [1, 4],
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ uint32_t data_size:3;
+ /* Unused field [1] */
+ uint32_t unused2:1;
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ uint32_t cache_option:4;
+ /*
+ * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE):
+ */
+ uint32_t table_index:26;
+ /* Unused field [6] */
+ uint32_t unused3:6;
+ /*
+ * The 64-bit host address to which to write the DMA data returned in
+ * the completion. The data will be written to the same function as the
+ * one that owns the SQ this command is read from. DATA_SIZE determines
+ * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0,
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ uint32_t host_address_1:32;
+ uint32_t host_address_2:32;
+};
+
+/**
+ * WRITE_CMD: This command writes 1-4 consecutive 32B words to the
+ * specified address within a table scope.
+ */
+struct cfa_mpc_write_cmd {
+ /*
+ * This value selects the format for the mid-path command for the CFA.
+ */
+ uint32_t opcode:8;
+ #define WRITE_CMD_OPCODE_WRITE 1
+ /* This value selects the table type to be acted upon. */
+ uint32_t table_type:4;
+ #define WRITE_CMD_TABLE_TYPE_ACTION 0
+ #define WRITE_CMD_TABLE_TYPE_EM 1
+ /*
+ * Sets the OPTION field on the cache interface to use write-through for
+ * EM entry writes while processing EM_INSERT commands. For all other
+ * cases (inluding EM_INSERT bucket writes), the OPTION field is set by
+ * the CACHE_OPTION and CACHE_OPTION2 fields.
+ */
+ uint32_t write_through:1;
+ /* Unused field [3] */
+ uint32_t unused0:3;
+ /* Table scope to access. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused1:3;
+ /*
+ * Number of 32B units in access. If value is outside the range [1, 4],
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ uint32_t data_size:3;
+ /* Unused field [1] */
+ uint32_t unused2:1;
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ uint32_t cache_option:4;
+ /*
+ * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE):
+ */
+ uint32_t table_index:26;
+ /* Unused field [70] */
+ uint32_t unused3_1:6;
+ uint32_t unused3_2:32;
+ uint32_t unused3_3:32;
+};
+
+/**
+ * READ_CLR_CMD: This command performs a read-modify-write to the
+ * specified 32B address using a 16b mask that specifies up to 16 16b
+ * words to clear before writing the data back. It returns the 32B data
+ * word read from cache (not the value written after the clear
+ * operation).
+ */
+struct cfa_mpc_read_clr_cmd {
+ /*
+ * This value selects the format for the mid-path command for the CFA.
+ */
+ uint32_t opcode:8;
+ #define READ_CLR_CMD_OPCODE_READ_CLR 2
+ /* This value selects the table type to be acted upon. */
+ uint32_t table_type:4;
+ #define READ_CLR_CMD_TABLE_TYPE_ACTION 0
+ #define READ_CLR_CMD_TABLE_TYPE_EM 1
+ /* Unused field [4] */
+ uint32_t unused0:4;
+ /* Table scope to access. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused1:3;
+ /*
+ * This field is no longer used. The READ_CLR command always reads (and
+ * does a mask-clear) on a single cache line. This field was added for
+ * SR2 A0 to avoid an ADDR_ERR when TABLE_INDEX=0 and TABLE_TYPE=EM (see
+ * CUMULUS-17872). That issue was fixed in SR2 B0.
+ */
+ uint32_t data_size:3;
+ /* Unused field [1] */
+ uint32_t unused2:1;
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ uint32_t cache_option:4;
+ /*
+ * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE):
+ */
+ uint32_t table_index:26;
+ /* Unused field [6] */
+ uint32_t unused3:6;
+ /*
+ * The 64-bit host address to which to write the DMA data returned in
+ * the completion. The data will be written to the same function as the
+ * one that owns the SQ this command is read from. DATA_SIZE determines
+ * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0,
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ uint32_t host_address_1:32;
+ uint32_t host_address_2:32;
+ /*
+ * Specifies bits in 32B data word to clear. For x=0..15, when
+ * clear_mask[x]=1, data[x*16+15:x*16] is set to 0.
+ */
+ uint32_t clear_mask:16;
+ /* Unused field [16] */
+ uint32_t unused4:16;
+};
+
+/**
+ * INVALIDATE_CMD: This command forces an explicit evict of 1-4
+ * consecutive cache lines such that the next time the structure is used
+ * it will be re-read from its backing store location.
+ */
+struct cfa_mpc_invalidate_cmd {
+ /*
+ * This value selects the format for the mid-path command for the CFA.
+ */
+ uint32_t opcode:8;
+ #define INVALIDATE_CMD_OPCODE_INVALIDATE 5
+ /* This value selects the table type to be acted upon. */
+ uint32_t table_type:4;
+ #define INVALIDATE_CMD_TABLE_TYPE_ACTION 0
+ #define INVALIDATE_CMD_TABLE_TYPE_EM 1
+ /* Unused field [4] */
+ uint32_t unused0:4;
+ /* Table scope to access. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused1:3;
+ /*
+ * This value identifies the number of cache lines to invalidate. A
+ * FMT_ERR is reported if the value is not in the range of [1, 4].
+ */
+ uint32_t data_size:3;
+ /* Unused field [1] */
+ uint32_t unused2:1;
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ uint32_t cache_option:4;
+ /*
+ * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE):
+ */
+ uint32_t table_index:26;
+ /* Unused field [6] */
+ uint32_t unused3:6;
+};
+
+/**
+ * EM_SEARCH_CMD: This command supplies an exact match entry of 1-4 32B
+ * words to search for in the exact match table. CFA first computes the
+ * hash value of the key in the entry, and determines the static bucket
+ * address to search from the hash and the (EM_BUCKETS, EM_SIZE) for
+ * TABLE_SCOPE. It then searches that static bucket chain for an entry
+ * with a matching key (the LREC in the command entry is ignored). If a
+ * matching entry is found, CFA reports OK status in the completion.
+ * Otherwise, assuming no errors abort the search before it completes,
+ * it reports EM_MISS status.
+ */
+struct cfa_mpc_em_search_cmd {
+ /*
+ * This value selects the format for the mid-path command for the CFA.
+ */
+ uint32_t opcode:8;
+ #define EM_SEARCH_CMD_OPCODE_EM_SEARCH 8
+ /* Unused field [8] */
+ uint32_t unused0:8;
+ /* Table scope to access. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused1:3;
+ /*
+ * Number of 32B units in access. If value is outside the range [1, 4],
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ uint32_t data_size:3;
+ /* Unused field [1] */
+ uint32_t unused2:1;
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ uint32_t cache_option:4;
+ /* Unused field [96] */
+ uint32_t unused3_1:32;
+ uint32_t unused3_2:32;
+ uint32_t unused3_3:32;
+};
+
+/**
+ * EM_INSERT_CMD: This command supplies an exact match entry of 1-4 32B
+ * words to insert in the exact match table. CFA first computes the hash
+ * value of the key in the entry, and determines the static bucket
+ * address to search from the hash and the (EM_BUCKETS, EM_SIZE) for
+ * TABLE_SCOPE. It then writes the 1-4 32B words of the exact match
+ * entry starting at the TABLE_INDEX location in the command. When the
+ * entry write completes, it searches the static bucket chain for an
+ * existing entry with a key matching the key in the insert entry (the
+ * LREC does not need to match). If a matching entry is found: * If
+ * REPLACE=0, the CFA aborts the insert and returns EM_DUPLICATE status.
+ * * If REPLACE=1, the CFA overwrites the matching entry with the new
+ * entry. REPLACED_ENTRY=1 in the completion in this case to signal that
+ * an entry was replaced. The location of the entry is provided in the
+ * completion. If no match is found, CFA adds the new entry to the
+ * lowest unused entry in the tail bucket. If the current tail bucket is
+ * full, this requires adding a new bucket to the tail. Then entry is
+ * then inserted at entry number 0. TABLE_INDEX2 provides the address of
+ * the new tail bucket, if needed. If set to 0, the insert is aborted
+ * and returns EM_ABORT status instead of adding a new bucket to the
+ * tail. CHAIN_UPD in the completion indicates whether a new bucket was
+ * added (1) or not (0). For locked scopes, if the read of the static
+ * bucket gives a locked scope miss error, indicating that the address
+ * is not in the cache, the static bucket is assumed empty. In this
+ * case, TAI creates a new bucket, setting entry 0 to the new entry
+ * fields and initializing all other fields to 0. It writes this new
+ * bucket to the static bucket address, which installs it in the cache.
+ */
+struct cfa_mpc_em_insert_cmd {
+ /*
+ * This value selects the format for the mid-path command for the CFA.
+ */
+ uint32_t opcode:8;
+ #define EM_INSERT_CMD_OPCODE_EM_INSERT 9
+ /* Unused field [4] */
+ uint32_t unused0:4;
+ /*
+ * Sets the OPTION field on the cache interface to use write-through for
+ * EM entry writes while processing EM_INSERT commands. For all other
+ * cases (inluding EM_INSERT bucket writes), the OPTION field is set by
+ * the CACHE_OPTION and CACHE_OPTION2 fields.
+ */
+ uint32_t write_through:1;
+ /* Unused field [3] */
+ uint32_t unused1:3;
+ /* Table scope to access. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused2:3;
+ /*
+ * Number of 32B units in access. If value is outside the range [1, 4],
+ * CFA aborts processing and reports FMT_ERR status.
+ */
+ uint32_t data_size:3;
+ /* Unused field [1] */
+ uint32_t unused3:1;
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ uint32_t cache_option:4;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. Starting
+ * address to write exact match entry being inserted.
+ */
+ uint32_t table_index:26;
+ /* Unused field [2] */
+ uint32_t unused4:2;
+ /*
+ * Determines setting of OPTION field for all cache write requests for
+ * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support
+ * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0.
+ */
+ uint32_t cache_option2:4;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. Only used
+ * when no duplicate entry is found and the tail bucket in the chain
+ * searched has no unused entries. In this case, TABLE_INDEX2 provides
+ * the index to the 32B dynamic bucket to add to the tail of the chain
+ * (it is the new tail bucket). In this case, the CFA first writes
+ * TABLE_INDEX2 with a new bucket: * Entry 0 of the bucket sets the
+ * HASH_MSBS computed from the hash and ENTRY_PTR to TABLE_INDEX. *
+ * Entries 1-5 of the bucket set HASH_MSBS and ENTRY_PTR to 0. * CHAIN=0
+ * and CHAIN_PTR is set to CHAIN_PTR from to original tail bucket to
+ * maintain the background chaining. CFA then sets CHAIN=1 and
+ * CHAIN_PTR=TABLE_INDEX2 in the original tail bucket to link the new
+ * bucket to the chain. CHAIN_UPD=1 in the completion to signal that the
+ * new bucket at TABLE_INDEX2 was added to the tail of the chain.
+ */
+ uint32_t table_index2:26;
+ /* Unused field [5] */
+ uint32_t unused5:5;
+ /*
+ * Only used if an entry is found whose key matches the exact match
+ * entry key in the command: * REPLACE=0: The insert is aborted and
+ * EM_DUPLICATE status is returned, signaling that the insert failed.
+ * The index of the matching entry that blocked the insertion is
+ * returned in the completion. * REPLACE=1: The matching entry is
+ * replaced with that from the command (ENTRY_PTR in the bucket is
+ * overwritten with TABLE_INDEX from the command). HASH_MSBS for the
+ * entry number never changes in this case since it had to match the new
+ * entry key HASH_MSBS to match. When an entry is replaced,
+ * REPLACED_ENTRY=1 in the completion and the index of the matching
+ * entry is returned in the completion so that software can de-allocate
+ * the entry.
+ */
+ uint32_t replace:1;
+ /* Unused field [32] */
+ uint32_t unused6:32;
+};
+
+/**
+ * EM_DELETE_CMD: This command searches for an exact match entry index
+ * in the static bucket chain and deletes it if found. TABLE_INDEX give
+ * the entry index to delete and TABLE_INDEX2 gives the static bucket
+ * index. If a matching entry is found: * If the matching entry is the
+ * last valid entry in the tail bucket, its entry fields (HASH_MSBS and
+ * ENTRY_PTR) are set to 0 to delete the entry. * If the matching entry
+ * is not the last valid entry in the tail bucket, the entry fields from
+ * that last entry are moved to the matching entry, and the fields of
+ * that last entry are set to 0. * If any of the previous processing
+ * results in the tail bucket not having any valid entries, the tail
+ * bucket is the static bucket, the scope is a locked scope, and
+ * CHAIN_PTR=0, hardware evicts the static bucket from the cache and the
+ * completion signals this case with CHAIN_UPD=1. * If any of the
+ * previous processing results in the tail bucket not having any valid
+ * entries, and the tail bucket is not the static bucket, the tail
+ * bucket is removed from the chain. In this case, the penultimate
+ * bucket in the chain becomes the tail bucket. It has CHAIN set to 0 to
+ * unlink the tail bucket, and CHAIN_PTR set to that from the original
+ * tail bucket to preserve background chaining. The completion signals
+ * this case with CHAIN_UPD=1 and returns the index to the bucket
+ * removed so that software can de-allocate it. CFA returns OK status if
+ * the entry was successfully deleted. Otherwise, it returns EM_MISS
+ * status assuming there were no errors that caused processing to be
+ * aborted.
+ */
+struct cfa_mpc_em_delete_cmd {
+ /*
+ * This value selects the format for the mid-path command for the CFA.
+ */
+ uint32_t opcode:8;
+ #define EM_DELETE_CMD_OPCODE_EM_DELETE 10
+ /* Unused field [4] */
+ uint32_t unused0:4;
+ /*
+ * Sets the OPTION field on the cache interface to use write-through for
+ * EM entry writes while processing EM_INSERT commands. For all other
+ * cases (inluding EM_INSERT bucket writes), the OPTION field is set by
+ * the CACHE_OPTION and CACHE_OPTION2 fields.
+ */
+ uint32_t write_through:1;
+ /* Unused field [3] */
+ uint32_t unused1:3;
+ /* Table scope to access. */
+ uint32_t table_scope:5;
+ /* Unused field [7] */
+ uint32_t unused2:7;
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ uint32_t cache_option:4;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. Entry index
+ * to delete.
+ */
+ uint32_t table_index:26;
+ /* Unused field [2] */
+ uint32_t unused3:2;
+ /*
+ * Determines setting of OPTION field for all cache write requests for
+ * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support
+ * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0.
+ */
+ uint32_t cache_option2:4;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. Static
+ * bucket address for bucket chain.
+ */
+ uint32_t table_index2:26;
+ /* Unused field [6] */
+ uint32_t unused4:6;
+};
+
+/**
+ * EM_CHAIN_CMD: This command updates CHAIN_PTR in the tail bucket of a
+ * static bucket chain, supplying both the static bucket and the new
+ * CHAIN_PTR value. TABLE_INDEX is the new CHAIN_PTR value and
+ * TABLE_INDEX2[23:0] is the static bucket. This command provides
+ * software a means to update background chaining coherently with other
+ * bucket updates. The value of CHAIN is unaffected (stays at 0). For
+ * locked scopes, if the static bucket is the tail bucket, it is empty
+ * (all of its ENTRY_PTR values are 0), and TABLE_INDEX=0 (the CHAIN_PTR
+ * is being set to 0), instead of updating the static bucket it is
+ * evicted from the cache. In this case, CHAIN_UPD=1 in the completion.
+ */
+struct cfa_mpc_em_chain_cmd {
+ /*
+ * This value selects the format for the mid-path command for the CFA.
+ */
+ uint32_t opcode:8;
+ #define EM_CHAIN_CMD_OPCODE_EM_CHAIN 11
+ /* Unused field [4] */
+ uint32_t unused0:4;
+ /*
+ * Sets the OPTION field on the cache interface to use write-through for
+ * EM entry writes while processing EM_INSERT commands. For all other
+ * cases (inluding EM_INSERT bucket writes), the OPTION field is set by
+ * the CACHE_OPTION and CACHE_OPTION2 fields.
+ */
+ uint32_t write_through:1;
+ /* Unused field [3] */
+ uint32_t unused1:3;
+ /* Table scope to access. */
+ uint32_t table_scope:5;
+ /* Unused field [7] */
+ uint32_t unused2:7;
+ /*
+ * Determines setting of OPTION field for all cache requests while
+ * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN.
+ * For these latter commands, CACHE_OPTION sets the OPTION field for all
+ * read requests, and CACHE_OPTION2 sets it for all write requests. CFA
+ * does not support posted write requests. Therefore, for WRITE
+ * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that
+ * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set
+ * to 0.
+ */
+ uint32_t cache_option:4;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. New
+ * CHAIN_PTR to write to tail bucket.
+ */
+ uint32_t table_index:26;
+ /* Unused field [2] */
+ uint32_t unused3:2;
+ /*
+ * Determines setting of OPTION field for all cache write requests for
+ * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support
+ * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0.
+ */
+ uint32_t cache_option2:4;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. Static
+ * bucket address for bucket chain.
+ */
+ uint32_t table_index2:26;
+ /* Unused field [6] */
+ uint32_t unused4:6;
+};
+
+/**
+ * READ_CMP: When no errors, teturns 1-4 consecutive 32B words from the
+ * TABLE_INDEX within the TABLE_SCOPE specified in the command, writing
+ * them to HOST_ADDRESS from the command.
+ */
+struct cfa_mpc_read_cmp {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ uint32_t type:6;
+ #define READ_CMP_TYPE_MID_PATH_SHORT 30
+ /* Unused field [2] */
+ uint32_t unused0:2;
+ /* The command processing status. */
+ uint32_t status:4;
+ #define READ_CMP_STATUS_OK 0
+ #define READ_CMP_STATUS_UNSPRT_ERR 1
+ #define READ_CMP_STATUS_FMT_ERR 2
+ #define READ_CMP_STATUS_SCOPE_ERR 3
+ #define READ_CMP_STATUS_ADDR_ERR 4
+ #define READ_CMP_STATUS_CACHE_ERR 5
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ uint32_t mp_client:4;
+ #define READ_CMP_MP_CLIENT_TE_CFA 2
+ #define READ_CMP_MP_CLIENT_RE_CFA 3
+ /* OPCODE from the command. */
+ uint32_t opcode:8;
+ #define READ_CMP_OPCODE_READ 0
+ /*
+ * The length of the DMA that accompanies the completion in units of
+ * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates
+ * that there is no DMA that accompanies the completion.
+ */
+ uint32_t dma_length:8;
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ uint32_t opaque:32;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v:1;
+ /* Unused field [3] */
+ uint32_t unused1:3;
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ uint32_t hash_msb:12;
+ /* Unused field [4] */
+ uint32_t unused2:4;
+ /* TABLE_TYPE from the command. */
+ uint32_t table_type:4;
+ #define READ_CMP_TABLE_TYPE_ACTION 0
+ #define READ_CMP_TABLE_TYPE_EM 1
+ /* TABLE_SCOPE from the command. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused3:3;
+ /* TABLE_INDEX from the command. */
+ uint32_t table_index:26;
+ /* Unused field [6] */
+ uint32_t unused4:6;
+};
+
+/**
+ * WRITE_CMP: Returns status of the write of 1-4 consecutive 32B words
+ * starting at TABLE_INDEX in the table specified by (TABLE_TYPE,
+ * TABLE_SCOPE).
+ */
+struct cfa_mpc_write_cmp {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ uint32_t type:6;
+ #define WRITE_CMP_TYPE_MID_PATH_SHORT 30
+ /* Unused field [2] */
+ uint32_t unused0:2;
+ /* The command processing status. */
+ uint32_t status:4;
+ #define WRITE_CMP_STATUS_OK 0
+ #define WRITE_CMP_STATUS_UNSPRT_ERR 1
+ #define WRITE_CMP_STATUS_FMT_ERR 2
+ #define WRITE_CMP_STATUS_SCOPE_ERR 3
+ #define WRITE_CMP_STATUS_ADDR_ERR 4
+ #define WRITE_CMP_STATUS_CACHE_ERR 5
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ uint32_t mp_client:4;
+ #define WRITE_CMP_MP_CLIENT_TE_CFA 2
+ #define WRITE_CMP_MP_CLIENT_RE_CFA 3
+ /* OPCODE from the command. */
+ uint32_t opcode:8;
+ #define WRITE_CMP_OPCODE_WRITE 1
+ /* Unused field [8] */
+ uint32_t unused1:8;
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ uint32_t opaque:32;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v:1;
+ /* Unused field [3] */
+ uint32_t unused2:3;
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ uint32_t hash_msb:12;
+ /* Unused field [4] */
+ uint32_t unused3:4;
+ /* TABLE_TYPE from the command. */
+ uint32_t table_type:4;
+ #define WRITE_CMP_TABLE_TYPE_ACTION 0
+ #define WRITE_CMP_TABLE_TYPE_EM 1
+ /* TABLE_SCOPE from the command. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused4:3;
+ /* TABLE_INDEX from the command. */
+ uint32_t table_index:26;
+ /* Unused field [6] */
+ uint32_t unused5:6;
+};
+
+/**
+ * READ_CLR_CMP: When no errors, returns 1 32B word from TABLE_INDEX in
+ * the table specified by (TABLE_TYPE, TABLE_SCOPE). The data returned
+ * is the value prior to the clear.
+ */
+struct cfa_mpc_read_clr_cmp {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ uint32_t type:6;
+ #define READ_CLR_CMP_TYPE_MID_PATH_SHORT 30
+ /* Unused field [2] */
+ uint32_t unused0:2;
+ /* The command processing status. */
+ uint32_t status:4;
+ #define READ_CLR_CMP_STATUS_OK 0
+ #define READ_CLR_CMP_STATUS_UNSPRT_ERR 1
+ #define READ_CLR_CMP_STATUS_FMT_ERR 2
+ #define READ_CLR_CMP_STATUS_SCOPE_ERR 3
+ #define READ_CLR_CMP_STATUS_ADDR_ERR 4
+ #define READ_CLR_CMP_STATUS_CACHE_ERR 5
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ uint32_t mp_client:4;
+ #define READ_CLR_CMP_MP_CLIENT_TE_CFA 2
+ #define READ_CLR_CMP_MP_CLIENT_RE_CFA 3
+ /* OPCODE from the command. */
+ uint32_t opcode:8;
+ #define READ_CLR_CMP_OPCODE_READ_CLR 2
+ /*
+ * The length of the DMA that accompanies the completion in units of
+ * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates
+ * that there is no DMA that accompanies the completion.
+ */
+ uint32_t dma_length:8;
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ uint32_t opaque:32;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v:1;
+ /* Unused field [3] */
+ uint32_t unused1:3;
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ uint32_t hash_msb:12;
+ /* Unused field [4] */
+ uint32_t unused2:4;
+ /* TABLE_TYPE from the command. */
+ uint32_t table_type:4;
+ #define READ_CLR_CMP_TABLE_TYPE_ACTION 0
+ #define READ_CLR_CMP_TABLE_TYPE_EM 1
+ /* TABLE_SCOPE from the command. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused3:3;
+ /* TABLE_INDEX from the command. */
+ uint32_t table_index:26;
+ /* Unused field [6] */
+ uint32_t unused4:6;
+};
+
+/**
+ * INVALIDATE_CMP: Returns status for INVALIDATE commands.
+ */
+struct cfa_mpc_invalidate_cmp {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ uint32_t type:6;
+ #define INVALIDATE_CMP_TYPE_MID_PATH_SHORT 30
+ /* Unused field [2] */
+ uint32_t unused0:2;
+ /* The command processing status. */
+ uint32_t status:4;
+ #define INVALIDATE_CMP_STATUS_OK 0
+ #define INVALIDATE_CMP_STATUS_UNSPRT_ERR 1
+ #define INVALIDATE_CMP_STATUS_FMT_ERR 2
+ #define INVALIDATE_CMP_STATUS_SCOPE_ERR 3
+ #define INVALIDATE_CMP_STATUS_ADDR_ERR 4
+ #define INVALIDATE_CMP_STATUS_CACHE_ERR 5
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ uint32_t mp_client:4;
+ #define INVALIDATE_CMP_MP_CLIENT_TE_CFA 2
+ #define INVALIDATE_CMP_MP_CLIENT_RE_CFA 3
+ /* OPCODE from the command. */
+ uint32_t opcode:8;
+ #define INVALIDATE_CMP_OPCODE_INVALIDATE 5
+ /* Unused field [8] */
+ uint32_t unused1:8;
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ uint32_t opaque:32;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v:1;
+ /* Unused field [3] */
+ uint32_t unused2:3;
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ uint32_t hash_msb:12;
+ /* Unused field [4] */
+ uint32_t unused3:4;
+ /* TABLE_TYPE from the command. */
+ uint32_t table_type:4;
+ #define INVALIDATE_CMP_TABLE_TYPE_ACTION 0
+ #define INVALIDATE_CMP_TABLE_TYPE_EM 1
+ /* TABLE_SCOPE from the command. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused4:3;
+ /* TABLE_INDEX from the command. */
+ uint32_t table_index:26;
+ /* Unused field [6] */
+ uint32_t unused5:6;
+};
+
+/**
+ * EM_SEARCH_CMP: For OK status, returns the index of the matching entry
+ * found for the EM key supplied in the command. Returns EM_MISS status
+ * if no match was found.
+ */
+struct cfa_mpc_em_search_cmp {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ uint32_t type:6;
+ #define EM_SEARCH_CMP_TYPE_MID_PATH_LONG 31
+ /* Unused field [2] */
+ uint32_t unused0:2;
+ /* The command processing status. */
+ uint32_t status:4;
+ #define EM_SEARCH_CMP_STATUS_OK 0
+ #define EM_SEARCH_CMP_STATUS_UNSPRT_ERR 1
+ #define EM_SEARCH_CMP_STATUS_FMT_ERR 2
+ #define EM_SEARCH_CMP_STATUS_SCOPE_ERR 3
+ #define EM_SEARCH_CMP_STATUS_ADDR_ERR 4
+ #define EM_SEARCH_CMP_STATUS_CACHE_ERR 5
+ #define EM_SEARCH_CMP_STATUS_EM_MISS 6
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ uint32_t mp_client:4;
+ #define EM_SEARCH_CMP_MP_CLIENT_TE_CFA 2
+ #define EM_SEARCH_CMP_MP_CLIENT_RE_CFA 3
+ /* OPCODE from the command. */
+ uint32_t opcode:8;
+ #define EM_SEARCH_CMP_OPCODE_EM_SEARCH 8
+ /* Unused field [8] */
+ uint32_t unused1:8;
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ uint32_t opaque:32;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v1:1;
+ /* Unused field [3] */
+ uint32_t unused2:3;
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ uint32_t hash_msb:12;
+ /* Unused field [8] */
+ uint32_t unused3:8;
+ /* TABLE_SCOPE from the command. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused4:3;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. For OK
+ * status, gives ENTRY_PTR[25:0] of the matching entry found. Otherwise,
+ * set to 0.
+ */
+ uint32_t table_index:26;
+ /* Unused field [6] */
+ uint32_t unused5:6;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. If the hash
+ * is computed (no errors during initial processing of the command),
+ * TABLE_INDEX2[23:0] is the static bucket address determined from the
+ * hash of the exact match entry key in the command and the (EM_SIZE,
+ * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24
+ * in this case are set to 0. For any other status, it is always 0.
+ */
+ uint32_t table_index2:26;
+ /* Unused field [38] */
+ uint32_t unused6_1:6;
+ uint32_t unused6_2:32;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v2:1;
+ /* Unused field [31] */
+ uint32_t unused7:31;
+ /*
+ * BKT_NUM is the bucket number in chain of the tail bucket after
+ * finishing processing the command, except when the command stops
+ * processing before the tail bucket. NUM_ENTRIES is the number of valid
+ * entries in the BKT_NUM bucket. The following describes the cases
+ * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after
+ * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR,
+ * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. *
+ * For CACHE_ERR completion status, BKT_NUM will be set to the bucket
+ * number that was last read without error. If ERR=1 in the response to
+ * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The
+ * static bucket is number 0, BKT_NUM increments for each new bucket in
+ * the chain, and saturates at 255. Therefore, if the value is 255,
+ * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES
+ * will still be the correct value as described above for the bucket.
+ */
+ uint32_t bkt_num:8;
+ /* See BKT_NUM description. */
+ uint32_t num_entries:3;
+ /* Unused field [21] */
+ uint32_t unused8:21;
+};
+
+/**
+ * EM_INSERT_CMP: OK status indicates that the exact match entry from
+ * the command was successfully inserted. EM_DUPLICATE status indicates
+ * that the insert was aborted because an entry with the same exact
+ * match key was found and REPLACE=0 in the command. EM_ABORT status
+ * indicates that no duplicate was found, the tail bucket in the chain
+ * was full, and TABLE_INDEX2=0. No changes are made to the database in
+ * this case. TABLE_INDEX is the starting address at which to insert the
+ * exact match entry (from the command). TABLE_INDEX2 is the address at
+ * which to insert a new bucket at the tail of the static bucket chain
+ * if needed (from the command). CHAIN_UPD=1 if a new bucket was added
+ * at this address. TABLE_INDEX3 is the static bucket address for the
+ * chain, determined from hashing the exact match entry. Software needs
+ * this address and TABLE_INDEX in order to delete the entry using an
+ * EM_DELETE command. TABLE_INDEX4 is the index of an entry found that
+ * had a matching exact match key to the command entry key. If no
+ * matching entry was found, it is set to 0. There are two cases when
+ * there is a matching entry, depending on REPLACE from the command: *
+ * REPLACE=0: EM_DUPLICATE status is reported and the insert is aborted.
+ * Software can use the static bucket address (TABLE_INDEX3[23:0]) and
+ * the matching entry (TABLE_INDEX4) in an EM_DELETE command if it
+ * wishes to explicity delete the matching entry. * REPLACE=1:
+ * REPLACED_ENTRY=1 to signal that the entry at TABLE_INDEX4 was
+ * replaced by the insert entry. REPLACED_ENTRY will only be 1 if
+ * reporting OK status in this case. Software can de-allocate the entry
+ * at TABLE_INDEX4.
+ */
+struct cfa_mpc_em_insert_cmp {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ uint32_t type:6;
+ #define EM_INSERT_CMP_TYPE_MID_PATH_LONG 31
+ /* Unused field [2] */
+ uint32_t unused0:2;
+ /* The command processing status. */
+ uint32_t status:4;
+ #define EM_INSERT_CMP_STATUS_OK 0
+ #define EM_INSERT_CMP_STATUS_UNSPRT_ERR 1
+ #define EM_INSERT_CMP_STATUS_FMT_ERR 2
+ #define EM_INSERT_CMP_STATUS_SCOPE_ERR 3
+ #define EM_INSERT_CMP_STATUS_ADDR_ERR 4
+ #define EM_INSERT_CMP_STATUS_CACHE_ERR 5
+ #define EM_INSERT_CMP_STATUS_EM_DUPLICATE 7
+ #define EM_INSERT_CMP_STATUS_EM_ABORT 9
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ uint32_t mp_client:4;
+ #define EM_INSERT_CMP_MP_CLIENT_TE_CFA 2
+ #define EM_INSERT_CMP_MP_CLIENT_RE_CFA 3
+ /* OPCODE from the command. */
+ uint32_t opcode:8;
+ #define EM_INSERT_CMP_OPCODE_EM_INSERT 9
+ /* Unused field [8] */
+ uint32_t unused1:8;
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ uint32_t opaque:32;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v1:1;
+ /* Unused field [3] */
+ uint32_t unused2:3;
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ uint32_t hash_msb:12;
+ /* Unused field [8] */
+ uint32_t unused3:8;
+ /* TABLE_SCOPE from the command. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused4:3;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX
+ * from the command, which is the starting address at which to insert
+ * the exact match entry.
+ */
+ uint32_t table_index:26;
+ /* Unused field [6] */
+ uint32_t unused5:6;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2
+ * from the command, which is the index for the new tail bucket to add
+ * if needed (CHAIN_UPD=1 if it was used).
+ */
+ uint32_t table_index2:26;
+ /* Unused field [6] */
+ uint32_t unused6:6;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. If the hash
+ * is computed (no errors during initial processing of the command),
+ * TABLE_INDEX2[23:0] is the static bucket address determined from the
+ * hash of the exact match entry key in the command and the (EM_SIZE,
+ * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24
+ * in this case are set to 0. For any other status, it is always 0.
+ */
+ uint32_t table_index3:26;
+ /* Unused field [6] */
+ uint32_t unused7:6;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v2:1;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. ENTRY_PTR of
+ * matching entry found. Set to 0 if no matching entry found. If
+ * REPLACED_ENTRY=1, that indicates a matching entry was found and
+ * REPLACE=1 in the command. In this case, the matching entry was
+ * replaced by the new entry in the command and this index can therefore
+ * by de-allocated.
+ */
+ uint32_t table_index4:26;
+ /* Unused field [5] */
+ uint32_t unused8:5;
+ /*
+ * BKT_NUM is the bucket number in chain of the tail bucket after
+ * finishing processing the command, except when the command stops
+ * processing before the tail bucket. NUM_ENTRIES is the number of valid
+ * entries in the BKT_NUM bucket. The following describes the cases
+ * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after
+ * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR,
+ * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. *
+ * For CACHE_ERR completion status, BKT_NUM will be set to the bucket
+ * number that was last read without error. If ERR=1 in the response to
+ * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The
+ * static bucket is number 0, BKT_NUM increments for each new bucket in
+ * the chain, and saturates at 255. Therefore, if the value is 255,
+ * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES
+ * will still be the correct value as described above for the bucket.
+ */
+ uint32_t bkt_num:8;
+ /* See BKT_NUM description. */
+ uint32_t num_entries:3;
+ /*
+ * Specifies if the chain was updated while processing the command: Set
+ * to 1 when a new bucket is added to the tail of the static bucket
+ * chain at TABLE_INDEX2. This occurs if and only if the insert requires
+ * adding a new entry and the tail bucket is full. If set to 0,
+ * TABLE_INDEX2 was not used and is therefore still free.
+ */
+ uint32_t chain_upd:1;
+ /*
+ * Set to 1 if a matching entry was found and REPLACE=1 in command. In
+ * the case, the entry starting at TABLE_INDEX4 was replaced and can
+ * therefore be de-allocated. Otherwise, this flag is set to 0.
+ */
+ uint32_t replaced_entry:1;
+ /* Unused field [19] */
+ uint32_t unused9:19;
+};
+
+/**
+ * EM_DELETE_CMP: OK status indicates that an ENTRY_PTR matching
+ * TABLE_INDEX was found in the static bucket chain specified and was
+ * therefore deleted. EM_MISS status indicates that no match was found.
+ * TABLE_INDEX is from the command. It is the index of the entry to
+ * delete. TABLE_INDEX2 is from the command. It is the static bucket
+ * address. TABLE_INDEX3 is the index of the tail bucket of the static
+ * bucket chain prior to processing the command. TABLE_INDEX4 is the
+ * index of the tail bucket of the static bucket chain after processing
+ * the command. If CHAIN_UPD=1 and TABLE_INDEX4==TABLE_INDEX2, the
+ * static bucket was the tail bucket, it became empty after the delete,
+ * the scope is a locked scope, and CHAIN_PTR was 0. In this case, the
+ * static bucket has been evicted from the cache. Otherwise, if
+ * CHAIN_UPD=1, the original tail bucket given by TABLE_INDEX3 was
+ * removed from the chain because it went empty. It can therefore be de-
+ * allocated.
+ */
+struct cfa_mpc_em_delete_cmp {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ uint32_t type:6;
+ #define EM_DELETE_CMP_TYPE_MID_PATH_LONG 31
+ /* Unused field [2] */
+ uint32_t unused0:2;
+ /* The command processing status. */
+ uint32_t status:4;
+ #define EM_DELETE_CMP_STATUS_OK 0
+ #define EM_DELETE_CMP_STATUS_UNSPRT_ERR 1
+ #define EM_DELETE_CMP_STATUS_FMT_ERR 2
+ #define EM_DELETE_CMP_STATUS_SCOPE_ERR 3
+ #define EM_DELETE_CMP_STATUS_ADDR_ERR 4
+ #define EM_DELETE_CMP_STATUS_CACHE_ERR 5
+ #define EM_DELETE_CMP_STATUS_EM_MISS 6
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ uint32_t mp_client:4;
+ #define EM_DELETE_CMP_MP_CLIENT_TE_CFA 2
+ #define EM_DELETE_CMP_MP_CLIENT_RE_CFA 3
+ /* OPCODE from the command. */
+ uint32_t opcode:8;
+ #define EM_DELETE_CMP_OPCODE_EM_DELETE 10
+ /* Unused field [8] */
+ uint32_t unused1:8;
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ uint32_t opaque:32;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v1:1;
+ /* Unused field [3] */
+ uint32_t unused2:3;
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ uint32_t hash_msb:12;
+ /* Unused field [8] */
+ uint32_t unused3:8;
+ /* TABLE_SCOPE from the command. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused4:3;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX
+ * from the command, which is the index of the entry to delete.
+ */
+ uint32_t table_index:26;
+ /* Unused field [6] */
+ uint32_t unused5:6;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2
+ * from the command.
+ */
+ uint32_t table_index2:26;
+ /* Unused field [6] */
+ uint32_t unused6:6;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. For OK or
+ * EM_MISS status, the index of the tail bucket of the chain prior to
+ * processing the command. If CHAIN_UPD=1, the bucket was removed and
+ * this index can be de-allocated. For other status values, it is set to
+ * 0.
+ */
+ uint32_t table_index3:26;
+ /* Unused field [6] */
+ uint32_t unused7:6;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v2:1;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. For OK or
+ * EM_MISS status, the index of the tail bucket of the chain prior to
+ * after the command. If CHAIN_UPD=0 (always for EM_MISS status), it is
+ * always equal to TABLE_INDEX3 as the chain was not updated. For other
+ * status values, it is set to 0.
+ */
+ uint32_t table_index4:26;
+ /* Unused field [5] */
+ uint32_t unused8:5;
+ /*
+ * BKT_NUM is the bucket number in chain of the tail bucket after
+ * finishing processing the command, except when the command stops
+ * processing before the tail bucket. NUM_ENTRIES is the number of valid
+ * entries in the BKT_NUM bucket. The following describes the cases
+ * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after
+ * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR,
+ * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. *
+ * For CACHE_ERR completion status, BKT_NUM will be set to the bucket
+ * number that was last read without error. If ERR=1 in the response to
+ * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The
+ * static bucket is number 0, BKT_NUM increments for each new bucket in
+ * the chain, and saturates at 255. Therefore, if the value is 255,
+ * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES
+ * will still be the correct value as described above for the bucket.
+ */
+ uint32_t bkt_num:8;
+ /* See BKT_NUM description. */
+ uint32_t num_entries:3;
+ /*
+ * Specifies if the chain was updated while processing the command: Set
+ * to 1 when a bucket is removed from the static bucket chain. This
+ * occurs if after the delete, the tail bucket is a dynamic bucket and
+ * no longer has any valid entries. In this case, software should de-
+ * allocate the dynamic bucket at TABLE_INDEX3. It is also set to 1 when
+ * the static bucket is evicted, which only occurs for locked scopes.
+ * See the EM_DELETE command description for details.
+ */
+ uint32_t chain_upd:1;
+ /* Unused field [20] */
+ uint32_t unused9:20;
+};
+
+/**
+ * EM_CHAIN_CMP: OK status indicates that the CHAIN_PTR of the tail
+ * bucket was successfully updated. TABLE_INDEX is from the command. It
+ * is the value of the new CHAIN_PTR. TABLE_INDEX2 is from the command.
+ * TABLE_INDEX3 is the index of the tail bucket of the static bucket
+ * chain.
+ */
+struct cfa_mpc_em_chain_cmp {
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records **(EXCEPT
+ * no_op!!!!)** .
+ */
+ uint32_t type:6;
+ #define EM_CHAIN_CMP_TYPE_MID_PATH_LONG 31
+ /* Unused field [2] */
+ uint32_t unused0:2;
+ /* The command processing status. */
+ uint32_t status:4;
+ #define EM_CHAIN_CMP_STATUS_OK 0
+ #define EM_CHAIN_CMP_STATUS_UNSPRT_ERR 1
+ #define EM_CHAIN_CMP_STATUS_FMT_ERR 2
+ #define EM_CHAIN_CMP_STATUS_SCOPE_ERR 3
+ #define EM_CHAIN_CMP_STATUS_ADDR_ERR 4
+ #define EM_CHAIN_CMP_STATUS_CACHE_ERR 5
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ uint32_t mp_client:4;
+ #define EM_CHAIN_CMP_MP_CLIENT_TE_CFA 2
+ #define EM_CHAIN_CMP_MP_CLIENT_RE_CFA 3
+ /* OPCODE from the command. */
+ uint32_t opcode:8;
+ #define EM_CHAIN_CMP_OPCODE_EM_CHAIN 11
+ /* Unused field [8] */
+ uint32_t unused1:8;
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ uint32_t opaque:32;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v1:1;
+ /* Unused field [3] */
+ uint32_t unused2:3;
+ /*
+ * For EM_SEARCH and EM_INSERT commands without errors that abort the
+ * command processing prior to the hash computation, set to HASH[35:24]
+ * of the hash computed from the exact match entry key in the command.
+ * For all other cases, set to 0 except for the following error
+ * conditions, which carry debug information in this field as shown by
+ * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0],
+ * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present
+ * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. *
+ * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands -
+ * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} -
+ * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if
+ * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an
+ * error - TABLE_INDEX[n]=0 if the completion does not have the
+ * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0,
+ * DATA_SIZE[2:0]}
+ */
+ uint32_t hash_msb:12;
+ /* Unused field [8] */
+ uint32_t unused3:8;
+ /* TABLE_SCOPE from the command. */
+ uint32_t table_scope:5;
+ /* Unused field [3] */
+ uint32_t unused4:3;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX
+ * from the command, which is the new CHAIN_PTR for the tail bucket of
+ * the static bucket chain.
+ */
+ uint32_t table_index:26;
+ /* Unused field [6] */
+ uint32_t unused5:6;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2
+ * from the command.
+ */
+ uint32_t table_index2:26;
+ /* Unused field [6] */
+ uint32_t unused6:6;
+ /*
+ * A 32B index into the EM table identified by TABLE_SCOPE. For OK
+ * status, the index of the tail bucket of the chain. Otherwise, set to
+ * 0.
+ */
+ uint32_t table_index3:26;
+ /* Unused field [6] */
+ uint32_t unused7:6;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ uint32_t v2:1;
+ /* Unused field [31] */
+ uint32_t unused8:31;
+ /*
+ * BKT_NUM is the bucket number in chain of the tail bucket after
+ * finishing processing the command, except when the command stops
+ * processing before the tail bucket. NUM_ENTRIES is the number of valid
+ * entries in the BKT_NUM bucket. The following describes the cases
+ * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after
+ * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR,
+ * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. *
+ * For CACHE_ERR completion status, BKT_NUM will be set to the bucket
+ * number that was last read without error. If ERR=1 in the response to
+ * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The
+ * static bucket is number 0, BKT_NUM increments for each new bucket in
+ * the chain, and saturates at 255. Therefore, if the value is 255,
+ * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES
+ * will still be the correct value as described above for the bucket.
+ */
+ uint32_t bkt_num:8;
+ /* See BKT_NUM description. */
+ uint32_t num_entries:3;
+ /*
+ * Set to 1 when the scope is a locked scope, the tail bucket is the
+ * static bucket, the bucket is empty (all of its ENTRY_PTR values are
+ * 0), and TABLE_INDEX=0 in the command. In this case, the static bucket
+ * is evicted. For all other cases, it is set to 0.
+ */
+ uint32_t chain_upd:1;
+ /* Unused field [20] */
+ uint32_t unused9:20;
+};
+
+/* clang-format on */
+
+#endif /* _CFA_P70_MPC_STRUCTS_H_ */
new file mode 100644
@@ -0,0 +1,927 @@
+/****************************************************************************
+ * Copyright(c) 2021 Broadcom Corporation, all rights reserved
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * @file cfa_bld_p70_mpc.c
+ *
+ * @brief CFA phase 7.0 api implementation to build CFA Mid-path commands
+ * and Parse CFA Mid-path Command completions
+ */
+
+#define COMP_ID BLD
+
+#include <errno.h>
+#include <string.h>
+#include "sys_util.h"
+#include "cfa_trace.h"
+#include "cfa_types.h"
+#include "cfa_p70.h"
+#include "cfa_bld_p70_mpc.h"
+#include "cfa_bld_p70_mpc_defs.h"
+#include "cfa_p70_mpc_structs.h"
+
+/* CFA MPC client ids */
+#define MP_CLIENT_TE_CFA READ_CMP_MP_CLIENT_TE_CFA
+#define MP_CLIENT_RE_CFA READ_CMP_MP_CLIENT_RE_CFA
+
+/* MPC Client id check in CFA completion messages */
+#define ASSERT_CFA_MPC_CLIENT_ID(MPCID) \
+ do { \
+ if ((MPCID) != MP_CLIENT_TE_CFA && \
+ (MPCID) != MP_CLIENT_RE_CFA) { \
+ CFA_LOG_WARN( \
+ "Unexpected MPC client id in response: %d\n", \
+ (MPCID)); \
+ } \
+ } while (0)
+
+#ifdef NXT_ENV_DEBUG
+#define ASSERT_RETURN(ERRNO) CFA_LOG_ERR("Returning error: %d\n", (ERRNO))
+#else
+#define ASSERT_RETURN(ERRNO)
+#endif
+
+/**
+ * MPC header definition
+ */
+struct mpc_header {
+ uint32_t type : 6;
+ uint32_t flags : 10;
+ uint32_t len : 16;
+ uint32_t opaque;
+ uint64_t unused;
+};
+
+/*
+ * For successful completions of read and read-clear MPC CFA
+ * commands, the responses will contain this dma info structure
+ * following the cfa_mpc_read(|clr)_cmp structure and preceding
+ * the actual data read from the cache.
+ */
+struct mpc_cr_short_dma_data {
+ uint32_t dma_length : 8;
+ uint32_t unused0 : 24;
+ uint32_t dma_addr0;
+ uint32_t dma_addr1;
+};
+
+/** Add MPC header information to MPC command message */
+static int fill_mpc_header(uint8_t *cmd, uint32_t size, uint32_t opaque_val)
+{
+ struct mpc_header hdr = {
+ .opaque = opaque_val,
+ };
+
+ if (size < sizeof(struct mpc_header)) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ memcpy(cmd, &hdr, sizeof(hdr));
+
+ return 0;
+}
+
+/** Compose Table read-clear message */
+static int compose_mpc_read_clr_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len,
+ struct cfa_mpc_cache_axs_params *parms)
+{
+ struct cfa_mpc_read_clr_cmd *cmd;
+ struct cfa_mpc_cache_read_params *rd_parms = &parms->read;
+ uint32_t cmd_size =
+ sizeof(struct mpc_header) + sizeof(struct cfa_mpc_read_clr_cmd);
+
+ if (parms->data_size != 1) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (parms->tbl_type >= CFA_HW_TABLE_MAX) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (*cmd_buff_len < cmd_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ cmd = (struct cfa_mpc_read_clr_cmd *)(cmd_buff +
+ sizeof(struct mpc_header));
+
+ /* Populate CFA MPC command header */
+ memset(cmd, 0, sizeof(struct cfa_mpc_read_clr_cmd));
+ cmd->opcode = READ_CLR_CMD_OPCODE_READ_CLR;
+ cmd->table_type = parms->tbl_type;
+ cmd->table_scope = parms->tbl_scope;
+ cmd->data_size = parms->data_size;
+ cmd->table_index = parms->tbl_index;
+ cmd->host_address_1 = (uint32_t)rd_parms->host_address;
+ cmd->host_address_2 = (uint32_t)(rd_parms->host_address >> 32);
+ switch (rd_parms->mode) {
+ case CFA_MPC_RD_EVICT:
+ cmd->cache_option = CACHE_READ_CLR_OPTION_EVICT;
+ break;
+ default:
+ case CFA_MPC_RD_NORMAL:
+ cmd->cache_option = CACHE_READ_CLR_OPTION_NORMAL;
+ break;
+ }
+ cmd->clear_mask = rd_parms->clear_mask;
+ *cmd_buff_len = cmd_size;
+
+ return 0;
+}
+
+/** Compose Table read message */
+static int compose_mpc_read_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len,
+ struct cfa_mpc_cache_axs_params *parms)
+{
+ struct cfa_mpc_read_cmd *cmd;
+ struct cfa_mpc_cache_read_params *rd_parms = &parms->read;
+ uint32_t cmd_size =
+ sizeof(struct mpc_header) + sizeof(struct cfa_mpc_read_cmd);
+
+ if (parms->data_size < 1 || parms->data_size > 4) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (parms->tbl_type >= CFA_HW_TABLE_MAX) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (*cmd_buff_len < cmd_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ cmd = (struct cfa_mpc_read_cmd *)(cmd_buff + sizeof(struct mpc_header));
+
+ /* Populate CFA MPC command header */
+ memset(cmd, 0, sizeof(struct cfa_mpc_read_cmd));
+ cmd->opcode = READ_CMD_OPCODE_READ;
+ cmd->table_type = parms->tbl_type;
+ cmd->table_scope = parms->tbl_scope;
+ cmd->data_size = parms->data_size;
+ cmd->table_index = parms->tbl_index;
+ cmd->host_address_1 = (uint32_t)rd_parms->host_address;
+ cmd->host_address_2 = (uint32_t)(rd_parms->host_address >> 32);
+ switch (rd_parms->mode) {
+ case CFA_MPC_RD_EVICT:
+ cmd->cache_option = CACHE_READ_OPTION_EVICT;
+ break;
+ case CFA_MPC_RD_DEBUG_LINE:
+ cmd->cache_option = CACHE_READ_OPTION_DEBUG_LINE;
+ break;
+ case CFA_MPC_RD_DEBUG_TAG:
+ cmd->cache_option = CACHE_READ_OPTION_DEBUG_TAG;
+ break;
+ default:
+ case CFA_MPC_RD_NORMAL:
+ cmd->cache_option = CACHE_READ_OPTION_NORMAL;
+ break;
+ }
+ *cmd_buff_len = cmd_size;
+
+ return 0;
+}
+
+/** Compose Table write message */
+static int compose_mpc_write_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len,
+ struct cfa_mpc_cache_axs_params *parms)
+{
+ struct cfa_mpc_write_cmd *cmd;
+ struct cfa_mpc_cache_write_params *wr_parms = &parms->write;
+ uint32_t cmd_size = sizeof(struct mpc_header) +
+ sizeof(struct cfa_mpc_write_cmd) +
+ parms->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE;
+
+ if (parms->data_size < 1 || parms->data_size > 4) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (parms->tbl_type >= CFA_HW_TABLE_MAX) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (!parms->write.data_ptr) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (*cmd_buff_len < cmd_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ cmd = (struct cfa_mpc_write_cmd *)(cmd_buff +
+ sizeof(struct mpc_header));
+
+ /* Populate CFA MPC command header */
+ memset(cmd, 0, sizeof(struct cfa_mpc_write_cmd));
+ cmd->opcode = WRITE_CMD_OPCODE_WRITE;
+ cmd->table_type = parms->tbl_type;
+ cmd->table_scope = parms->tbl_scope;
+ cmd->data_size = parms->data_size;
+ cmd->table_index = parms->tbl_index;
+ switch (wr_parms->mode) {
+ case CFA_MPC_WR_WRITE_THRU:
+ cmd->cache_option = CACHE_WRITE_OPTION_WRITE_THRU;
+ break;
+ default:
+ case CFA_MPC_WR_WRITE_BACK:
+ cmd->cache_option = CACHE_WRITE_OPTION_WRITE_BACK;
+ break;
+ }
+
+ /* Populate CFA MPC command payload following the header */
+ memcpy(cmd + 1, wr_parms->data_ptr,
+ parms->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE);
+
+ *cmd_buff_len = cmd_size;
+
+ return 0;
+}
+
+/** Compose Invalidate message */
+static int compose_mpc_evict_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len,
+ struct cfa_mpc_cache_axs_params *parms)
+{
+ struct cfa_mpc_invalidate_cmd *cmd;
+ struct cfa_mpc_cache_evict_params *ev_parms = &parms->evict;
+ uint32_t cmd_size = sizeof(struct mpc_header) +
+ sizeof(struct cfa_mpc_invalidate_cmd);
+
+ if (parms->data_size < 1 || parms->data_size > 4) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (parms->tbl_type >= CFA_HW_TABLE_MAX) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (*cmd_buff_len < cmd_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ cmd = (struct cfa_mpc_invalidate_cmd *)(cmd_buff +
+ sizeof(struct mpc_header));
+
+ /* Populate CFA MPC command header */
+ memset(cmd, 0, sizeof(struct cfa_mpc_invalidate_cmd));
+ cmd->opcode = INVALIDATE_CMD_OPCODE_INVALIDATE;
+ cmd->table_type = parms->tbl_type;
+ cmd->table_scope = parms->tbl_scope;
+ cmd->data_size = parms->data_size;
+ cmd->table_index = parms->tbl_index;
+
+ switch (ev_parms->mode) {
+ case CFA_MPC_EV_EVICT_LINE:
+ cmd->cache_option = CACHE_EVICT_OPTION_LINE;
+ break;
+ case CFA_MPC_EV_EVICT_CLEAN_LINES:
+ cmd->cache_option = CACHE_EVICT_OPTION_CLEAN_LINES;
+ break;
+ case CFA_MPC_EV_EVICT_CLEAN_FAST_EVICT_LINES:
+ cmd->cache_option = CACHE_EVICT_OPTION_CLEAN_FAST_LINES;
+ break;
+ case CFA_MPC_EV_EVICT_CLEAN_AND_CLEAN_FAST_EVICT_LINES:
+ cmd->cache_option =
+ CACHE_EVICT_OPTION_CLEAN_AND_CLEAN_FAST_EVICT_LINES;
+ break;
+ case CFA_MPC_EV_EVICT_TABLE_SCOPE:
+ /* Not supported */
+ ASSERT_RETURN(-ENOTSUP);
+ return -ENOTSUP;
+ default:
+ case CFA_MPC_EV_EVICT_SCOPE_ADDRESS:
+ cmd->cache_option = CACHE_EVICT_OPTION_SCOPE_ADDRESS;
+ break;
+ }
+ *cmd_buff_len = cmd_size;
+
+ return 0;
+}
+
+/**
+ * Build MPC CFA Cache access command
+ *
+ * @param [in] opc MPC opcode
+ *
+ * @param [out] cmd_buff Command data buffer to write the command to
+ *
+ * @param [in/out] cmd_buff_len Pointer to command buffer size param
+ * Set by caller to indicate the input cmd_buff size.
+ * Set to the actual size of the command generated by the api.
+ *
+ * @param [in] parms Pointer to MPC cache access command parameters
+ *
+ * @return 0 on Success, negative errno on failure
+ */
+int cfa_mpc_build_cache_axs_cmd(enum cfa_mpc_opcode opc, uint8_t *cmd_buff,
+ uint32_t *cmd_buff_len,
+ struct cfa_mpc_cache_axs_params *parms)
+{
+ int rc;
+ if (!cmd_buff || !cmd_buff_len || *cmd_buff_len == 0 || !parms) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ rc = fill_mpc_header(cmd_buff, *cmd_buff_len, parms->opaque);
+ if (rc)
+ return rc;
+
+ switch (opc) {
+ case CFA_MPC_READ_CLR:
+ return compose_mpc_read_clr_msg(cmd_buff, cmd_buff_len, parms);
+ case CFA_MPC_READ:
+ return compose_mpc_read_msg(cmd_buff, cmd_buff_len, parms);
+ case CFA_MPC_WRITE:
+ return compose_mpc_write_msg(cmd_buff, cmd_buff_len, parms);
+ case CFA_MPC_INVALIDATE:
+ return compose_mpc_evict_msg(cmd_buff, cmd_buff_len, parms);
+ default:
+ ASSERT_RETURN(-ENOTSUP);
+ return -ENOTSUP;
+ }
+}
+
+/** Compose EM Search message */
+static int compose_mpc_em_search_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len,
+ struct cfa_mpc_em_op_params *parms)
+{
+ struct cfa_mpc_em_search_cmd *cmd;
+ struct cfa_mpc_em_search_params *e = &parms->search;
+ uint32_t cmd_size = sizeof(struct mpc_header) +
+ sizeof(struct cfa_mpc_em_search_cmd) +
+ e->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE;
+
+ if (e->data_size < 1 || e->data_size > 4) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (*cmd_buff_len < cmd_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (!e->em_entry) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ cmd = (struct cfa_mpc_em_search_cmd *)(cmd_buff +
+ sizeof(struct mpc_header));
+
+ /* Populate CFA MPC command header */
+ memset(cmd, 0, sizeof(struct cfa_mpc_em_search_cmd));
+ cmd->opcode = EM_SEARCH_CMD_OPCODE_EM_SEARCH;
+ cmd->table_scope = parms->tbl_scope;
+ cmd->data_size = e->data_size;
+ /* Default to normal read cache option for EM search */
+ cmd->cache_option = CACHE_READ_OPTION_NORMAL;
+
+ /* Populate CFA MPC command payload following the header */
+ memcpy(cmd + 1, e->em_entry,
+ e->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE);
+
+ *cmd_buff_len = cmd_size;
+
+ return 0;
+}
+
+/** Compose EM Insert message */
+static int compose_mpc_em_insert_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len,
+ struct cfa_mpc_em_op_params *parms)
+{
+ struct cfa_mpc_em_insert_cmd *cmd;
+ struct cfa_mpc_em_insert_params *e = &parms->insert;
+ uint32_t cmd_size = sizeof(struct mpc_header) +
+ sizeof(struct cfa_mpc_em_insert_cmd) +
+ e->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE;
+
+ if (e->data_size < 1 || e->data_size > 4) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (*cmd_buff_len < cmd_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (!e->em_entry) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ cmd = (struct cfa_mpc_em_insert_cmd *)(cmd_buff +
+ sizeof(struct mpc_header));
+
+ /* Populate CFA MPC command header */
+ memset(cmd, 0, sizeof(struct cfa_mpc_em_insert_cmd));
+ cmd->opcode = EM_INSERT_CMD_OPCODE_EM_INSERT;
+ cmd->write_through = 1;
+ cmd->table_scope = parms->tbl_scope;
+ cmd->data_size = e->data_size;
+ cmd->replace = e->replace;
+ cmd->table_index = e->entry_idx;
+ cmd->table_index2 = e->bucket_idx;
+ /* Default to normal read cache option for EM insert */
+ cmd->cache_option = CACHE_READ_OPTION_NORMAL;
+ /* Default to write through cache write option for EM insert */
+ cmd->cache_option2 = CACHE_WRITE_OPTION_WRITE_THRU;
+
+ /* Populate CFA MPC command payload following the header */
+ memcpy(cmd + 1, e->em_entry,
+ e->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE);
+
+ *cmd_buff_len = cmd_size;
+
+ return 0;
+}
+
+/** Compose EM Delete message */
+static int compose_mpc_em_delete_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len,
+ struct cfa_mpc_em_op_params *parms)
+{
+ struct cfa_mpc_em_delete_cmd *cmd;
+ struct cfa_mpc_em_delete_params *e = &parms->del;
+ uint32_t cmd_size = sizeof(struct mpc_header) +
+ sizeof(struct cfa_mpc_em_delete_cmd);
+
+ if (*cmd_buff_len < cmd_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ /* Populate CFA MPC command header */
+ cmd = (struct cfa_mpc_em_delete_cmd *)(cmd_buff +
+ sizeof(struct mpc_header));
+ memset(cmd, 0, sizeof(struct cfa_mpc_em_delete_cmd));
+ cmd->opcode = EM_DELETE_CMD_OPCODE_EM_DELETE;
+ cmd->table_scope = parms->tbl_scope;
+ cmd->table_index = e->entry_idx;
+ cmd->table_index2 = e->bucket_idx;
+ /* Default to normal read cache option for EM delete */
+ cmd->cache_option = CACHE_READ_OPTION_NORMAL;
+ /* Default to write through cache write option for EM delete */
+ cmd->cache_option2 = CACHE_WRITE_OPTION_WRITE_THRU;
+
+ *cmd_buff_len = cmd_size;
+
+ return 0;
+}
+
+/** Compose EM Chain message */
+static int compose_mpc_em_chain_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len,
+ struct cfa_mpc_em_op_params *parms)
+{
+ struct cfa_mpc_em_chain_cmd *cmd;
+ struct cfa_mpc_em_chain_params *e = &parms->chain;
+ uint32_t cmd_size =
+ sizeof(struct mpc_header) + sizeof(struct cfa_mpc_em_chain_cmd);
+
+ if (*cmd_buff_len < cmd_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ /* Populate CFA MPC command header */
+ cmd = (struct cfa_mpc_em_chain_cmd *)(cmd_buff +
+ sizeof(struct mpc_header));
+ memset(cmd, 0, sizeof(struct cfa_mpc_em_chain_cmd));
+ cmd->opcode = EM_CHAIN_CMD_OPCODE_EM_CHAIN;
+ cmd->table_scope = parms->tbl_scope;
+ cmd->table_index = e->entry_idx;
+ cmd->table_index2 = e->bucket_idx;
+ /* Default to normal read cache option for EM delete */
+ cmd->cache_option = CACHE_READ_OPTION_NORMAL;
+ /* Default to write through cache write option for EM delete */
+ cmd->cache_option2 = CACHE_WRITE_OPTION_WRITE_THRU;
+
+ *cmd_buff_len = cmd_size;
+
+ return 0;
+}
+
+/**
+ * Build MPC CFA EM operation command
+ *
+ * @param [in] opc MPC EM opcode
+ *
+ * @param [in] cmd_buff Command data buffer to write the command to
+ *
+ * @param [in/out] cmd_buff_len Pointer to command buffer size param
+ * Set by caller to indicate the input cmd_buff size.
+ * Set to the actual size of the command generated by the api.
+ *
+ * @param [in] parms Pointer to MPC cache access command parameters
+ *
+ * @return 0 on Success, negative errno on failure
+ */
+int cfa_mpc_build_em_op_cmd(enum cfa_mpc_opcode opc, uint8_t *cmd_buff,
+ uint32_t *cmd_buff_len,
+ struct cfa_mpc_em_op_params *parms)
+{
+ int rc;
+ if (!cmd_buff || !cmd_buff_len || *cmd_buff_len == 0 || !parms) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ rc = fill_mpc_header(cmd_buff, *cmd_buff_len, parms->opaque);
+ if (rc)
+ return rc;
+
+ switch (opc) {
+ case CFA_MPC_EM_SEARCH:
+ return compose_mpc_em_search_msg(cmd_buff, cmd_buff_len, parms);
+ case CFA_MPC_EM_INSERT:
+ return compose_mpc_em_insert_msg(cmd_buff, cmd_buff_len, parms);
+ case CFA_MPC_EM_DELETE:
+ return compose_mpc_em_delete_msg(cmd_buff, cmd_buff_len, parms);
+ case CFA_MPC_EM_CHAIN:
+ return compose_mpc_em_chain_msg(cmd_buff, cmd_buff_len, parms);
+ default:
+ ASSERT_RETURN(-ENOTSUP);
+ return -ENOTSUP;
+ }
+
+ return 0;
+}
+
+/** Parse MPC read clear completion */
+static int parse_mpc_read_clr_result(uint8_t *resp_buff, uint32_t resp_buff_len,
+ struct cfa_mpc_cache_axs_result *result)
+{
+ uint8_t *rd_data;
+ uint32_t resp_size, rd_size;
+ struct cfa_mpc_read_clr_cmp *cmp;
+
+ /* Minimum data size = 1 32B unit */
+ rd_size = MPC_CFA_CACHE_ACCESS_UNIT_SIZE;
+ resp_size = sizeof(struct mpc_header) +
+ sizeof(struct cfa_mpc_read_clr_cmp) +
+ sizeof(struct mpc_cr_short_dma_data) + rd_size;
+ cmp = (struct cfa_mpc_read_clr_cmp *)(resp_buff +
+ sizeof(struct mpc_header));
+
+ if (resp_buff_len < resp_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (result->data_len < rd_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (!result->rd_data) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ ASSERT_CFA_MPC_CLIENT_ID(cmp->mp_client);
+
+ result->status = cmp->status;
+ result->error_data = cmp->hash_msb;
+ result->opaque = cmp->opaque;
+
+ /* No data to copy if there was an error, return early */
+ if (cmp->status != READ_CLR_CMP_STATUS_OK)
+ return 0;
+
+ /* Copy the read data - starting at the end of the completion header including dma data */
+ rd_data = resp_buff + sizeof(struct mpc_header) +
+ sizeof(struct cfa_mpc_read_clr_cmp) +
+ sizeof(struct mpc_cr_short_dma_data);
+ memcpy(result->rd_data, rd_data, rd_size);
+
+ return 0;
+}
+
+/** Parse MPC table read completion */
+static int parse_mpc_read_result(uint8_t *resp_buff, uint32_t resp_buff_len,
+ struct cfa_mpc_cache_axs_result *result)
+{
+ uint8_t *rd_data;
+ uint32_t resp_size, rd_size;
+ struct cfa_mpc_read_cmp *cmp;
+
+ /* Minimum data size = 1 32B unit */
+ rd_size = MPC_CFA_CACHE_ACCESS_UNIT_SIZE;
+ resp_size = sizeof(struct mpc_header) +
+ sizeof(struct cfa_mpc_read_cmp) +
+ sizeof(struct mpc_cr_short_dma_data) + rd_size;
+ cmp = (struct cfa_mpc_read_cmp *)(resp_buff +
+ sizeof(struct mpc_header));
+
+ if (resp_buff_len < resp_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (result->data_len < rd_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ if (!result->rd_data) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ ASSERT_CFA_MPC_CLIENT_ID(cmp->mp_client);
+
+ result->status = cmp->status;
+ result->error_data = cmp->hash_msb;
+ result->opaque = cmp->opaque;
+
+ /* No data to copy if there was an error, return early */
+ if (cmp->status != READ_CMP_STATUS_OK)
+ return 0;
+
+ /* Copy max of 4 32B words that can fit into the return buffer */
+ rd_size = MIN(4 * MPC_CFA_CACHE_ACCESS_UNIT_SIZE, result->data_len);
+
+ /* Copy the read data - starting at the end of the completion header */
+ rd_data = resp_buff + sizeof(struct mpc_header) +
+ sizeof(struct cfa_mpc_read_cmp) +
+ sizeof(struct mpc_cr_short_dma_data);
+ memcpy(result->rd_data, rd_data, rd_size);
+
+ return 0;
+}
+
+/** Parse MPC table write completion */
+static int parse_mpc_write_result(uint8_t *resp_buff, uint32_t resp_buff_len,
+ struct cfa_mpc_cache_axs_result *result)
+{
+ uint32_t resp_size;
+ struct cfa_mpc_write_cmp *cmp;
+
+ resp_size =
+ sizeof(struct mpc_header) + sizeof(struct cfa_mpc_write_cmp);
+ cmp = (struct cfa_mpc_write_cmp *)(resp_buff +
+ sizeof(struct mpc_header));
+
+ if (resp_buff_len < resp_size) {
+ ASSERT_RETURN(-EINVAL);
+ return -EINVAL;
+ }
+
+ ASSERT_CFA_MPC_CLIENT_ID(cmp->mp_client);
+
+ result->status = cmp->status;
+ result->error_data = cmp->hash_msb;
+ result->opaque = cmp->opaque;
+ return 0;
+}
+
+/** Parse MPC table evict completion */
+static int parse_mpc_evict_result(uint8_t *resp_buff, uint32_t resp_buff_len,
+ struct cfa_mpc_cache_axs_result *result)
+{
+ uint32_t resp_size;
+ struct cfa_mpc_invalidate_cmp *cmp;
+
+ resp_size = sizeof(struct mpc_header) +
+ sizeof(struct cfa