diff mbox series

[v3,05/12] net/ice: update PTP init

Message ID 20240823095650.349785-6-soumyadeep.hore@intel.com (mailing list archive)
State Accepted
Delegated to: Bruce Richardson
Headers
Series Align ICE shared code with Base driver |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Hore, Soumyadeep Aug. 23, 2024, 9:56 a.m. UTC 
From: Norbert Zulinski <norbertx.zulinski@intel.com>

Add Bit macro to init PHY 1 for E825C devices.

Signed-off-by: Norbert Zulinski <norbertx.zulinski@intel.com>
Signed-off-by: Soumyadeep Hore <soumyadeep.hore@intel.com>
---
 drivers/net/ice/base/ice_ptp_hw.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index e574ae6d4f..e61810cbdc 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -2365,9 +2365,10 @@  static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable)
 	u32 regval = rd32(hw, PF_SB_REM_DEV_CTL);
 
 	if (enable)
-		regval |= (cgu | eth56g_dev_0 | eth56g_dev_1);
+		regval |= (BIT(eth56g_dev_1));
 	else
-		regval &= ~(cgu | eth56g_dev_0 | eth56g_dev_1);
+		regval &= ~(BIT(eth56g_dev_1));
+
 	wr32(hw, PF_SB_REM_DEV_CTL, regval);
 }
 
@@ -5691,6 +5692,7 @@  void ice_ptp_init_phy_model(struct ice_hw *hw)
 	}
 
 	ice_sb_access_ena_eth56g(hw, true);
+
 	for (phy = 0; phy < hw->num_phys; phy++)
 		if (hw->phy_addr[phy]) {
 			int err;