From patchwork Thu Aug 22 18:53:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143332 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 885404584B; Thu, 22 Aug 2024 21:49:00 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D04BD42FA9; Thu, 22 Aug 2024 21:48:27 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id 2A2D042F9D for ; Thu, 22 Aug 2024 21:48:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356106; x=1755892106; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FNkux+KL+WZ+4J/gmh58qvjXAF4Sb6bJmi83SMMQqh0=; b=QryWGIojKQxxelcW8SxgJFbvOn/W/fWOaNmSwYIVKOa3xCFFr2LNeX4H +n3BBwwQUUeug3CR4Eu4xF4V8X41TusmYNwDmukSuIi9oSSsUSatK+jfv oEuoWtPm3jQ94sHqJL9qlrne1lIyJUmT+R1xA686yfM2ona+3MaYS1xDe OW+Ty4UXNF6tdAoDa3+XNPOHRqD4auPWf1u45QbYGC2LgZAXJPsu55VLM /mMoyXA4PNsqQ6HIMqGmZjVV/U5/b0r4NT91R1VyeFivVzZS2OxATuvqm 6CJruA9Nw7H80Kbt0pXDOTEQgMNcslzpPBHZb0tpG8lSzbLi3EG9yu3gK g==; X-CSE-ConnectionGUID: 5VOExEnfR9Ss8M36nJQo0g== X-CSE-MsgGUID: uEg+NS7/RUyZsa9eUxURMQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979676" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979676" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:26 -0700 X-CSE-ConnectionGUID: KnlByoH9RCSBkeoTEoPaqQ== X-CSE-MsgGUID: BrmkAN23SVGAb4+Gr+21RA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301423" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:24 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 06/12] net/ice: address compilation errors Date: Thu, 22 Aug 2024 18:53:40 +0000 Message-ID: <20240822185346.221885-7-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Visual Studio C++ compiler does not pass 32->16 or 16->8 bits conversions because of possible loss of data. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_ptp_hw.c | 31 ++++--------------------------- 1 file changed, 4 insertions(+), 27 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index e61810cbdc..2a112fea12 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1092,7 +1092,7 @@ ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u8 phy_index, u32 reg_addr, */ static int ice_phy_port_res_address_eth56g(u8 port, enum eth56g_res_type res_type, - u16 offset, u32 *address) + u32 offset, u32 *address) { u8 phy, lane; @@ -1615,7 +1615,7 @@ ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) */ static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) { - unsigned int port; + u8 port; for (port = 0; port < hw->max_phy_port; port++) { ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, @@ -2018,21 +2018,6 @@ int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port) return ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); } -/** - * ice_calc_fixed_rx_offset_eth56g - Calculated the fixed Rx offset for a port - * @hw: pointer to HW struct - * @link_spd: The Link speed to calculate for - * - * Determine the fixed Rx latency for a given link speed. - */ -static u64 -ice_calc_fixed_rx_offset_eth56g(struct ice_hw *hw, - enum ice_ptp_link_spd link_spd) -{ - u64 fixed_offset = 0; - return fixed_offset; -} - /** * ice_phy_cfg_rx_offset_eth56g - Configure total Rx timestamp offset * @hw: pointer to the HW struct @@ -2055,16 +2040,8 @@ ice_calc_fixed_rx_offset_eth56g(struct ice_hw *hw, int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port) { int err; - u64 total_offset; - - total_offset = ice_calc_fixed_rx_offset_eth56g(hw, 0); - /* Now that the total offset has been calculated, program it to the - * PHY and indicate that the Rx offset is ready. After this, - * timestamps will be enabled. - */ - err = ice_write_64b_phy_reg_eth56g(hw, port, PHY_REG_TOTAL_RX_OFFSET_L, - total_offset); + err = ice_write_64b_phy_reg_eth56g(hw, port, PHY_REG_TOTAL_RX_OFFSET_L, 0); if (err) return err; @@ -5672,7 +5649,7 @@ void ice_ptp_unlock(struct ice_hw *hw) */ void ice_ptp_init_phy_model(struct ice_hw *hw) { - unsigned int phy; + u8 phy; for (phy = 0; phy < MAX_PHYS_PER_ICE; phy++) hw->phy_addr[phy] = 0;