[2/2] eal/riscv: add support for zicbop extension

Message ID 20240530171948.19763-3-daniel.gregory@bytedance.com (mailing list archive)
State Deferred
Delegated to: Thomas Monjalon
Headers
Series eal/riscv: implement prefetch using zicbop |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/github-robot: build fail github build: failed
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/intel-Functional success Functional PASS
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ci/iol-unit-amd64-testing fail Testing issues
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Commit Message

Daniel Gregory May 30, 2024, 5:19 p.m. UTC
  The zicbop extension adds instructions for prefetching data into cache.
Use them to implement RISCV-specific versions of the rte_prefetch* and
rte_prefetch*_write functions.

- prefetch.r indicates to hardware that the cache block will be accessed
  by a data read soon
- prefetch.w indicates to hardware that the cache block will be accessed
  by a data write soon

These instructions are emitted by __builtin_prefetch on modern versions
of Clang (17.0.1+) and GCC (13.1.0+). For earlier versions, we may not
have support for assembling Zicbop instructions, so emit the word
that encodes a 'prefetch.[rw] 0(a0)' instruction.

This new functionality is controlled by a Meson flag that is disabled by
default. Whilst it's a hint, like rte_pause(), and so has no effect if
the target doesn't support the extension, it requires the address
prefetched to be loaded into a0, which may be costly.

Signed-off-by: Daniel Gregory <daniel.gregory@bytedance.com>
Suggested-by: Punit Agrawal <punit.agrawal@bytedance.com>
---
 config/riscv/meson.build             |  6 +++
 lib/eal/riscv/include/rte_prefetch.h | 57 ++++++++++++++++++++++++++--
 2 files changed, 59 insertions(+), 4 deletions(-)
  

Comments

Daniel Gregory May 31, 2024, 8:49 a.m. UTC | #1
On Thu, May 30, 2024 at 06:19:48PM +0100, Daniel Gregory wrote:
> + * The RTE_RISCV_ZICBOP option controls whether we emit them manually for older
> + * compilers that may not have the support to assemble them.
> + */
>  static inline void rte_prefetch0(const volatile void *p)
>  {
> -	RTE_SET_USED(p);
> +#ifndef RTE_RISCV_ZICBOP
> +	/* by default __builtin_prefetch prepares for a read */
> +	__builtin_prefetch((const void *)p);

This cast causes warnings (which are treated as errors by the 0-day
Robot) due to it discarding the 'volatile' on p. 

Removing the volatile from the definition of rte_prefetch0 causes build
failures in some drivers (txgbe_rxtx.c:1809, ixgbe_rxtx.c:2174,
enic_rxtx.c:127, ...).

rte_prefetch0_write takes its argument as 'const void *' and so can use
__builtin_prefetch().
  

Patch

diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index 07d7d9da23..ecf9da1c39 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -26,6 +26,12 @@  flags_common = [
     # read from /proc/device-tree/cpus/timebase-frequency. This property is
     # guaranteed on Linux, as riscv time_init() requires it.
     ['RTE_RISCV_TIME_FREQ', 0],
+
+    # When true override the default implementation of the prefetching functions
+    # (rte_prefetch*) with a version that explicitly uses the Zicbop extension.
+    # Do not enable when using modern versions of GCC (13.1.0+) or Clang
+    # (17.0.1+). They will emit these instructions in the default implementation
+    ['RTE_RISCV_ZICBOP', false],
 ]
 
 ## SoC-specific options.
diff --git a/lib/eal/riscv/include/rte_prefetch.h b/lib/eal/riscv/include/rte_prefetch.h
index 748cf1b626..82cad526b3 100644
--- a/lib/eal/riscv/include/rte_prefetch.h
+++ b/lib/eal/riscv/include/rte_prefetch.h
@@ -14,21 +14,42 @@  extern "C" {
 
 #include <rte_compat.h>
 #include <rte_common.h>
+
+#ifdef RTE_RISCV_ZICBOP
+#define RTE_PREFETCH_WRITE_ARCH_DEFINED
+#endif
+
 #include "generic/rte_prefetch.h"
 
+/*
+ * Modern versions of GCC & Clang will emit prefetch instructions for
+ * __builtin_prefetch when the Zicbop extension is present.
+ * The RTE_RISCV_ZICBOP option controls whether we emit them manually for older
+ * compilers that may not have the support to assemble them.
+ */
 static inline void rte_prefetch0(const volatile void *p)
 {
-	RTE_SET_USED(p);
+#ifndef RTE_RISCV_ZICBOP
+	/* by default __builtin_prefetch prepares for a read */
+	__builtin_prefetch((const void *)p);
+#else
+	/* prefetch.r 0(a0) */
+	register const volatile void *a0 asm("a0") = p;
+	asm volatile (".int 0x00156013" : : "r" (a0));
+#endif
 }
 
+/*
+ * The RISC-V Zicbop extension doesn't have instructions to prefetch to only a
+ * subset of cache levels, so fallback to rte_prefetch0
+ */
 static inline void rte_prefetch1(const volatile void *p)
 {
-	RTE_SET_USED(p);
+	rte_prefetch0(p);
 }
-
 static inline void rte_prefetch2(const volatile void *p)
 {
-	RTE_SET_USED(p);
+	rte_prefetch0(p);
 }
 
 static inline void rte_prefetch_non_temporal(const volatile void *p)
@@ -44,6 +65,34 @@  rte_cldemote(const volatile void *p)
 	RTE_SET_USED(p);
 }
 
+#ifdef RTE_RISCV_ZICBOP
+__rte_experimental
+static inline void
+rte_prefetch0_write(const void *p)
+{
+	/* prefetch.w 0(a0) */
+	register const void *a0 asm("a0") = p;
+	asm volatile (".int 0x00356013" : : "r" (a0));
+}
+
+/*
+ * The RISC-V Zicbop extension doesn't have instructions to prefetch to only a
+ * subset of cache levels, so fallback to rte_prefetch0_write
+ */
+__rte_experimental
+static inline void
+rte_prefetch1_write(const void *p)
+{
+	rte_prefetch0_write(p);
+}
+__rte_experimental
+static inline void
+rte_prefetch2_write(const void *p)
+{
+	rte_prefetch0_write(p);
+}
+#endif /* RTE_RISCV_ZICBOP */
+
 #ifdef __cplusplus
 }
 #endif