From patchwork Thu May 2 20:45:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 139811 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9CAF843F6C; Thu, 2 May 2024 22:49:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 46B2D402D4; Thu, 2 May 2024 22:49:25 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by mails.dpdk.org (Postfix) with ESMTP id 0A5A1402B2 for ; Thu, 2 May 2024 22:49:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714682960; x=1746218960; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yXg4go4HUlhwOYOtp0gDsJ0aFhTZEZSSeLPRs315ASQ=; b=jfsx14YOU5bdZ/M/lwhO2p1ZbGwmzGMR3EPjFfLlimNvDiDkwaX1CHXE EZFqojeeSQQPttdEDyYDgg7CWvehEakI9Jvu93oehplXNNFr8xQK2ob0Z zXDolOXVfNM6u1UN+9/gM5XbGOQ3QCd8s8SQVDIrS9hFIPd6tVLWSTHxK fzLqORZnrJXY8CjNO9EbxumndodygXSOYcnbroc88h5dCjZ8VUCKUbtMa 5/tdJ1QUKDWax4qPTtBoSEVwEfxGK2FkPivIj/OeAwxDnjljWbyzRBiUI i4C/uNPnrf41BfpzvxCBt8lE4oPjDvP4qQPqGvkXCMutK2Q8y525rfh/B A==; X-CSE-ConnectionGUID: O+EipZmOQ4CfJDyDDYI0MA== X-CSE-MsgGUID: jWD9ICGkR/GgFObw9Lo89w== X-IronPort-AV: E=McAfee;i="6600,9927,11062"; a="21032753" X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="21032753" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 13:49:19 -0700 X-CSE-ConnectionGUID: cTs+NzytTVC9t1ELYbvd6g== X-CSE-MsgGUID: jSDTI76OR9iaQouE44axRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="27838128" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orviesa008.jf.intel.com with ESMTP; 02 May 2024 13:49:19 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v2 3/5] baseband/acc: remove ACC100 HARQ pruning Date: Thu, 2 May 2024 13:45:46 -0700 Message-Id: <20240502204548.236729-4-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240502204548.236729-1-hernan.vargas@intel.com> References: <20240502204548.236729-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org HARQ pruning is not an ACC100 feature. Removing in effect dead code. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 33 +++++---------------------- 1 file changed, 6 insertions(+), 27 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index d6b0b9400c82..f37722879c20 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1152,7 +1152,6 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; uint32_t harq_index; uint32_t l; - bool harq_prun = false; uint32_t max_hc_in; fcw->qm = op->ldpc_dec.q_m; @@ -1199,13 +1198,6 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_LLR_COMPRESSION); harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); -#ifdef ACC100_EXT_MEM - /* Limit cases when HARQ pruning is valid */ - harq_prun = ((op->ldpc_dec.harq_combined_output.offset % - ACC_HARQ_OFFSET) == 0) && - (op->ldpc_dec.harq_combined_output.offset <= UINT16_MAX - * ACC_HARQ_OFFSET); -#endif if (fcw->hcin_en > 0) { harq_in_length = op->ldpc_dec.harq_combined_input.length; if (fcw->hcin_decomp_mode > 0) @@ -1221,16 +1213,9 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, if (fcw->hcin_decomp_mode > 0) harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC100_HARQ_ALIGN_COMP); - if ((harq_layout[harq_index].offset > 0) && harq_prun) { - rte_bbdev_log_debug("HARQ IN offset unexpected for now\n"); - fcw->hcin_size0 = harq_layout[harq_index].size0; - fcw->hcin_offset = harq_layout[harq_index].offset; - fcw->hcin_size1 = harq_in_length - harq_layout[harq_index].offset; - } else { - fcw->hcin_size0 = harq_in_length; - fcw->hcin_offset = 0; - fcw->hcin_size1 = 0; - } + fcw->hcin_size0 = harq_in_length; + fcw->hcin_offset = 0; + fcw->hcin_size1 = 0; } else { fcw->hcin_size0 = 0; fcw->hcin_offset = 0; @@ -1296,15 +1281,9 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, if (fcw->hcout_comp_mode > 0) harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, ACC100_HARQ_ALIGN_COMP); - if ((k0_p > fcw->hcin_size0 + ACC_HARQ_OFFSET_THRESHOLD) && harq_prun) { - fcw->hcout_size0 = (uint16_t) fcw->hcin_size0; - fcw->hcout_offset = k0_p & 0xFFC0; - fcw->hcout_size1 = harq_out_length - fcw->hcout_offset; - } else { - fcw->hcout_size0 = harq_out_length; - fcw->hcout_size1 = 0; - fcw->hcout_offset = 0; - } + fcw->hcout_size0 = harq_out_length; + fcw->hcout_size1 = 0; + fcw->hcout_offset = 0; if (fcw->hcout_size0 == 0) { rte_bbdev_log(ERR, " Invalid FCW : HCout %d",