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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF00020E5F.mail.protection.outlook.com (10.167.249.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7452.22 via Frontend Transport; Fri, 12 Apr 2024 12:54:03 +0000 Received: from cae-Lilac-RMB.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 12 Apr 2024 07:53:51 -0500 From: Venkat Kumar Ande To: CC: , Venkat Kumar Ande Subject: [PATCH 08/24] net/axgbe: update DMA coherency values Date: Fri, 12 Apr 2024 08:52:33 -0400 Message-ID: <20240412125249.10625-8-VenkatKumar.Ande@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240412125249.10625-1-VenkatKumar.Ande@amd.com> References: <20240412125249.10625-1-VenkatKumar.Ande@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E5F:EE_|SN7PR12MB6791:EE_ X-MS-Office365-Filtering-Correlation-Id: aca88e3c-aed7-4f1f-795a-08dc5aefa199 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Apr 2024 12:54:03.4172 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aca88e3c-aed7-4f1f-795a-08dc5aefa199 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E5F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6791 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Based on the IOMMU configuration, the current cache control settings can result in possible coherency issues. The hardware team has recommended new settings for the PCI device path to eliminate the issue. Signed-off-by: Venkat Kumar Ande --- drivers/net/axgbe/axgbe_dev.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c index 3389954aa6..9b0073eea6 100644 --- a/drivers/net/axgbe/axgbe_dev.c +++ b/drivers/net/axgbe/axgbe_dev.c @@ -647,23 +647,21 @@ static void axgbe_config_dma_cache(struct axgbe_port *pdata) unsigned int arcache, awcache, arwcache; arcache = 0; - AXGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, 0x3); + AXGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, 0xf); + AXGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, 0xf); + AXGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, 0xf); AXGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache); awcache = 0; - AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, 0x3); - AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, 0x3); - AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, 0x1); - AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, 0x3); - AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, 0x1); - AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RDC, 0x3); - AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RDD, 0x1); + AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, 0xf); + AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, 0xf); + AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, 0xf); + AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RDC, 0xf); AXGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache); arwcache = 0; - AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, TDWD, 0x1); - AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, TDWC, 0x3); - AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, RDRC, 0x3); + AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, TDWC, 0xf); + AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, RDRC, 0xf); AXGMAC_IOWRITE(pdata, DMA_AXIAWRCR, arwcache); }