diff mbox series

[v6,14/14] examples/ipsec-secgw: fix port ID restriction

Message ID 20240321184721.69040-15-sivaprasad.tummala@amd.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series fix lcore ID restriction |

Checks

Context Check Description
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ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/intel-Functional success Functional PASS
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ci/iol-intel-Performance success Performance Testing PASS
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ci/iol-compile-amd64-testing success Testing PASS
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ci/iol-intel-Functional success Functional Testing PASS
ci/iol-unit-amd64-testing success Testing PASS
ci/iol-unit-arm64-testing success Testing PASS
ci/iol-compile-arm64-testing success Testing PASS
ci/iol-sample-apps-testing success Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS

Commit Message

Sivaprasad Tummala March 21, 2024, 6:47 p.m. UTC 
  Currently application supports port IDs up to 255
irrespective of RTE_MAX_ETHPORTS.

The patch fixes these constraints by allowing port
IDs up to RTE_MAX_ETHPORTS.

Fixes: d299106e8e31 ("examples/ipsec-secgw: add IPsec sample application")
Cc: sergio.gonzalez.monroy@intel.com
Cc: stable@dpdk.org

Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Ferruh Yigit <ferruh.yigit@amd.com>
---
 examples/ipsec-secgw/ipsec-secgw.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/examples/ipsec-secgw/ipsec-secgw.c b/examples/ipsec-secgw/ipsec-secgw.c
index 0fa9622626..dc7491a2b9 100644
--- a/examples/ipsec-secgw/ipsec-secgw.c
+++ b/examples/ipsec-secgw/ipsec-secgw.c
@@ -1048,7 +1048,7 @@  parse_config(const char *q_arg)
 	char *str_fld[_NUM_FLD];
 	int32_t i;
 	uint32_t size;
-	uint32_t max_fld[_NUM_FLD] = {USHRT_MAX,
+	uint32_t max_fld[_NUM_FLD] = {RTE_MAX_ETHPORTS,
 				USHRT_MAX, RTE_MAX_LCORE};
 
 	nb_lcore_params = 0;
@@ -1079,7 +1079,7 @@  parse_config(const char *q_arg)
 			return -1;
 		}
 		lcore_params_array[nb_lcore_params].port_id =
-			(uint8_t)int_fld[FLD_PORT];
+			(uint16_t)int_fld[FLD_PORT];
 		lcore_params_array[nb_lcore_params].queue_id =
 			(uint16_t)int_fld[FLD_QUEUE];
 		lcore_params_array[nb_lcore_params].lcore_id =