From patchwork Wed Mar 13 16:58:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rushil Gupta X-Patchwork-Id: 138333 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CF84F43CA0; Wed, 13 Mar 2024 17:58:53 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 56E8A410E3; Wed, 13 Mar 2024 17:58:53 +0100 (CET) Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) by mails.dpdk.org (Postfix) with ESMTP id BA52C40A84 for ; Wed, 13 Mar 2024 17:58:50 +0100 (CET) Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-60832a48684so993207b3.1 for ; Wed, 13 Mar 2024 09:58:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1710349130; x=1710953930; darn=dpdk.org; h=cc:to:from:subject:message-id:mime-version:date:from:to:cc:subject :date:message-id:reply-to; bh=csRs+72sEegmdoinpFGRSFnfUU+NBvyNSpvyfP6KdlI=; b=dL6PzhGIimTNdSFfZPevF1rePT27RZCehWLh1XbhzgX8m+UkmfPZK5fnmf3c9X+6CR MIviPiIUooqCNzk3xpRacdabWN/UGmNw/Vd15r6z6rRyyNncMNZkeA3nAYns4GEVNsGz gFRQeSn42l0myW5MS1Wjtq6uAZK+N1Zh7tLzLztGS49QtjrEMVPmt9E+ClLqW+ALkMQb 4MHw61j7GG+EDavJvrxb1RMUDztRssCuEX6AND48imZIxcj7LvY4pPMtw0AyyVPtkkGr s7zES1WAkVr54jyZ4+stmwA86JHWK2qTkyHcg36VvSz7OaRuMJEawQflV0llr3i1DPnI CO6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710349130; x=1710953930; h=cc:to:from:subject:message-id:mime-version:date:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=csRs+72sEegmdoinpFGRSFnfUU+NBvyNSpvyfP6KdlI=; b=RHtu2If7wyDs7xLfOYh+7q4my2BEE6wD0D5E0jPg+97GyCS9lZw3qVOiect2fwSw7D N9mVmoT5KSQXqT/gR75i4+vBdn9UWPJ6sL+7s78NeGOj56m4rXG1jMt4mipp5A+uqT9+ EY+Y4YF7LActlK82k0SzWq9mnOmAOO+A3sB8lbYGXUg7S0AkTJv5tn/m6psbmYgvmg/+ cEdxZE9UzxKyQcw2ViXHT9THtq9AbQ2QeWwm8SFAfFEYE60U0eev5CSG+P6rD0jBbqGP iFe89lCfoL5EMrPUHlPAoHuL0zxfaQPd8vjqi44lxgICY7hYZ6H8bEWoMR4tqlbq3MXX 6BUg== X-Gm-Message-State: AOJu0YzkJLtne+jImhJ1/B7hyMNDcjPK+mBVibxAnCp2NuQ80SWsk6a1 VNlJWRV6Jh1pW229laZi1vJA9F0Orqked2LK1GO41mv+5DOC4gPx8Wr3C+3WC96ND0totkFn1sT ukYLB8Q== X-Google-Smtp-Source: AGHT+IFl/l21oFMZWWGL8PwKBBnodJk6tmhUlvZ2e9VFdxDCoGCrIsQaSvxMygzyJvMSFvFubiWVzUjbhRG8 X-Received: from wrushilg.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:2168]) (user=rushilg job=sendgmr) by 2002:a81:4981:0:b0:60a:253d:a4d5 with SMTP id w123-20020a814981000000b0060a253da4d5mr537539ywa.8.1710349130002; Wed, 13 Mar 2024 09:58:50 -0700 (PDT) Date: Wed, 13 Mar 2024 16:58:46 +0000 Mime-Version: 1.0 X-Mailer: git-send-email 2.44.0.291.gc1ea87d7ee-goog Message-ID: <20240313165846.2409573-1-rushilg@google.com> Subject: [PATCH] drivers/net/gve: add IPv4 checksum offloading capability From: Rushil Gupta To: junfeng.guo@intel.com, jeroendb@google.com, joshwash@google.com, ferruh.yigit@amd.com Cc: dev@dpdk.org, Rushil Gupta X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Gvnic's DQO format allows offloading IPv4 checksum. Made changes to Tx and Rx path to translate DPDK flags to descriptor for offloading (and vice-versa). Add ptype adminq support to only add this flags for supported L3/L4 packet-types. Signed-off-by: Rushil Gupta Reviewed-by: Joshua Washington --- drivers/net/gve/gve_ethdev.c | 34 +++++++++++++++++++++++++++++++--- drivers/net/gve/gve_ethdev.h | 5 +++++ drivers/net/gve/gve_rx_dqo.c | 38 ++++++++++++++++++++++++++++++++++++-- drivers/net/gve/gve_tx_dqo.c | 2 +- 4 files changed, 73 insertions(+), 6 deletions(-) diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c index 3b8ec58..475745b 100644 --- a/drivers/net/gve/gve_ethdev.c +++ b/drivers/net/gve/gve_ethdev.c @@ -434,8 +434,14 @@ gve_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_TSO; - if (priv->queue_format == GVE_DQO_RDA_FORMAT) - dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TCP_LRO; + if (!gve_is_gqi(priv)) { + dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; + dev_info->rx_offload_capa |= + RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | + RTE_ETH_RX_OFFLOAD_UDP_CKSUM | + RTE_ETH_RX_OFFLOAD_TCP_CKSUM | + RTE_ETH_RX_OFFLOAD_TCP_LRO; + } dev_info->default_rxconf = (struct rte_eth_rxconf) { .rx_free_thresh = GVE_DEFAULT_RX_FREE_THRESH, @@ -938,6 +944,11 @@ gve_teardown_device_resources(struct gve_priv *priv) if (err) PMD_DRV_LOG(ERR, "Could not deconfigure device resources: err=%d", err); } + + if (!gve_is_gqi(priv)) { + rte_free(priv->ptype_lut_dqo); + priv->ptype_lut_dqo = NULL; + } gve_free_counter_array(priv); gve_free_irq_db(priv); gve_clear_device_resources_ok(priv); @@ -997,8 +1008,25 @@ gve_setup_device_resources(struct gve_priv *priv) PMD_DRV_LOG(ERR, "Could not config device resources: err=%d", err); goto free_irq_dbs; } - return 0; + if (!gve_is_gqi(priv)) { + priv->ptype_lut_dqo = rte_zmalloc("gve_ptype_lut_dqo", + sizeof(struct gve_ptype_lut), 0); + if (priv->ptype_lut_dqo == NULL) { + PMD_DRV_LOG(ERR, "Failed to alloc ptype lut."); + err = -ENOMEM; + goto free_irq_dbs; + } + err = gve_adminq_get_ptype_map_dqo(priv, priv->ptype_lut_dqo); + if (unlikely(err)) { + PMD_DRV_LOG(ERR, "Failed to get ptype map: err=%d", err); + goto free_ptype_lut; + } + } + return 0; +free_ptype_lut: + rte_free(priv->ptype_lut_dqo); + priv->ptype_lut_dqo = NULL; free_irq_dbs: gve_free_irq_db(priv); free_cnt_array: diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h index d713657..9b19fc5 100644 --- a/drivers/net/gve/gve_ethdev.h +++ b/drivers/net/gve/gve_ethdev.h @@ -36,6 +36,10 @@ RTE_MBUF_F_TX_L4_MASK | \ RTE_MBUF_F_TX_TCP_SEG) +#define GVE_TX_CKSUM_OFFLOAD_MASK_DQO ( \ + GVE_TX_CKSUM_OFFLOAD_MASK | \ + RTE_MBUF_F_TX_IP_CKSUM) + #define GVE_RTE_RSS_OFFLOAD_ALL ( \ RTE_ETH_RSS_IPV4 | \ RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ @@ -295,6 +299,7 @@ struct gve_priv { uint16_t stats_end_idx; /* end index of array of stats written by NIC */ struct gve_rss_config rss_config; + struct gve_ptype_lut *ptype_lut_dqo; }; static inline bool diff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c index 7c7a8c4..1c37c54 100644 --- a/drivers/net/gve/gve_rx_dqo.c +++ b/drivers/net/gve/gve_rx_dqo.c @@ -75,6 +75,40 @@ gve_rx_refill_dqo(struct gve_rx_queue *rxq) rxq->bufq_tail = next_avail; } +static inline uint16_t +gve_parse_csum_ol_flags(volatile struct gve_rx_compl_desc_dqo *rx_desc, + struct gve_priv *priv) { + uint64_t ol_flags = 0; + struct gve_ptype ptype = + priv->ptype_lut_dqo->ptypes[rx_desc->packet_type]; + + if (!rx_desc->l3_l4_processed) + return ol_flags; + + if (ptype.l3_type == GVE_L3_TYPE_IPV4) { + if (rx_desc->csum_ip_err) + ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD; + else + ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; + } + + if (rx_desc->csum_l4_err) { + ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD; + return ol_flags; + } + switch (ptype.l4_type) { + case GVE_L4_TYPE_TCP: + case GVE_L4_TYPE_UDP: + case GVE_L4_TYPE_ICMP: + case GVE_L4_TYPE_SCTP: + ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD; + break; + default: + break; + } + return ol_flags; +} + uint16_t gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) { @@ -125,8 +159,8 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) rxm->data_len = pkt_len; rxm->port = rxq->port_id; rxm->ol_flags = 0; - - rxm->ol_flags |= RTE_MBUF_F_RX_RSS_HASH; + rxm->ol_flags |= RTE_MBUF_F_RX_RSS_HASH | + gve_parse_csum_ol_flags(rx_desc, rxq->hw); rxm->hash.rss = rte_be_to_cpu_32(rx_desc->hash); rx_pkts[nb_rx++] = rxm; diff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c index 30a1455..a65e6aa 100644 --- a/drivers/net/gve/gve_tx_dqo.c +++ b/drivers/net/gve/gve_tx_dqo.c @@ -138,7 +138,7 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) /* fill the last descriptor with End of Packet (EOP) bit */ txd->pkt.end_of_packet = 1; - if (ol_flags & GVE_TX_CKSUM_OFFLOAD_MASK) + if (ol_flags & GVE_TX_CKSUM_OFFLOAD_MASK_DQO) txd->pkt.checksum_offload_enable = 1; txq->nb_free -= nb_used;