From patchwork Wed Mar 6 12:24:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138035 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3DA1A43C5B; Wed, 6 Mar 2024 13:27:54 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A469142EA4; Wed, 6 Mar 2024 13:25:41 +0100 (CET) Received: from smtp-fw-6002.amazon.com (smtp-fw-6002.amazon.com [52.95.49.90]) by mails.dpdk.org (Postfix) with ESMTP id 4565E42E84 for ; Wed, 6 Mar 2024 13:25:39 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1709727939; x=1741263939; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Zai/BgUaGSoqifZiR4OiBXewPTuqqcgz+ZmvIeSN9fM=; b=fVB7BCO/zY+146b0NB+bEYLepGRkky8UAVKZ9Cr3epJoe5RmktwbggtE pFucig0am09PArXxfnDhI4Inn4nIRf8bEH+6gLZXtQynBLxbNo5ghzfme 4l1fE4coOCZDaY8dUmXAGCFr8Ms3orDT4XuCtzvNxCwihcsRZSRzzj1DY Q=; X-IronPort-AV: E=Sophos;i="6.06,208,1705363200"; d="scan'208";a="391346682" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.43.8.6]) by smtp-border-fw-6002.iad6.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2024 12:25:38 +0000 Received: from EX19MTAEUB002.ant.amazon.com [10.0.10.100:53528] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.42.5:2525] with esmtp (Farcaster) id 2b432284-11e1-4a07-ae03-c8bbb5597bf2; Wed, 6 Mar 2024 12:25:37 +0000 (UTC) X-Farcaster-Flow-ID: 2b432284-11e1-4a07-ae03-c8bbb5597bf2 Received: from EX19D007EUA001.ant.amazon.com (10.252.50.133) by EX19MTAEUB002.ant.amazon.com (10.252.51.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 6 Mar 2024 12:25:36 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 6 Mar 2024 12:25:35 +0000 Received: from HFA15-CG15235BS.amazon.com (10.1.213.21) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 6 Mar 2024 12:25:34 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v3 22/33] net/ena/hal: rework Rx ring submission queue Date: Wed, 6 Mar 2024 14:24:34 +0200 Message-ID: <20240306122445.4350-23-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240306122445.4350-1-shaibran@amazon.com> References: <20240306122445.4350-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes RX ring submission queue descriptors are always located in host memory This optimization replaces the generic update tail method with a tailored method for host memory type descriptors to avoid unnecessary if statement. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/hal/ena_eth_com.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/net/ena/hal/ena_eth_com.c b/drivers/net/ena/hal/ena_eth_com.c index b9123f84c3..ebad38d15a 100644 --- a/drivers/net/ena/hal/ena_eth_com.c +++ b/drivers/net/ena/hal/ena_eth_com.c @@ -210,11 +210,8 @@ static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq) return ENA_COM_OK; } -static int ena_com_sq_update_tail(struct ena_com_io_sq *io_sq) +static int ena_com_sq_update_reqular_queue_tail(struct ena_com_io_sq *io_sq) { - if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) - return ena_com_sq_update_llq_tail(io_sq); - io_sq->tail++; /* Switch phase bit in case of wrap around */ @@ -224,6 +221,14 @@ static int ena_com_sq_update_tail(struct ena_com_io_sq *io_sq) return ENA_COM_OK; } +static int ena_com_sq_update_tail(struct ena_com_io_sq *io_sq) +{ + if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) + return ena_com_sq_update_llq_tail(io_sq); + + return ena_com_sq_update_reqular_queue_tail(io_sq); +} + static struct ena_eth_io_rx_cdesc_base * ena_com_rx_cdesc_idx_to_ptr(struct ena_com_io_cq *io_cq, u16 idx) { @@ -662,7 +667,7 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, desc->buff_addr_hi = ((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); - return ena_com_sq_update_tail(io_sq); + return ena_com_sq_update_reqular_queue_tail(io_sq); } bool ena_com_cq_empty(struct ena_com_io_cq *io_cq)