From patchwork Mon Mar 4 12:29:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 137906 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1BC1E43B9B; Mon, 4 Mar 2024 13:33:35 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AB45642E51; Mon, 4 Mar 2024 13:30:57 +0100 (CET) Received: from smtp-fw-9102.amazon.com (smtp-fw-9102.amazon.com [207.171.184.29]) by mails.dpdk.org (Postfix) with ESMTP id 800A542E3E for ; Mon, 4 Mar 2024 13:30:52 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1709555452; x=1741091452; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=JN4Cdp67AP725W6CBVT8Kd96v7Zzn8D7wLAc5SBHAVY=; b=vJYPnQKxds8UZ/O79x9nuM6hx7V19KH4xWyASE8erAsgGLhu1kY9L//D R5j/Zh40zI/p8fhyAytQQabne4rcs0HM8AFaz8P9dJz31NqyPXrAgaShE 1xBmM5TGuQxSKrE5jErJfBo2EPNGTXF8T8Ieh5uouDc0H5/OD7/M4rdJV s=; X-IronPort-AV: E=Sophos;i="6.06,203,1705363200"; d="scan'208";a="401329830" Received: from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.25.36.214]) by smtp-border-fw-9102.sea19.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2024 12:30:51 +0000 Received: from EX19MTAEUB002.ant.amazon.com [10.0.17.79:12811] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.11.111:2525] with esmtp (Farcaster) id d9013f26-9394-4ce3-9228-1228ed69b8dd; Mon, 4 Mar 2024 12:30:50 +0000 (UTC) X-Farcaster-Flow-ID: d9013f26-9394-4ce3-9228-1228ed69b8dd Received: from EX19D007EUA002.ant.amazon.com (10.252.50.68) by EX19MTAEUB002.ant.amazon.com (10.252.51.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Mon, 4 Mar 2024 12:30:50 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Mon, 4 Mar 2024 12:30:49 +0000 Received: from HFA15-CG15235BS.amazon.com (10.1.212.49) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Mon, 4 Mar 2024 12:30:48 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v2 28/33] net/ena/hal: cosmetic changes Date: Mon, 4 Mar 2024 14:29:37 +0200 Message-ID: <20240304122942.3496-29-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240304122942.3496-1-shaibran@amazon.com> References: <20240304122942.3496-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes 1. modify log prints to use correct format specifier for unsigned variables. 2. removed line breaks for lines that do not exceed maximal line length. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/hal/ena_eth_com.c | 22 +++++++++++----------- drivers/net/ena/hal/ena_plat_dpdk.h | 5 ++--- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/net/ena/hal/ena_eth_com.c b/drivers/net/ena/hal/ena_eth_com.c index ebad38d15a..87a2dbfba1 100644 --- a/drivers/net/ena/hal/ena_eth_com.c +++ b/drivers/net/ena/hal/ena_eth_com.c @@ -64,7 +64,7 @@ static int ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq, io_sq->entries_in_tx_burst_left--; ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), - "Decreasing entries_in_tx_burst_left of queue %d to %d\n", + "Decreasing entries_in_tx_burst_left of queue %u to %u\n", io_sq->qid, io_sq->entries_in_tx_burst_left); } @@ -259,7 +259,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, if (unlikely((status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT && count != 0)) { ena_trc_err(dev, - "First bit is on in descriptor #%d on q_id: %d, req_id: %u\n", + "First bit is on in descriptor #%u on q_id: %u, req_id: %u\n", count, io_cq->qid, cdesc->req_id); return ENA_COM_FAULT; } @@ -268,7 +268,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK)) && ena_com_get_cap(dev, ENA_ADMIN_CDESC_MBZ))) { ena_trc_err(dev, - "Corrupted RX descriptor #%d on q_id: %d, req_id: %u\n", + "Corrupted RX descriptor #%u on q_id: %u, req_id: %u\n", count, io_cq->qid, cdesc->req_id); return ENA_COM_FAULT; } @@ -288,7 +288,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, io_cq->cur_rx_pkt_cdesc_start_idx = head_masked; ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), - "ENA q_id: %d packets were completed. first desc idx %u descs# %d\n", + "ENA q_id: %u packets were completed. first desc idx %u descs# %u\n", io_cq->qid, *first_cdesc_idx, count); } else { io_cq->cur_rx_pkt_cdesc_count = count; @@ -394,7 +394,7 @@ static void ena_com_rx_set_flags(struct ena_com_io_cq *io_cq, ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT; ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), - "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %d frag %d cdesc_status %x\n", + "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %u frag %d cdesc_status %x\n", ena_rx_ctx->l3_proto, ena_rx_ctx->l4_proto, ena_rx_ctx->l3_csum_err, @@ -434,7 +434,7 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, if (unlikely(header_len > io_sq->tx_max_header_size)) { ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), - "Header size is too large %d max header: %d\n", + "Header size is too large %u max header: %u\n", header_len, io_sq->tx_max_header_size); return ENA_COM_INVAL; } @@ -592,12 +592,12 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, } ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), - "Fetch rx packet: queue %d completed desc: %d\n", + "Fetch rx packet: queue %u completed desc: %u\n", io_cq->qid, nb_hw_desc); if (unlikely(nb_hw_desc > ena_rx_ctx->max_bufs)) { ena_trc_err(ena_com_io_cq_to_ena_dev(io_cq), - "Too many RX cdescs (%d) > MAX(%d)\n", + "Too many RX cdescs (%u) > MAX(%u)\n", nb_hw_desc, ena_rx_ctx->max_bufs); return ENA_COM_NO_SPACE; } @@ -622,7 +622,7 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, io_sq->next_to_comp += nb_hw_desc; ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), - "[%s][QID#%d] Updating SQ head to: %d\n", __func__, + "Updating Queue %u, SQ head to: %u\n", io_sq->qid, io_sq->next_to_comp); /* Get rx flags from the last pkt */ @@ -660,8 +660,8 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, desc->req_id = req_id; ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), - "[%s] Adding single RX desc, Queue: %u, req_id: %u\n", - __func__, io_sq->qid, req_id); + "Adding single RX desc, Queue: %u, req_id: %u\n", + io_sq->qid, req_id); desc->buff_addr_lo = (u32)ena_buf->paddr; desc->buff_addr_hi = diff --git a/drivers/net/ena/hal/ena_plat_dpdk.h b/drivers/net/ena/hal/ena_plat_dpdk.h index aa8fbb0cd9..fc602971d5 100644 --- a/drivers/net/ena/hal/ena_plat_dpdk.h +++ b/drivers/net/ena/hal/ena_plat_dpdk.h @@ -40,7 +40,7 @@ typedef uint64_t dma_addr_t; #define ETIME ETIMEDOUT #endif -#define ENA_PRIU64 PRIu64 +#define ENA_PRIu64 PRIu64 #define ena_atomic32_t rte_atomic32_t #define ena_mem_handle_t const struct rte_memzone * @@ -73,8 +73,7 @@ typedef uint64_t dma_addr_t; /* Redefine memcpy with caution: rte_memcpy can be simply aliased to memcpy, so * make the redefinition only if it's safe (and beneficial) to do so. */ -#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64_MEMCPY) || \ - defined(RTE_ARCH_ARM_NEON_MEMCPY) +#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64_MEMCPY) || defined(RTE_ARCH_ARM_NEON_MEMCPY) #undef memcpy #define memcpy rte_memcpy #endif