From patchwork Mon Mar 4 12:29:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 137893 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1E6F443B9B; Mon, 4 Mar 2024 13:31:44 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E685E42DF2; Mon, 4 Mar 2024 13:30:27 +0100 (CET) Received: from smtp-fw-9106.amazon.com (smtp-fw-9106.amazon.com [207.171.188.206]) by mails.dpdk.org (Postfix) with ESMTP id 523E740EDC for ; Mon, 4 Mar 2024 13:30:24 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1709555424; x=1741091424; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=dI/+4j50ym1i6p7Y/+jdESCGnAYK60J+dlv/WbcCxD4=; b=fXQgjljmFLr77P5pG+p12bCWvAgmHhTIdl7HHqWtacPbaqSA4oLC1gci Gu3OSujRyEk7Q4A+aCTjhqceFeZLBwQAs/Hz/kKJJksw8kY7lO6UD/unS CyuKmFQCIUui4c4LAhppMyl5hi1VclEKDX5mG3EwmLu8GRa1M7M1g1kA4 0=; X-IronPort-AV: E=Sophos;i="6.06,203,1705363200"; d="scan'208";a="708475288" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.210]) by smtp-border-fw-9106.sea19.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2024 12:30:19 +0000 Received: from EX19MTAEUA001.ant.amazon.com [10.0.17.79:22351] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.23.38:2525] with esmtp (Farcaster) id 2dfec49d-dd87-493c-866f-391bc265201c; Mon, 4 Mar 2024 12:30:18 +0000 (UTC) X-Farcaster-Flow-ID: 2dfec49d-dd87-493c-866f-391bc265201c Received: from EX19D007EUB003.ant.amazon.com (10.252.51.43) by EX19MTAEUA001.ant.amazon.com (10.252.50.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Mon, 4 Mar 2024 12:30:18 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB003.ant.amazon.com (10.252.51.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Mon, 4 Mar 2024 12:30:17 +0000 Received: from HFA15-CG15235BS.amazon.com (10.1.212.49) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Mon, 4 Mar 2024 12:30:16 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v2 13/33] net/ena/hal: use correct read once on u8 field Date: Mon, 4 Mar 2024 14:29:22 +0200 Message-ID: <20240304122942.3496-14-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240304122942.3496-1-shaibran@amazon.com> References: <20240304122942.3496-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes The flags field in ena_eth_io_tx_cdesc is 8-bits long. The current macro used is READ_ONCE16. Switching to READ_ONCE8 to avoid reading extra data. Given that there's an implicit cast to u8 in the assignment, the correct value is being read, but this change makes it even more accurate. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/hal/ena_eth_com.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ena/hal/ena_eth_com.h b/drivers/net/ena/hal/ena_eth_com.h index cee4f35124..6a7c17f84f 100644 --- a/drivers/net/ena/hal/ena_eth_com.h +++ b/drivers/net/ena/hal/ena_eth_com.h @@ -219,7 +219,7 @@ static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, * expected, it mean that the device still didn't update * this completion. */ - cdesc_phase = READ_ONCE16(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK; + cdesc_phase = READ_ONCE8(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK; if (cdesc_phase != expected_phase) return ENA_COM_TRY_AGAIN;