From patchwork Sat Mar 2 09:38:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagadheeraj Rottela X-Patchwork-Id: 137795 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CA83643C30; Sat, 2 Mar 2024 10:38:55 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 44E5E42D89; Sat, 2 Mar 2024 10:38:46 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 8146142831 for ; Sat, 2 Mar 2024 10:38:44 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4227JlMc024641; Sat, 2 Mar 2024 01:38:43 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=WN8T3SKSM/f1z11uvv8c48FvOiVfNWDc6oUhbKtMrFU=; b=L7+ v3PqvDStm0u1qZE5SHcbaQh3RlXvbM3a4j8XTczvqZJ9bEzQiOFDFEdiuohoKTlc 6O8tBANIcWF1V7lMhjPGqgON0Z7um77gObOt9kh1CLcmxX4Eu/HD7V9JAcqjJhSq NAT6sk70vwnueKO07gdXi9hpkKm9oAiFlnqXB1ycpe7ipHXgNyl5SO2g34usjtb1 5PtBGRAtEhmmlydjBSxGjOixdjL8Zxl6Dv+UZ5hSQfKVp3fT78MVDxOdB7QAS6jn izSf6HK1ZlyPg6pi6ofpZ4xWuogcZ8gncw3ZLnrIVysj43+ovg3aZf+gMTsENWhy mrEmdNv3J4TSeSNjaYQ== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wkcq5bh9b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 02 Mar 2024 01:38:43 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Sat, 2 Mar 2024 01:38:42 -0800 Received: from hyd1399.caveonetworks.com.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Sat, 2 Mar 2024 01:38:40 -0800 From: Nagadheeraj Rottela To: , , CC: , Nagadheeraj Rottela Subject: [PATCH v5 2/7] drivers/compress: add Nitrox driver Date: Sat, 2 Mar 2024 15:08:08 +0530 Message-ID: <20240302093813.14922-3-rnagadheeraj@marvell.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240302093813.14922-1-rnagadheeraj@marvell.com> References: <20240302093813.14922-1-rnagadheeraj@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: QLKio3LXQ7pQ8G4gH7EU-B-xzzjfz27h X-Proofpoint-ORIG-GUID: QLKio3LXQ7pQ8G4gH7EU-B-xzzjfz27h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-02_04,2024-03-01_03,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Introduce Nitrox compressdev driver. This patch implements below operations - dev_configure - dev_close - dev_infos_get - private_xform_create - private_xform_free Signed-off-by: Nagadheeraj Rottela --- MAINTAINERS | 7 + doc/guides/compressdevs/features/nitrox.ini | 17 + doc/guides/compressdevs/index.rst | 1 + doc/guides/compressdevs/nitrox.rst | 50 +++ doc/guides/rel_notes/release_24_03.rst | 3 + drivers/common/nitrox/meson.build | 1 + drivers/common/nitrox/nitrox_device.c | 37 +- drivers/common/nitrox/nitrox_device.h | 3 + drivers/compress/meson.build | 1 + drivers/compress/nitrox/meson.build | 15 + drivers/compress/nitrox/nitrox_comp.c | 353 +++++++++++++++++++ drivers/compress/nitrox/nitrox_comp.h | 33 ++ drivers/compress/nitrox/nitrox_comp_reqmgr.h | 40 +++ 13 files changed, 556 insertions(+), 5 deletions(-) create mode 100644 doc/guides/compressdevs/features/nitrox.ini create mode 100644 doc/guides/compressdevs/nitrox.rst create mode 100644 drivers/compress/nitrox/meson.build create mode 100644 drivers/compress/nitrox/nitrox_comp.c create mode 100644 drivers/compress/nitrox/nitrox_comp.h create mode 100644 drivers/compress/nitrox/nitrox_comp_reqmgr.h diff --git a/MAINTAINERS b/MAINTAINERS index d6abebc55c..a6e2cf6eae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1215,6 +1215,13 @@ F: drivers/compress/isal/ F: doc/guides/compressdevs/isal.rst F: doc/guides/compressdevs/features/isal.ini +Marvell Nitrox +M: Nagadheeraj Rottela +F: drivers/compress/nitrox/ +F: drivers/common/nitrox/ +F: doc/guides/compressdevs/nitrox.rst +F: doc/guides/compressdevs/features/nitrox.ini + NVIDIA mlx5 M: Matan Azrad F: drivers/compress/mlx5/ diff --git a/doc/guides/compressdevs/features/nitrox.ini b/doc/guides/compressdevs/features/nitrox.ini new file mode 100644 index 0000000000..1b6a96ac6d --- /dev/null +++ b/doc/guides/compressdevs/features/nitrox.ini @@ -0,0 +1,17 @@ +; +; Refer to default.ini for the full list of available PMD features. +; +; Supported features of 'nitrox' compression driver. +; +[Features] +HW Accelerated = Y +Stateful Compression = Y +Stateful Decompression = Y +OOP SGL In SGL Out = Y +OOP SGL In LB Out = Y +OOP LB In SGL Out = Y +Deflate = Y +Adler32 = Y +Crc32 = Y +Fixed = Y +Dynamic = Y diff --git a/doc/guides/compressdevs/index.rst b/doc/guides/compressdevs/index.rst index 54a3ef4273..849f211688 100644 --- a/doc/guides/compressdevs/index.rst +++ b/doc/guides/compressdevs/index.rst @@ -12,6 +12,7 @@ Compression Device Drivers overview isal mlx5 + nitrox octeontx qat_comp zlib diff --git a/doc/guides/compressdevs/nitrox.rst b/doc/guides/compressdevs/nitrox.rst new file mode 100644 index 0000000000..840fd7241a --- /dev/null +++ b/doc/guides/compressdevs/nitrox.rst @@ -0,0 +1,50 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2024 Marvell. + +Marvell NITROX Compression Poll Mode Driver +=========================================== + +The Nitrox compression poll mode driver provides support for offloading +compression and decompression operations to the NITROX V processor. +Detailed information about the NITROX V processor can be obtained here: + +* https://www.marvell.com/security-solutions/nitrox-security-processors/nitrox-v/ + +Features +-------- + +NITROX V compression PMD has support for: + +Compression/Decompression algorithm: + +* DEFLATE + +Huffman code type: + +* FIXED +* DYNAMIC + +Window size support: + +* Min - 2 bytes +* Max - 32KB + +Checksum generation: + +* CRC32, Adler + +Limitations +----------- + +* Compressdev level 0, no compression, is not supported. + +Initialization +-------------- + +Nitrox compression PMD depends on Nitrox kernel PF driver being installed on +the platform. Nitrox PF driver is required to create VF devices which will +be used by the PMD. Each VF device can enable one compressdev PMD. + +Nitrox kernel PF driver is available as part of CNN55XX-Driver SDK. The SDK +and it's installation instructions can be obtained from: +`Marvell Customer Portal `_. diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 879bb4944c..bb91953a23 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -138,6 +138,9 @@ New Features to support TLS v1.2, TLS v1.3 and DTLS v1.2. * Added PMD API to allow raw submission of instructions to CPT. +* **Added Marvell NITROX compression PMD.** + + * Added support for DEFLATE compression and decompression. Removed Items ------------- diff --git a/drivers/common/nitrox/meson.build b/drivers/common/nitrox/meson.build index 99fadbbfc9..f3cb42f006 100644 --- a/drivers/common/nitrox/meson.build +++ b/drivers/common/nitrox/meson.build @@ -16,3 +16,4 @@ sources += files( ) includes += include_directories('../../crypto/nitrox') +includes += include_directories('../../compress/nitrox') diff --git a/drivers/common/nitrox/nitrox_device.c b/drivers/common/nitrox/nitrox_device.c index b2f638ec8a..39edc440a7 100644 --- a/drivers/common/nitrox/nitrox_device.c +++ b/drivers/common/nitrox/nitrox_device.c @@ -7,6 +7,7 @@ #include "nitrox_device.h" #include "nitrox_hal.h" #include "nitrox_sym.h" +#include "nitrox_comp.h" #define PCI_VENDOR_ID_CAVIUM 0x177d #define NITROX_V_PCI_VF_DEV_ID 0x13 @@ -67,7 +68,7 @@ nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pdev) { struct nitrox_device *ndev; - int err; + int err = -1; /* Nitrox CSR space */ if (!pdev->mem_resource[0].addr) @@ -79,12 +80,20 @@ nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, ndev_init(ndev, pdev); err = nitrox_sym_pmd_create(ndev); - if (err) { - ndev_release(ndev); - return err; - } + if (err) + goto sym_pmd_err; + + err = nitrox_comp_pmd_create(ndev); + if (err) + goto comp_pmd_err; return 0; + +comp_pmd_err: + nitrox_sym_pmd_destroy(ndev); +sym_pmd_err: + ndev_release(ndev); + return err; } static int @@ -101,6 +110,10 @@ nitrox_pci_remove(struct rte_pci_device *pdev) if (err) return err; + err = nitrox_comp_pmd_destroy(ndev); + if (err) + return err; + ndev_release(ndev); return 0; } @@ -134,5 +147,19 @@ nitrox_sym_pmd_destroy(struct nitrox_device *ndev) return 0; } +__rte_weak int +nitrox_comp_pmd_create(struct nitrox_device *ndev) +{ + RTE_SET_USED(ndev); + return 0; +} + +__rte_weak int +nitrox_comp_pmd_destroy(struct nitrox_device *ndev) +{ + RTE_SET_USED(ndev); + return 0; +} + RTE_PMD_REGISTER_PCI(nitrox, nitrox_pmd); RTE_PMD_REGISTER_PCI_TABLE(nitrox, pci_id_nitrox_map); diff --git a/drivers/common/nitrox/nitrox_device.h b/drivers/common/nitrox/nitrox_device.h index b7c7ffd772..877bccb321 100644 --- a/drivers/common/nitrox/nitrox_device.h +++ b/drivers/common/nitrox/nitrox_device.h @@ -8,13 +8,16 @@ #include struct nitrox_sym_device; +struct nitrox_comp_device; struct nitrox_device { TAILQ_ENTRY(nitrox_device) next; struct rte_pci_device *pdev; uint8_t *bar_addr; struct nitrox_sym_device *sym_dev; + struct nitrox_comp_device *comp_dev; struct rte_device rte_sym_dev; + struct rte_device rte_comp_dev; uint16_t nr_queues; }; diff --git a/drivers/compress/meson.build b/drivers/compress/meson.build index abe043ab94..b91195b27d 100644 --- a/drivers/compress/meson.build +++ b/drivers/compress/meson.build @@ -8,6 +8,7 @@ endif drivers = [ 'isal', 'mlx5', + 'nitrox', 'octeontx', 'zlib', ] diff --git a/drivers/compress/nitrox/meson.build b/drivers/compress/nitrox/meson.build new file mode 100644 index 0000000000..f137303689 --- /dev/null +++ b/drivers/compress/nitrox/meson.build @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2024 Marvell. + +if not is_linux + build = false + reason = 'only supported on Linux' +endif + +deps += ['common_nitrox', 'bus_pci', 'compressdev'] + +sources += files( + 'nitrox_comp.c', +) + +includes += include_directories('../../common/nitrox') diff --git a/drivers/compress/nitrox/nitrox_comp.c b/drivers/compress/nitrox/nitrox_comp.c new file mode 100644 index 0000000000..e97a686fbf --- /dev/null +++ b/drivers/compress/nitrox/nitrox_comp.c @@ -0,0 +1,353 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2024 Marvell. + */ + +#include +#include +#include + +#include "nitrox_comp.h" +#include "nitrox_device.h" +#include "nitrox_logs.h" +#include "nitrox_comp_reqmgr.h" + +static const char nitrox_comp_drv_name[] = RTE_STR(COMPRESSDEV_NAME_NITROX_PMD); +static const struct rte_driver nitrox_rte_comp_drv = { + .name = nitrox_comp_drv_name, + .alias = nitrox_comp_drv_name +}; + +static const struct rte_compressdev_capabilities + nitrox_comp_pmd_capabilities[] = { + { .algo = RTE_COMP_ALGO_DEFLATE, + .comp_feature_flags = RTE_COMP_FF_HUFFMAN_FIXED | + RTE_COMP_FF_HUFFMAN_DYNAMIC | + RTE_COMP_FF_CRC32_CHECKSUM | + RTE_COMP_FF_ADLER32_CHECKSUM | + RTE_COMP_FF_SHAREABLE_PRIV_XFORM | + RTE_COMP_FF_OOP_SGL_IN_SGL_OUT | + RTE_COMP_FF_OOP_SGL_IN_LB_OUT | + RTE_COMP_FF_OOP_LB_IN_SGL_OUT, + .window_size = { + .min = NITROX_COMP_WINDOW_SIZE_MIN, + .max = NITROX_COMP_WINDOW_SIZE_MAX, + .increment = 1 + }, + }, + RTE_COMP_END_OF_CAPABILITIES_LIST() +}; + +static int nitrox_comp_dev_configure(struct rte_compressdev *dev, + struct rte_compressdev_config *config) +{ + struct nitrox_comp_device *comp_dev = dev->data->dev_private; + struct nitrox_device *ndev = comp_dev->ndev; + uint32_t xform_cnt; + char name[RTE_MEMPOOL_NAMESIZE]; + + if (config->nb_queue_pairs > ndev->nr_queues) { + NITROX_LOG(ERR, "Invalid queue pairs, max supported %d\n", + ndev->nr_queues); + return -EINVAL; + } + + xform_cnt = config->max_nb_priv_xforms + config->max_nb_streams; + if (unlikely(xform_cnt == 0)) { + NITROX_LOG(ERR, "Invalid configuration with 0 xforms\n"); + return -EINVAL; + } + + snprintf(name, sizeof(name), "%s_xform", dev->data->name); + comp_dev->xform_pool = rte_mempool_create(name, + xform_cnt, sizeof(struct nitrox_comp_xform), + 0, 0, NULL, NULL, NULL, NULL, + config->socket_id, 0); + if (comp_dev->xform_pool == NULL) { + NITROX_LOG(ERR, "Failed to create xform pool, err %d\n", + rte_errno); + return -rte_errno; + } + + return 0; +} + +static int nitrox_comp_dev_start(struct rte_compressdev *dev) +{ + RTE_SET_USED(dev); + return 0; +} + +static void nitrox_comp_dev_stop(struct rte_compressdev *dev) +{ + RTE_SET_USED(dev); +} + +static int nitrox_comp_dev_close(struct rte_compressdev *dev) +{ + struct nitrox_comp_device *comp_dev = dev->data->dev_private; + + rte_mempool_free(comp_dev->xform_pool); + comp_dev->xform_pool = NULL; + return 0; +} + +static void nitrox_comp_stats_get(struct rte_compressdev *dev, + struct rte_compressdev_stats *stats) +{ + RTE_SET_USED(dev); + RTE_SET_USED(stats); +} + +static void nitrox_comp_stats_reset(struct rte_compressdev *dev) +{ + RTE_SET_USED(dev); +} + +static void nitrox_comp_dev_info_get(struct rte_compressdev *dev, + struct rte_compressdev_info *info) +{ + struct nitrox_comp_device *comp_dev = dev->data->dev_private; + struct nitrox_device *ndev = comp_dev->ndev; + + if (!info) + return; + + info->max_nb_queue_pairs = ndev->nr_queues; + info->feature_flags = dev->feature_flags; + info->capabilities = nitrox_comp_pmd_capabilities; +} + +static int nitrox_comp_queue_pair_setup(struct rte_compressdev *dev, + uint16_t qp_id, + uint32_t max_inflight_ops, int socket_id) +{ + RTE_SET_USED(dev); + RTE_SET_USED(qp_id); + RTE_SET_USED(max_inflight_ops); + RTE_SET_USED(socket_id); + return -1; +} + +static int nitrox_comp_queue_pair_release(struct rte_compressdev *dev, + uint16_t qp_id) +{ + RTE_SET_USED(dev); + RTE_SET_USED(qp_id); + return 0; +} + +static int nitrox_comp_private_xform_create(struct rte_compressdev *dev, + const struct rte_comp_xform *xform, + void **private_xform) +{ + struct nitrox_comp_device *comp_dev = dev->data->dev_private; + struct nitrox_comp_xform *nxform; + enum rte_comp_checksum_type chksum_type; + int ret; + + if (unlikely(comp_dev->xform_pool == NULL)) { + NITROX_LOG(ERR, "private xform pool not yet created\n"); + return -EINVAL; + } + + if (rte_mempool_get(comp_dev->xform_pool, private_xform)) { + NITROX_LOG(ERR, "Failed to get from private xform pool\n"); + return -ENOMEM; + } + + nxform = (struct nitrox_comp_xform *)*private_xform; + memset(nxform, 0, sizeof(*nxform)); + if (xform->type == RTE_COMP_COMPRESS) { + enum rte_comp_huffman algo; + int level; + + nxform->op = NITROX_COMP_OP_COMPRESS; + if (xform->compress.algo != RTE_COMP_ALGO_DEFLATE) { + NITROX_LOG(ERR, "Only deflate is supported\n"); + ret = -ENOTSUP; + goto err_exit; + } + + algo = xform->compress.deflate.huffman; + if (algo == RTE_COMP_HUFFMAN_DEFAULT) + nxform->algo = NITROX_COMP_ALGO_DEFLATE_DEFAULT; + else if (algo == RTE_COMP_HUFFMAN_FIXED) + nxform->algo = NITROX_COMP_ALGO_DEFLATE_FIXEDHUFF; + else if (algo == RTE_COMP_HUFFMAN_DYNAMIC) + nxform->algo = NITROX_COMP_ALGO_DEFLATE_DYNHUFF; + else { + NITROX_LOG(ERR, "Invalid deflate algorithm %d\n", algo); + ret = -EINVAL; + goto err_exit; + } + + level = xform->compress.level; + if (level == RTE_COMP_LEVEL_PMD_DEFAULT) { + nxform->level = NITROX_COMP_LEVEL_MEDIUM; + } else if (level >= NITROX_COMP_LEVEL_LOWEST_START && + level <= NITROX_COMP_LEVEL_LOWEST_END) { + nxform->level = NITROX_COMP_LEVEL_LOWEST; + } else if (level >= NITROX_COMP_LEVEL_LOWER_START && + level <= NITROX_COMP_LEVEL_LOWER_END) { + nxform->level = NITROX_COMP_LEVEL_LOWER; + } else if (level >= NITROX_COMP_LEVEL_MEDIUM_START && + level <= NITROX_COMP_LEVEL_MEDIUM_END) { + nxform->level = NITROX_COMP_LEVEL_MEDIUM; + } else if (level >= NITROX_COMP_LEVEL_BEST_START && + level <= NITROX_COMP_LEVEL_BEST_END) { + nxform->level = NITROX_COMP_LEVEL_BEST; + } else { + NITROX_LOG(ERR, "Unsupported compression level %d\n", + xform->compress.level); + ret = -ENOTSUP; + goto err_exit; + } + + chksum_type = xform->compress.chksum; + } else if (xform->type == RTE_COMP_DECOMPRESS) { + nxform->op = NITROX_COMP_OP_DECOMPRESS; + if (xform->decompress.algo != RTE_COMP_ALGO_DEFLATE) { + NITROX_LOG(ERR, "Only deflate is supported\n"); + ret = -ENOTSUP; + goto err_exit; + } + + nxform->algo = NITROX_COMP_ALGO_DEFLATE_DEFAULT; + nxform->level = NITROX_COMP_LEVEL_BEST; + chksum_type = xform->decompress.chksum; + } else { + ret = -EINVAL; + goto err_exit; + } + + if (chksum_type == RTE_COMP_CHECKSUM_NONE) + nxform->chksum_type = NITROX_CHKSUM_TYPE_NONE; + else if (chksum_type == RTE_COMP_CHECKSUM_CRC32) + nxform->chksum_type = NITROX_CHKSUM_TYPE_CRC32; + else if (chksum_type == RTE_COMP_CHECKSUM_ADLER32) + nxform->chksum_type = NITROX_CHKSUM_TYPE_ADLER32; + else { + NITROX_LOG(ERR, "Unsupported checksum type %d\n", + chksum_type); + ret = -ENOTSUP; + goto err_exit; + } + + return 0; +err_exit: + memset(nxform, 0, sizeof(*nxform)); + rte_mempool_put(comp_dev->xform_pool, nxform); + return ret; +} + +static int nitrox_comp_private_xform_free(struct rte_compressdev *dev, + void *private_xform) +{ + struct nitrox_comp_xform *nxform = private_xform; + struct rte_mempool *mp = rte_mempool_from_obj(nxform); + + RTE_SET_USED(dev); + if (unlikely(nxform == NULL)) + return -EINVAL; + + memset(nxform, 0, sizeof(*nxform)); + mp = rte_mempool_from_obj(nxform); + rte_mempool_put(mp, nxform); + return 0; +} + +static uint16_t nitrox_comp_dev_enq_burst(void *qp, + struct rte_comp_op **ops, + uint16_t nb_ops) +{ + RTE_SET_USED(qp); + RTE_SET_USED(ops); + RTE_SET_USED(nb_ops); + return 0; +} + +static uint16_t nitrox_comp_dev_deq_burst(void *qp, + struct rte_comp_op **ops, + uint16_t nb_ops) +{ + RTE_SET_USED(qp); + RTE_SET_USED(ops); + RTE_SET_USED(nb_ops); + return 0; +} + +static struct rte_compressdev_ops nitrox_compressdev_ops = { + .dev_configure = nitrox_comp_dev_configure, + .dev_start = nitrox_comp_dev_start, + .dev_stop = nitrox_comp_dev_stop, + .dev_close = nitrox_comp_dev_close, + + .stats_get = nitrox_comp_stats_get, + .stats_reset = nitrox_comp_stats_reset, + + .dev_infos_get = nitrox_comp_dev_info_get, + + .queue_pair_setup = nitrox_comp_queue_pair_setup, + .queue_pair_release = nitrox_comp_queue_pair_release, + + .private_xform_create = nitrox_comp_private_xform_create, + .private_xform_free = nitrox_comp_private_xform_free, + .stream_create = NULL, + .stream_free = NULL +}; + +int +nitrox_comp_pmd_create(struct nitrox_device *ndev) +{ + char name[RTE_COMPRESSDEV_NAME_MAX_LEN]; + struct rte_compressdev_pmd_init_params init_params = { + .name = "", + .socket_id = ndev->pdev->device.numa_node, + }; + struct rte_compressdev *cdev; + + rte_pci_device_name(&ndev->pdev->addr, name, sizeof(name)); + snprintf(name + strlen(name), + RTE_COMPRESSDEV_NAME_MAX_LEN - strlen(name), + "_n5comp"); + ndev->rte_comp_dev.driver = &nitrox_rte_comp_drv; + ndev->rte_comp_dev.numa_node = ndev->pdev->device.numa_node; + ndev->rte_comp_dev.devargs = NULL; + cdev = rte_compressdev_pmd_create(name, + &ndev->rte_comp_dev, + sizeof(struct nitrox_comp_device), + &init_params); + if (!cdev) { + NITROX_LOG(ERR, "Cryptodev '%s' creation failed\n", name); + return -ENODEV; + } + + cdev->dev_ops = &nitrox_compressdev_ops; + cdev->enqueue_burst = nitrox_comp_dev_enq_burst; + cdev->dequeue_burst = nitrox_comp_dev_deq_burst; + cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; + + ndev->comp_dev = cdev->data->dev_private; + ndev->comp_dev->cdev = cdev; + ndev->comp_dev->ndev = ndev; + ndev->comp_dev->xform_pool = NULL; + NITROX_LOG(DEBUG, "Created compressdev '%s', dev_id %d\n", + cdev->data->name, cdev->data->dev_id); + return 0; +} + +int +nitrox_comp_pmd_destroy(struct nitrox_device *ndev) +{ + int err; + + if (ndev->comp_dev == NULL) + return 0; + + err = rte_compressdev_pmd_destroy(ndev->comp_dev->cdev); + if (err) + return err; + + ndev->comp_dev = NULL; + return 0; +} diff --git a/drivers/compress/nitrox/nitrox_comp.h b/drivers/compress/nitrox/nitrox_comp.h new file mode 100644 index 0000000000..90e1931b05 --- /dev/null +++ b/drivers/compress/nitrox/nitrox_comp.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2024 Marvell. + */ + +#ifndef _NITROX_COMP_H_ +#define _NITROX_COMP_H_ + +#define COMPRESSDEV_NAME_NITROX_PMD compress_nitrox +#define NITROX_DECOMP_CTX_SIZE 2048 +#define NITROX_CONSTANTS_MAX_SEARCH_DEPTH 31744 +#define NITROX_COMP_WINDOW_SIZE_MIN 1 +#define NITROX_COMP_WINDOW_SIZE_MAX 15 +#define NITROX_COMP_LEVEL_LOWEST_START 1 +#define NITROX_COMP_LEVEL_LOWEST_END 2 +#define NITROX_COMP_LEVEL_LOWER_START 3 +#define NITROX_COMP_LEVEL_LOWER_END 4 +#define NITROX_COMP_LEVEL_MEDIUM_START 5 +#define NITROX_COMP_LEVEL_MEDIUM_END 6 +#define NITROX_COMP_LEVEL_BEST_START 7 +#define NITROX_COMP_LEVEL_BEST_END 9 + +struct nitrox_comp_device { + struct rte_compressdev *cdev; + struct nitrox_device *ndev; + struct rte_mempool *xform_pool; +}; + +struct nitrox_device; + +int nitrox_comp_pmd_create(struct nitrox_device *ndev); +int nitrox_comp_pmd_destroy(struct nitrox_device *ndev); + +#endif /* _NITROX_COMP_H_ */ diff --git a/drivers/compress/nitrox/nitrox_comp_reqmgr.h b/drivers/compress/nitrox/nitrox_comp_reqmgr.h new file mode 100644 index 0000000000..14f35a1e5b --- /dev/null +++ b/drivers/compress/nitrox/nitrox_comp_reqmgr.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2024 Marvell. + */ + +#ifndef _NITROX_COMP_REQMGR_H_ +#define _NITROX_COMP_REQMGR_H_ + +enum nitrox_comp_op { + NITROX_COMP_OP_DECOMPRESS, + NITROX_COMP_OP_COMPRESS, +}; + +enum nitrox_comp_algo { + NITROX_COMP_ALGO_DEFLATE_DEFAULT, + NITROX_COMP_ALGO_DEFLATE_DYNHUFF, + NITROX_COMP_ALGO_DEFLATE_FIXEDHUFF, + NITROX_COMP_ALGO_LZS, +}; + +enum nitrox_comp_level { + NITROX_COMP_LEVEL_BEST, + NITROX_COMP_LEVEL_MEDIUM, + NITROX_COMP_LEVEL_LOWER, + NITROX_COMP_LEVEL_LOWEST, +}; + +enum nitrox_chksum_type { + NITROX_CHKSUM_TYPE_CRC32, + NITROX_CHKSUM_TYPE_ADLER32, + NITROX_CHKSUM_TYPE_NONE, +}; + +struct nitrox_comp_xform { + enum nitrox_comp_op op; + enum nitrox_comp_algo algo; + enum nitrox_comp_level level; + enum nitrox_chksum_type chksum_type; +}; + +#endif /* _NITROX_COMP_REQMGR_H_ */