From patchwork Fri Mar 1 17:32:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Prakash Shukla X-Patchwork-Id: 137764 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4DF8E43C12; Fri, 1 Mar 2024 18:32:33 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3EC554334B; Fri, 1 Mar 2024 18:32:33 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 28D2B41611 for ; Fri, 1 Mar 2024 18:32:32 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4219mvnQ013986 for ; Fri, 1 Mar 2024 09:32:31 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=CWiJQbMuui1nDS8KzbpwkqqOBJ6afmBmxzLy0Mewotw=; b=PAX muKmMJCV1lBKzHdVnlVY8YglYsw9ePQkito/fGMwT7vLFDohngOtjukfycsW+/AZ ftjaxdeLilKykZucUABQm8dzEkEvTACZzysBnuyBlD9D7YiISyePWFdiLe2+aMqO 20QhxqRILyOrYam/x7kTeGqShgTaIL99LxfmzXSB7c1oyAH14td+MwMIz1sYy724 eYp4CAiKzSdSxw7UVXxWAiH/c8JYNce9E1nETHixIlisCXOzEL0nSIL2ab+kBGqe AbiYU5e4WWiQrY6gtVruuH0rwlqoK7cUZ7PJqENF8h0O7cJKDylyX435tS4DVxHK 0xt4sDRrgS1wYXGlHog== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wkcq59dnw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 01 Mar 2024 09:32:31 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 1 Mar 2024 09:32:30 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 1 Mar 2024 09:32:29 -0800 Received: from cavium-OptiPlex-5090-BM14.. (unknown [10.28.36.157]) by maili.marvell.com (Postfix) with ESMTP id B33BC3F71A8; Fri, 1 Mar 2024 09:32:26 -0800 (PST) From: Amit Prakash Shukla To: Pavan Nikhilesh , Shijith Thotton CC: , , , , , , Amit Prakash Shukla Subject: [PATCH v4 3/3] event/cnxk: support DMA event functions Date: Fri, 1 Mar 2024 23:02:02 +0530 Message-ID: <20240301173202.2782112-3-amitprakashs@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301173202.2782112-1-amitprakashs@marvell.com> References: <20240226094334.3657250-1-amitprakashs@marvell.com> <20240301173202.2782112-1-amitprakashs@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 6Tpq0wqrKvOqIFCXvBjRYdPV26GgjIXX X-Proofpoint-ORIG-GUID: 6Tpq0wqrKvOqIFCXvBjRYdPV26GgjIXX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-01_19,2024-03-01_02,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added support of dma driver callback assignment to eventdev enqueue and dequeue. The change also defines dma adapter capabilities function. Depends-on: series-30612 ("lib/dmadev: get DMA device using device ID") Signed-off-by: Amit Prakash Shukla --- v4: - Fixed compilation error. - Updated release notes. v3: - Rebased and fixed compilation error. v2: - Added dual workslot enqueue support. - Fixed compilation error. doc/guides/rel_notes/release_24_03.rst | 4 + drivers/event/cnxk/cn10k_eventdev.c | 70 +++++++++++++++++ drivers/event/cnxk/cn10k_worker.h | 3 + drivers/event/cnxk/cn9k_eventdev.c | 67 ++++++++++++++++ drivers/event/cnxk/cn9k_worker.h | 2 + drivers/event/cnxk/cnxk_eventdev.h | 3 + drivers/event/cnxk/cnxk_eventdev_adptr.c | 97 ++++++++++++++++++++++++ drivers/event/cnxk/meson.build | 1 - 8 files changed, 246 insertions(+), 1 deletion(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 39899244f6..13ffa32f3d 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -146,6 +146,10 @@ New Features * Added support for DMA event enqueue and dequeue. * Added support for dual workslot DMA event enqueue. +* **Updated Marvell cnxk eventdev driver.** + + * Added support for DMA driver callback assignment to eventdev enqueue and dequeue. + Removed Items ------------- diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 221f419055..18f3b402c9 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -8,6 +8,9 @@ #include "cn10k_cryptodev_ops.h" #include "cnxk_eventdev.h" #include "cnxk_worker.h" +#include "cnxk_dma_event_dp.h" + +#include #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \ deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)] @@ -477,6 +480,8 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev) else event_dev->ca_enqueue = cn10k_cpt_sg_ver1_crypto_adapter_enqueue; + event_dev->dma_enqueue = cn10k_dma_adapter_enqueue; + if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue, sso_hws_tx_adptr_enq_seg); else @@ -1020,6 +1025,67 @@ cn10k_crypto_adapter_vec_limits(const struct rte_eventdev *event_dev, return 0; } +static int +cn10k_dma_adapter_caps_get(const struct rte_eventdev *event_dev, + const int16_t dma_dev_id, uint32_t *caps) +{ + struct rte_dma_dev *dma_dev; + + RTE_SET_USED(event_dev); + + dma_dev = rte_dma_pmd_get_dev_by_id(dma_dev_id); + if (dma_dev == NULL) + return -EINVAL; + + CNXK_VALID_DEV_OR_ERR_RET(dma_dev->device, "cnxk_dmadev_pci_driver", EINVAL); + + *caps = RTE_EVENT_DMA_ADAPTER_CAP_INTERNAL_PORT_OP_FWD; + + return 0; +} + +static int +cn10k_dma_adapter_vchan_add(const struct rte_eventdev *event_dev, + const int16_t dma_dev_id, uint16_t vchan_id, + const struct rte_event *event) +{ + struct rte_dma_dev *dma_dev; + int ret; + + RTE_SET_USED(event); + dma_dev = rte_dma_pmd_get_dev_by_id(dma_dev_id); + if (dma_dev == NULL) + return -EINVAL; + + CNXK_VALID_DEV_OR_ERR_RET(dma_dev->device, "cnxk_dmadev_pci_driver", EINVAL); + + cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); + + ret = cnxk_dma_adapter_vchan_add(event_dev, dma_dev_id, vchan_id); + cn10k_sso_set_priv_mem(event_dev, NULL); + + return ret; +} + +static int +cn10k_dma_adapter_vchan_del(const struct rte_eventdev *event_dev, + const int16_t dma_dev_id, uint16_t vchan_id) +{ + struct rte_dma_dev *dma_dev; + + RTE_SET_USED(event_dev); + + dma_dev = rte_dma_pmd_get_dev_by_id(dma_dev_id); + if (dma_dev == NULL) + return -EINVAL; + + CNXK_VALID_DEV_OR_ERR_RET(dma_dev->device, "cnxk_dmadev_pci_driver", EINVAL); + + return cnxk_dma_adapter_vchan_del(dma_dev_id, vchan_id); +} + + + static struct eventdev_ops cn10k_sso_dev_ops = { .dev_infos_get = cn10k_sso_info_get, .dev_configure = cn10k_sso_dev_configure, @@ -1061,6 +1127,10 @@ static struct eventdev_ops cn10k_sso_dev_ops = { .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del, .crypto_adapter_vector_limits_get = cn10k_crypto_adapter_vec_limits, + .dma_adapter_caps_get = cn10k_dma_adapter_caps_get, + .dma_adapter_vchan_add = cn10k_dma_adapter_vchan_add, + .dma_adapter_vchan_del = cn10k_dma_adapter_vchan_del, + .xstats_get = cnxk_sso_xstats_get, .xstats_reset = cnxk_sso_xstats_reset, .xstats_get_names = cnxk_sso_xstats_get_names, diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index 8aa916fa12..0036495d98 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -7,6 +7,7 @@ #include #include "cn10k_cryptodev_event_dp.h" +#include "cnxk_dma_event_dp.h" #include "cn10k_rx.h" #include "cnxk_worker.h" #include "cn10k_eventdev.h" @@ -236,6 +237,8 @@ cn10k_sso_hws_post_process(struct cn10k_sso_hws *ws, uint64_t *u64, /* Mark vector mempool object as get */ RTE_MEMPOOL_CHECK_COOKIES(rte_mempool_from_obj((void *)u64[1]), (void **)&u64[1], 1, 1); + } else if (CNXK_EVENT_TYPE_FROM_TAG(u64[0]) == RTE_EVENT_TYPE_DMADEV) { + u64[1] = cnxk_dma_adapter_dequeue(u64[1]); } } diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 00a87b3bcd..3cd6f448f0 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -6,6 +6,8 @@ #include "cnxk_eventdev.h" #include "cnxk_worker.h" +#include + #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id) #define CN9K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \ @@ -513,6 +515,8 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev) sso_hws_dual_tx_adptr_enq); } + event_dev->dma_enqueue = cn9k_dma_adapter_enqueue; + event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue; rte_mb(); #else @@ -1020,6 +1024,65 @@ cn9k_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, cn9k_sso_set_priv_mem); } +static int +cn9k_dma_adapter_caps_get(const struct rte_eventdev *event_dev, + const int16_t dma_dev_id, uint32_t *caps) +{ + struct rte_dma_dev *dma_dev; + RTE_SET_USED(event_dev); + + dma_dev = rte_dma_pmd_get_dev_by_id(dma_dev_id); + if (dma_dev == NULL) + return -EINVAL; + + CNXK_VALID_DEV_OR_ERR_RET(dma_dev->device, "cnxk_dmadev_pci_driver", EINVAL); + + *caps = RTE_EVENT_DMA_ADAPTER_CAP_INTERNAL_PORT_OP_FWD; + + return 0; +} + +static int +cn9k_dma_adapter_vchan_add(const struct rte_eventdev *event_dev, + const int16_t dma_dev_id, uint16_t vchan_id, + const struct rte_event *event) +{ + struct rte_dma_dev *dma_dev; + int ret; + + RTE_SET_USED(event); + + dma_dev = rte_dma_pmd_get_dev_by_id(dma_dev_id); + if (dma_dev == NULL) + return -EINVAL; + + CNXK_VALID_DEV_OR_ERR_RET(dma_dev->device, "cnxk_dmadev_pci_driver", EINVAL); + + cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); + + ret = cnxk_dma_adapter_vchan_add(event_dev, dma_dev_id, vchan_id); + cn9k_sso_set_priv_mem(event_dev, NULL); + + return ret; +} + +static int +cn9k_dma_adapter_vchan_del(const struct rte_eventdev *event_dev, + const int16_t dma_dev_id, uint16_t vchan_id) +{ + struct rte_dma_dev *dma_dev; + + RTE_SET_USED(event_dev); + + dma_dev = rte_dma_pmd_get_dev_by_id(dma_dev_id); + if (dma_dev == NULL) + return -EINVAL; + + CNXK_VALID_DEV_OR_ERR_RET(dma_dev->device, "cnxk_dmadev_pci_driver", EINVAL); + + return cnxk_dma_adapter_vchan_del(dma_dev_id, vchan_id); +} + static struct eventdev_ops cn9k_sso_dev_ops = { .dev_infos_get = cn9k_sso_info_get, .dev_configure = cn9k_sso_dev_configure, @@ -1058,6 +1121,10 @@ static struct eventdev_ops cn9k_sso_dev_ops = { .crypto_adapter_queue_pair_add = cn9k_crypto_adapter_qp_add, .crypto_adapter_queue_pair_del = cn9k_crypto_adapter_qp_del, + .dma_adapter_caps_get = cn9k_dma_adapter_caps_get, + .dma_adapter_vchan_add = cn9k_dma_adapter_vchan_add, + .dma_adapter_vchan_del = cn9k_dma_adapter_vchan_del, + .xstats_get = cnxk_sso_xstats_get, .xstats_reset = cnxk_sso_xstats_reset, .xstats_get_names = cnxk_sso_xstats_get_names, diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index 0cd8c45e9a..e8863e42fc 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -206,6 +206,8 @@ cn9k_sso_hws_post_process(uint64_t *u64, uint64_t mbuf, const uint32_t flags, if (flags & NIX_RX_OFFLOAD_TSTAMP_F) cn9k_sso_process_tstamp(u64[1], mbuf, tstamp[port]); u64[1] = mbuf; + } else if (CNXK_EVENT_TYPE_FROM_TAG(u64[0]) == RTE_EVENT_TYPE_DMADEV) { + u64[1] = cnxk_dma_adapter_dequeue(u64[1]); } } diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index d42d1afa1a..fa99dede85 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -284,4 +284,7 @@ int cnxk_crypto_adapter_qp_add(const struct rte_eventdev *event_dev, const struct rte_event_crypto_adapter_queue_conf *conf); int cnxk_crypto_adapter_qp_del(const struct rte_cryptodev *cdev, int32_t queue_pair_id); +int cnxk_dma_adapter_vchan_add(const struct rte_eventdev *event_dev, + const int16_t dma_dev_id, uint16_t vchan_id); +int cnxk_dma_adapter_vchan_del(const int16_t dma_dev_id, uint16_t vchan_id); #endif /* __CNXK_EVENTDEV_H__ */ diff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c index 92aea92389..a2a59b16c9 100644 --- a/drivers/event/cnxk/cnxk_eventdev_adptr.c +++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c @@ -5,6 +5,7 @@ #include "cnxk_cryptodev_ops.h" #include "cnxk_ethdev.h" #include "cnxk_eventdev.h" +#include "cnxk_dmadev.h" void cnxk_sso_updt_xae_cnt(struct cnxk_sso_evdev *dev, void *data, @@ -737,3 +738,99 @@ cnxk_crypto_adapter_qp_del(const struct rte_cryptodev *cdev, return 0; } + +static int +dma_adapter_vchan_setup(const int16_t dma_dev_id, struct cnxk_dpi_conf *vchan, + uint16_t vchan_id) +{ + char name[RTE_MEMPOOL_NAMESIZE]; + uint32_t cache_size, nb_req; + unsigned int req_size; + + snprintf(name, RTE_MEMPOOL_NAMESIZE, "cnxk_dma_req_%u:%u", dma_dev_id, vchan_id); + req_size = sizeof(struct cnxk_dpi_compl_s); + + nb_req = vchan->c_desc.max_cnt; + cache_size = 16; + nb_req += (cache_size * rte_lcore_count()); + + vchan->adapter_info.req_mp = rte_mempool_create(name, nb_req, req_size, cache_size, 0, + NULL, NULL, NULL, NULL, rte_socket_id(), 0); + if (vchan->adapter_info.req_mp == NULL) + return -ENOMEM; + + vchan->adapter_info.enabled = true; + + return 0; +} + +int +cnxk_dma_adapter_vchan_add(const struct rte_eventdev *event_dev, + const int16_t dma_dev_id, uint16_t vchan_id) +{ + struct cnxk_sso_evdev *sso_evdev = cnxk_sso_pmd_priv(event_dev); + uint32_t adptr_xae_cnt = 0; + struct cnxk_dpi_vf_s *dpivf; + struct cnxk_dpi_conf *vchan; + int ret; + + dpivf = rte_dma_fp_objs[dma_dev_id].dev_private; + if ((int16_t)vchan_id == -1) { + uint16_t vchan_id; + + for (vchan_id = 0; vchan_id < dpivf->num_vchans; vchan_id++) { + vchan = &dpivf->conf[vchan_id]; + ret = dma_adapter_vchan_setup(dma_dev_id, vchan, vchan_id); + if (ret) { + cnxk_dma_adapter_vchan_del(dma_dev_id, -1); + return ret; + } + adptr_xae_cnt += vchan->adapter_info.req_mp->size; + } + } else { + vchan = &dpivf->conf[vchan_id]; + ret = dma_adapter_vchan_setup(dma_dev_id, vchan, vchan_id); + if (ret) + return ret; + adptr_xae_cnt = vchan->adapter_info.req_mp->size; + } + + /* Update dma adapter XAE count */ + sso_evdev->adptr_xae_cnt += adptr_xae_cnt; + cnxk_sso_xae_reconfigure((struct rte_eventdev *)(uintptr_t)event_dev); + + return 0; +} + +static int +dma_adapter_vchan_free(struct cnxk_dpi_conf *vchan) +{ + rte_mempool_free(vchan->adapter_info.req_mp); + vchan->adapter_info.enabled = false; + + return 0; +} + +int +cnxk_dma_adapter_vchan_del(const int16_t dma_dev_id, uint16_t vchan_id) +{ + struct cnxk_dpi_vf_s *dpivf; + struct cnxk_dpi_conf *vchan; + + dpivf = rte_dma_fp_objs[dma_dev_id].dev_private; + if ((int16_t)vchan_id == -1) { + uint16_t vchan_id; + + for (vchan_id = 0; vchan_id < dpivf->num_vchans; vchan_id++) { + vchan = &dpivf->conf[vchan_id]; + if (vchan->adapter_info.enabled) + dma_adapter_vchan_free(vchan); + } + } else { + vchan = &dpivf->conf[vchan_id]; + if (vchan->adapter_info.enabled) + dma_adapter_vchan_free(vchan); + } + + return 0; +} diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index 2a30b97bff..f2e07b8665 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -317,7 +317,6 @@ endforeach headers = files('rte_pmd_cnxk_eventdev.h') deps += ['bus_pci', 'common_cnxk', 'net_cnxk', 'crypto_cnxk', 'dma_cnxk'] - require_iova_in_mbuf = false annotate_locks = false