From patchwork Thu Feb 29 10:19:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 137464 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B756A43C35; Thu, 29 Feb 2024 11:20:41 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CD15640E0F; Thu, 29 Feb 2024 11:20:40 +0100 (CET) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2048.outbound.protection.outlook.com [40.107.243.48]) by mails.dpdk.org (Postfix) with ESMTP id 590F5402B4; Thu, 29 Feb 2024 11:20:38 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FI7jHxOFnZ97chsmSZaJpzL7U8MbU0FFR8KHOuD6gvZnspW7v3m8caqto7/nfTsk03lX0dLymqolYmcDmSaujCuQMJFpAIUsFBn6y3L2TiMcxTBkfJ0wIDnXYAGrp7BOX2eU/cou74q2ahRNtrHnNXyRBCK4DXazpJWU1tRLZh4PYoctlEQXMPQgmq5rodKZMLfyqYU2pqovIOrJ3iNPNaqldhhzx3NSwYFYEi+mZQJIRdDhhXMToQCIQJ1MYsnjnDmzBdm2GUfMh6Mq4U90l9NW53QbWDuzJrSqEMnFu9pxm0B7ajwWeDdSZWw0iXvsUFH8hlGpAhMFSlTN95Ukdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=keYC1v8acV2JHX+26PvY63cQkgRJ3T4GCKc7Usjp3zs=; b=kfxOhPUzBvpEsJGURekmT8PmQZzUYBdL2X5pFJEMonmJa7usWR3iCfr4K57kdjRWiwvmPKIip0rdNtCdutrYtPoy0+j+P8uG9vgH3pogGYoopVeOZzKqpKisSbdxjxoB/T+R/K/fUHba3MfQY0+QQfJJASCqsumFHUnb9bdQ2dPg7rlaqTNvPHcBJoOSklp13tH3KPEw//YP1LKg00sunbhtGjIlOUxSwptsYOjZzMGF5qn4xX7xnAIYdy2uiU+Qs/CBOBA0Ye8+niqMhiIgN7bv7hceCAe2T1tPfJOp61m/vvJtVzXqRuMxNu7aedzVpf+VSOW1IVTkele0yUnV1Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=keYC1v8acV2JHX+26PvY63cQkgRJ3T4GCKc7Usjp3zs=; b=JLsRtzG9U4F5vdjmt0Yr4feDT7HNXQWx72RUtZzuezua/jNpRYQz8aC+JU0jOTL2EfNrsLT6M8HtaRccCr3GVlRnygxW332UO4T8hF2MSjKuAiUJR6YQWy9degraXM+TZibti5T93fMitDPYrfYGz1twQ5c20JGFytK+Bl2Up4eIhZ8LpBTTimhcYjLgIW41tK46xDSX2BCiz6MZJV7fQnN8tChkHngppg/R+D7KPR3TmNfGitIjqqRHn+hrLyrxv8x68cowhUndrv2cvuDPAejY5f+TVzc6HlP8s4HIkd03JFKAbRPUXc76/Cp/cnP6BlfV0CBdL/H+faiw6qYeBw== Received: from BN9PR03CA0180.namprd03.prod.outlook.com (2603:10b6:408:f4::35) by PH7PR12MB8780.namprd12.prod.outlook.com (2603:10b6:510:26b::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.36; Thu, 29 Feb 2024 10:20:35 +0000 Received: from BN1PEPF00004685.namprd03.prod.outlook.com (2603:10b6:408:f4:cafe::ac) by BN9PR03CA0180.outlook.office365.com (2603:10b6:408:f4::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.32 via Frontend Transport; Thu, 29 Feb 2024 10:20:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN1PEPF00004685.mail.protection.outlook.com (10.167.243.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Thu, 29 Feb 2024 10:20:33 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Thu, 29 Feb 2024 02:20:16 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 29 Feb 2024 02:20:10 -0800 From: Gregory Etelson To: CC: , , , , Suanming Mou , Dariusz Sosnowski , Viacheslav Ovsiienko , "Ori Kam" , Matan Azrad Subject: [PATCH] net/mlx5: fix action template expansion: support indirect actions list Date: Thu, 29 Feb 2024 12:19:55 +0200 Message-ID: <20240229101955.586947-1-getelson@nvidia.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004685:EE_|PH7PR12MB8780:EE_ X-MS-Office365-Filtering-Correlation-Id: f9f70ae7-ecdd-4f2a-55e6-08dc39101064 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2Y+hNZCYj3U/IWRyHl20CorZwf7cqwE5Hnd7cLke9BBsJZphQ1j5hggdw9zKYMGyD/ZYa0ZHvq1T+UyWrPpOu73EWNTpjurVSZ84zy6lDmNVlwfTOY3r0bPPm65f4JVEtdob0bSxA4CttTKPqmM4BSXOrInS6MCrA81hpL2fPo9iYihItd6cFJ4khq2y+EwoBN1WBMDpSenld0rtlwyIeoeAOT9q5fHOsjQx/hvxNFUSxxHHylxeiHMwaCmM0yW0LiazFxHNu2qEYgs00ISupIps/4J3bnE2wiN91OuRJPh/cFlEA7Q9tHSDBGDesNER659r7Kfruo9fLabC6Lqlz5X1ozeUdwDg/CT7Pro9KOJYIYfhueWCeFos97ksJSEDIf76nj0ISv/ovrCQ/s5tlR6wbuSjK2CbFtsJnpjZTDR5m+QDCCYJANL6H5IXS3NfulE7+F+nVisWarIuLvoA2BGmsrpCvWBhcH5IfVHXgh85Nbh6Tmh+NT4WSgm+kWAy2zzapxLibQgi+5VVtZOGAQ0g9DY0f5Jk4Cdg/vsoFYdpSZZuzLGZKqSJW8fXeQo5AWXdT4u85IRyEJ6eBmgUb1lJSDpPLdSkay0MVYpurtmTiK8AFMDky/QJvXZgoSDTbdpLWlYWpGHk7O2W7mnbPAHPKpGXDnNRQ+tFcJ6dOMKV0hc3TACyAD11ipMZacrP+hD6okVcUsQRzR5oQB+tb4SordLTndxnrtlmTP6KU6po5ReYu9IErIhkht35BdAM X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Feb 2024 10:20:33.5007 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9f70ae7-ecdd-4f2a-55e6-08dc39101064 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004685.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8780 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MLX5 PMD actions template compilation may implicitly add MODIFY_HEADER to actions list provided by application. MLX5 actions in a template list must be arranged according to the HW supported order. The PMD must place new MODIFY_HEADER in the correct location relative to existing actions. The patch adds indirect actions list to calculation of the new MODIFY_HEADER location. Fixes: e26f50adbf38 ("net/mlx5: support indirect list meter mark action") Cc: stable@dpdk.org Signed-off-by: Gregory Etelson Acked-by: Suanming Mou --- drivers/net/mlx5/mlx5_flow_hw.c | 80 +++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index f778fd0698..585f1ba925 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -88,6 +88,9 @@ mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev, static void mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment); +static __rte_always_inline enum mlx5_indirect_list_type +flow_hw_inlist_type_get(const struct rte_flow_action *actions); + static __rte_always_inline int mlx5_multi_pattern_reformat_to_index(enum mlx5dr_action_type type) { @@ -5803,6 +5806,69 @@ mlx5_decap_encap_reformat_type(const struct rte_flow_action *actions, MLX5_FLOW_ACTION_ENCAP : MLX5_FLOW_ACTION_DECAP; } +enum mlx5_hw_indirect_list_relative_position { + MLX5_INDIRECT_LIST_POSITION_UNKNOWN = -1, + MLX5_INDIRECT_LIST_POSITION_BEFORE_MH = 0, + MLX5_INDIRECT_LIST_POSITION_AFTER_MH, +}; + +static enum mlx5_hw_indirect_list_relative_position +mlx5_hw_indirect_list_mh_position(const struct rte_flow_action *action) +{ + const struct rte_flow_action_indirect_list *conf = action->conf; + enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(conf->handle); + enum mlx5_hw_indirect_list_relative_position pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN; + const union { + struct mlx5_indlst_legacy *legacy; + struct mlx5_hw_encap_decap_action *reformat; + struct rte_flow_action_list_handle *handle; + } h = { .handle = conf->handle}; + + switch (list_type) { + case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY: + switch (h.legacy->legacy_type) { + case RTE_FLOW_ACTION_TYPE_AGE: + case RTE_FLOW_ACTION_TYPE_COUNT: + case RTE_FLOW_ACTION_TYPE_CONNTRACK: + case RTE_FLOW_ACTION_TYPE_METER_MARK: + case RTE_FLOW_ACTION_TYPE_QUOTA: + pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH; + break; + case RTE_FLOW_ACTION_TYPE_RSS: + pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH; + break; + default: + pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN; + break; + } + break; + case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR: + pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH; + break; + case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT: + switch (h.reformat->action_type) { + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2: + pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH; + break; + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3: + pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH; + break; + default: + pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN; + break; + } + break; + default: + pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN; + break; + } + return pos; +} + +#define MLX5_HW_EXPAND_MH_FAILED 0xffff + static inline uint16_t flow_hw_template_expand_modify_field(struct rte_flow_action actions[], struct rte_flow_action masks[], @@ -5839,6 +5905,7 @@ flow_hw_template_expand_modify_field(struct rte_flow_action actions[], * @see action_order_arr[] */ for (i = act_num - 2; (int)i >= 0; i--) { + enum mlx5_hw_indirect_list_relative_position pos; enum rte_flow_action_type type = actions[i].type; uint64_t reformat_type; @@ -5869,6 +5936,13 @@ flow_hw_template_expand_modify_field(struct rte_flow_action actions[], if (actions[i - 1].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) i--; break; + case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST: + pos = mlx5_hw_indirect_list_mh_position(&actions[i]); + if (pos == MLX5_INDIRECT_LIST_POSITION_UNKNOWN) + return MLX5_HW_EXPAND_MH_FAILED; + if (pos == MLX5_INDIRECT_LIST_POSITION_BEFORE_MH) + goto insert; + break; default: i++; /* new MF inserted AFTER actions[i] */ goto insert; @@ -6822,6 +6896,12 @@ flow_hw_actions_template_create(struct rte_eth_dev *dev, action_flags, act_num, expand_mf_num); + if (pos == MLX5_HW_EXPAND_MH_FAILED) { + rte_flow_error_set(error, ENOMEM, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, "modify header expansion failed"); + return NULL; + } act_num += expand_mf_num; for (i = pos + expand_mf_num; i < act_num; i++) src_off[i] += expand_mf_num;