From patchwork Thu Feb 22 12:45:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 137035 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E433743B74; Thu, 22 Feb 2024 13:45:33 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 81C5B40DCE; Thu, 22 Feb 2024 13:45:28 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id D98F840281 for ; Thu, 22 Feb 2024 13:45:22 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41M9BLVi021857; Thu, 22 Feb 2024 04:45:19 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=yedSnrrKjdIOQXdvZ0WK3d8eF5VOpR0tkM0w87ABZ3M=; b=O/5 bbfOiOCnsCu/MuQoCT7KTqeMe7wFzrO8kx+eAcX/k9/eKlvMiEd82nmkr68pD9db oSQuqV7Yj4LKKIjN2B5DArYMmb89MGMF3Sxkbnlqj+tEwSrGiTe698pWY0G6ILOT nnXJEP6eL7BX30eXbxLo0J/CkCFLTRqmjhO6Ld++jzUvaIu9JzikjKorFdwgat6n rxzVmDg/3PqqZ9Y9nIxSRZHHvNrWNRy4Tm4PiT0LN+WocFSzUYI2fyN8kH+eP5HP 4fDSo9+pVoj3Oya6+F67b5CgAdjQ7mp1KG3Wlm8MTTMElHNXyW00u5epOxq96w9W 5/z+VOeI4dW2QYvICwA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3we3dw8mau-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 22 Feb 2024 04:45:19 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 22 Feb 2024 04:45:17 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 22 Feb 2024 04:45:17 -0800 Received: from MININT-80QBFE8.corp.innovium.com (unknown [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 6E9A93F725B; Thu, 22 Feb 2024 04:45:14 -0800 (PST) From: To: , , , , Ruifeng Wang , "Bruce Richardson" CC: , Pavan Nikhilesh , Chengwen Feng , Honnappa Nagarahalli Subject: [PATCH v5 3/3] config/arm: allow WFE to be enabled config time Date: Thu, 22 Feb 2024 18:15:03 +0530 Message-ID: <20240222124503.17043-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240222124503.17043-1-pbhagavatula@marvell.com> References: <20240221202018.14179-1-pbhagavatula@marvell.com> <20240222124503.17043-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: nblaq-bHza4YpuVWfChGICbwMG55OxvF X-Proofpoint-ORIG-GUID: nblaq-bHza4YpuVWfChGICbwMG55OxvF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-22_10,2024-02-22_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Allow RTE_ARM_USE_WFE to be enabled at meson configuration time by passing it via c_args instead of modifying `config/arm/meson.build`. Example usage: meson build -Dc_args='-DRTE_ARM_USE_WFE' \ --cross-file config/arm/arm64_cn10k_linux_gcc Signed-off-by: Pavan Nikhilesh Acked-by: Chengwen Feng Acked-by: Ruifeng Wang Reviewed-by: Honnappa Nagarahalli Reviewed-by: Wathsala Vithanage --- config/arm/meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 87ff5039f6..c26b8fb975 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -17,7 +17,9 @@ flags_common = [ # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF], # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false], - ['RTE_ARM_USE_WFE', false], + # Enable use of ARM wait for event instruction. + # ['RTE_ARM_USE_WFE', false], + ['RTE_ARCH_ARM64', true], ['RTE_CACHE_LINE_SIZE', 128] ]