From patchwork Wed Feb 21 20:20:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 136977 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CB8F943B62; Wed, 21 Feb 2024 21:20:45 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 79207406BA; Wed, 21 Feb 2024 21:20:39 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4AD3B4069F for ; Wed, 21 Feb 2024 21:20:35 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41LGuE9e016559; Wed, 21 Feb 2024 12:20:32 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=jhtz9dlK3O03yzxFTwcvo/36Sjd2cn9/cwc/FJwjWGg=; b=PM9 CUEKGVEW4ti7S69XwIYjzDC5GAntGf+vV1XitGrbaYi/UdqC17/kT0PMs557VE0j HTVHbPE3Cx7yUJwI46MnROp3XgPp89/SJU+00IKsj+8isbEBfG9I7oRTmKkDJ7C0 ucx+161SVy3EraFLb4jzRj5jnk551TnBgtKK2JtaFi2wyLKhd4AK+H/ihM8AizVM +qH9E7EOzUZ9uxGTfKBi8BVepe1xXPu8v3daUmVbRPFYbxKBCCzMwjeljQlNgTQ7 0vL23m/fyN8xCrJ6Nem6XjfQaKKrpklJrma+f+PToJ9utwsQATauqbTBfP5SMob9 d5cA09v34EM5zdhstcw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3wd21kdrg1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 21 Feb 2024 12:20:32 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 21 Feb 2024 12:20:30 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 21 Feb 2024 12:20:30 -0800 Received: from MININT-80QBFE8.corp.innovium.com (unknown [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 89C943F70AD; Wed, 21 Feb 2024 12:20:27 -0800 (PST) From: To: , , , , Ruifeng Wang , "Bruce Richardson" CC: , Pavan Nikhilesh , Chengwen Feng , Honnappa Nagarahalli Subject: [PATCH v4 3/3] config/arm: allow WFE to be enabled config time Date: Thu, 22 Feb 2024 01:50:18 +0530 Message-ID: <20240221202018.14179-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240221202018.14179-1-pbhagavatula@marvell.com> References: <20240202085031.10237-1-pbhagavatula@marvell.com> <20240221202018.14179-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: wUbIHixBVZwdCitYl71K7O_503SLjAan X-Proofpoint-ORIG-GUID: wUbIHixBVZwdCitYl71K7O_503SLjAan X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-21_07,2024-02-21_02,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Allow RTE_ARM_USE_WFE to be enabled at meson configuration time by passing it via c_args instead of modifying `config/arm/meson.build`. Example usage: meson build -Dc_args='-DRTE_ARM_USE_WFE' \ --cross-file config/arm/arm64_cn10k_linux_gcc Signed-off-by: Pavan Nikhilesh Acked-by: Chengwen Feng Acked-by: Ruifeng Wang Reviewed-by: Honnappa Nagarahalli Reviewed-by: Wathsala Vithanage --- config/arm/meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index f6521653c8..78e80f6699 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -17,7 +17,9 @@ flags_common = [ # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF], # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false], - ['RTE_ARM_USE_WFE', false], + # Enable use of ARM wait for event instruction. + # ['RTE_ARM_USE_WFE', false], + ['RTE_ARCH_ARM64', true], ['RTE_CACHE_LINE_SIZE', 128] ]