From patchwork Tue Feb 6 14:39:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 136431 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AB2C443A3A; Tue, 6 Feb 2024 15:41:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 614D842D55; Tue, 6 Feb 2024 15:40:31 +0100 (CET) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2054.outbound.protection.outlook.com [40.107.223.54]) by mails.dpdk.org (Postfix) with ESMTP id BBB2C42D2E for ; Tue, 6 Feb 2024 15:40:29 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fw4UpZ+R6TGudzBhcIxmcKEoKqN8+gau/oEqiXYvPJ45R+ag2BXyemlRJYBJnHCZOoMkwf+ntHXjEyD0+0iMCj26Dr8YD4m6TbJSj3jOlCXZC3x8TdDwkNmRoyLSq6oXg25spIq2OazOAquuAjCYqoMR5V2ChRnVgvIDnM5GFfYxPiOJhKHlAcUCCWm0L/f08utPPrK1mvBQz4Ymxf96ep2+u8oMceZuUV6JNEC9TsvBb4Vdq+T6klYTpS4fOu/0k5jILNJ8H2Th68iAeFfVw4dYWyE4cvRTlO/bItG4d/z654OHkNkleaQA6V/J6UFh/2mBAsH36u0O5ijWylE+8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sxwpUoMLrqhcb/ekBCqceEZrUvOBJ/Af6z/uuQylXsA=; b=CCviN+dJNaBSGlticGv4Co7lltPJRTdW3ueLAZHfqsnNEJ93WS5SRwFsQlwHloGCVmH1gocFNCTav+xjwzDZJkp7uCyJ4DttgTx1QeJXtP2U9NXXl1znKjscOTjGi8jNbsjEqQbf1ECTeLkhzjE0lVhSlbAX3nYXg1Zqv/epvw3la4U9CCZWtLxAPXDvXDWWUgulEEd9fsLEDGQ0+QJUfJAI2ppUCaK8VQ4vyme9X2upNHi0sWzsPXvUc0ZgOYUIq0+u8L4NDfXDI5FLZg+hBCOMVi/mI6ybrSSbDHvlEEIkZMcptIKTHcZOzxNwPVna9vjv+wlmVtOwvfzlPD0sBA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sxwpUoMLrqhcb/ekBCqceEZrUvOBJ/Af6z/uuQylXsA=; b=CeILeUpGfRgSPCP5GBXenm1PzumDc4lTS49cYHg2P+RjVH/2EmRGJrpgTL6PieQ2zN0L5o/v8k/Cf2TdnSR3M6eTeL9aZy4AWU1Xr9Ed3H+QWVcfec6NuiY1AdbzR/WwpWE3MlcbXesyjzM9JytMcnSBrPbvLr4DY8MWZE1p+9tn6/qnYZV1V/+PWc/MplVF7OW13YabqPj3S5oV6E/Xk3xZ7f4NYtUBttKCvm/p556iuw4yU04T3qjesDRcfBXVil3Zk3zYM0k9HSfLrgDAnMkNSfqlLrKPSRK0Zab9gKoFpqWwUeWf1+dMWpvjFeOr0XCfnO36Jiyvkg8/ZemhCA== Received: from DS7PR03CA0332.namprd03.prod.outlook.com (2603:10b6:8:55::19) by DM8PR12MB5494.namprd12.prod.outlook.com (2603:10b6:8:24::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.16; Tue, 6 Feb 2024 14:40:26 +0000 Received: from DS2PEPF0000343B.namprd02.prod.outlook.com (2603:10b6:8:55:cafe::56) by DS7PR03CA0332.outlook.office365.com (2603:10b6:8:55::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.36 via Frontend Transport; Tue, 6 Feb 2024 14:40:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS2PEPF0000343B.mail.protection.outlook.com (10.167.18.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.19 via Frontend Transport; Tue, 6 Feb 2024 14:40:24 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 6 Feb 2024 06:40:13 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 6 Feb 2024 06:40:12 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41 via Frontend Transport; Tue, 6 Feb 2024 06:40:10 -0800 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH v1 6/7] net/mlx5: support modify IPv6 traffic class field Date: Tue, 6 Feb 2024 16:39:49 +0200 Message-ID: <20240206143950.1499532-7-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240206143950.1499532-1-michaelba@nvidia.com> References: <20240206143950.1499532-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|DM8PR12MB5494:EE_ X-MS-Office365-Filtering-Correlation-Id: bb18fe2e-1bb7-4d39-4141-08dc27218e06 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TO+sx1t0mX0Nrkyl6Q1+JMrNw5M2HSK+T4/n/poMv4ZjYuXc3LkDeSCHb1iKpZIDPdsciIjlZW4BNN3ArrOtXx99x4i+rPFcZgfSGnj4kODQo9oglN1eEup+G/GwHphg6Cx5gOsN1WEMa7SwEoPSCYH/3POXSG5qqIzQKaJQ7fI4v7mXuzLMa54IVkNLEj0nIaxIeiv9f3q5WkQVcx5oM8apkpAkl5oNfQDzhZUux86/rvQbjM6pFyEiIsw7OangAZn20DPErndHfKPIxAwk1TogjN7X9Sd5t7SFQoWVlisXnV5LWmi7MM5NUX8tl4rQHsFVVCLazhtsIS8sD/HKTeRB4WlNCzavtzJVTnfSwtaP7nCqFWYVOF+PsPEmvvcbnORW5hM5i+deSNubCYtCxupS44iHYKpMWC6SvUMTvaDMH72ks6NBAZrVOwv5pmMlC3NufzzTKDHgZ5CjKLqx6fyG1WIMrQ5gwOsctx/iSehT3+vpbnc/kz7vAa+tirmhXr1cUdM/eXSzbgjNPN/WjfwqNCWhbdNeqJTwSzsGRuwubV/tk7p4HJsCxuUW5OOgMl7SI0kRjP685k9OLy/Hd3va8sRwWO/X5IHoYt9tpRWzK2iVA7KBdJgQqtPwVzdnQzZ1tNNB8BaKiy24IS5lqeAKOg+e0l1hI+LwmADjzbX/9ro4PAeURFS5EnzLSS0VYEqx5gnd8UkwUQl6mx7VTU1CglUfhHzsZXcGgukdh4oqEkX4IEHsRPIbxcFNiCiK X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(396003)(346002)(376002)(136003)(39860400002)(230922051799003)(1800799012)(82310400011)(64100799003)(451199024)(186009)(40470700004)(46966006)(36840700001)(40480700001)(55016003)(36756003)(40460700003)(478600001)(7636003)(1076003)(107886003)(83380400001)(336012)(41300700001)(356005)(426003)(82740400003)(6286002)(47076005)(26005)(2616005)(70206006)(7696005)(6916009)(2906002)(4326008)(5660300002)(86362001)(54906003)(70586007)(8936002)(6666004)(8676002)(316002)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2024 14:40:24.8383 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb18fe2e-1bb7-4d39-4141-08dc27218e06 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5494 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add HW steering support for IPv6 traffic class field modification. Copy from inner IPv6 traffic class field is also supported using "level=2". Signed-off-by: Michael Baum --- doc/guides/rel_notes/release_24_03.rst | 1 + drivers/net/mlx5/mlx5_flow_dv.c | 11 +++++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 3 ++- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 10268b7879..272bc9d056 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -100,6 +100,7 @@ New Features * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_SPI`` flow action. * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_SEQ_NUM`` flow action. * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_PROTO`` flow action. + * Added HW steering support for modify field ``RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS`` flow action. Removed Items diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 8454d00d4f..90ef21d75b 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1394,6 +1394,7 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev, return 32; case RTE_FLOW_FIELD_IPV6_DSCP: return 6; + case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS: case RTE_FLOW_FIELD_IPV6_HOPLIMIT: case RTE_FLOW_FIELD_IPV6_PROTO: return 8; @@ -1795,6 +1796,16 @@ mlx5_flow_field_id_to_modify_info else info[idx].offset = off_be; break; + case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS: + MLX5_ASSERT(data->offset + width <= 8); + off_be = 8 - (data->offset + width); + modi_id = CALC_MODI_ID(IPV6_TRAFFIC_CLASS, data->level); + info[idx] = (struct field_modify_info){1, 0, modi_id}; + if (mask) + mask[idx] = flow_modify_info_mask_8(width, off_be); + else + info[idx].offset = off_be; + break; case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN: MLX5_ASSERT(data->offset + width <= 16); off_be = 16 - (data->offset + width); diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index fc0f9dabb3..90e3cf2555 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -2871,7 +2871,7 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job, * bits left. Shift the data left for IPV6 DSCP */ if (field->id == MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS && - !(mask & MLX5_IPV6_HDR_ECN_MASK)) + mhdr_action->dst.field == RTE_FLOW_FIELD_IPV6_DSCP) data <<= MLX5_IPV6_HDR_DSCP_SHIFT; data = (data & mask) >> off_b; job->mhdr_cmd[i++].data1 = rte_cpu_to_be_32(data); @@ -5058,6 +5058,7 @@ flow_hw_validate_modify_field_level(const struct rte_flow_action_modify_data *da case RTE_FLOW_FIELD_IPV4_TTL: case RTE_FLOW_FIELD_IPV4_SRC: case RTE_FLOW_FIELD_IPV4_DST: + case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS: case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN: case RTE_FLOW_FIELD_IPV6_HOPLIMIT: case RTE_FLOW_FIELD_IPV6_SRC: