From patchwork Fri Feb 2 08:50:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 136306 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EBDBC43A4E; Fri, 2 Feb 2024 10:08:54 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DAD7942DC3; Fri, 2 Feb 2024 10:08:54 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 989144026E for ; Fri, 2 Feb 2024 10:08:53 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4121W9vH011451; Fri, 2 Feb 2024 01:08:49 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=rxTq0W37eYTlvcN7pLXVcfvG2fn8t/CsA6mkjb/qg/0=; b=SMX UovKZMO3SL/H6cAHj8fkIn/7BQgxc4AU+9bGg6D9RcYOvnVln/ffkle6AHgIunqP AtTGuyklzI+TJN0xTmQIex9eP/vbzn9cAsVEvp7CCFYvtJKwm1C1ult/+HFZmGuU fA1ZFaVJmb9VHS8ZKMUdFqEgqjN5AMku6MaHNNt5tKIwNo+FiVj3F+fgr+KbbA2b E2t/vN/6lbG7lhds9+MxrQduEUahQYNc4g6YN59AHKe5hoeYSpPHRbKFhyrYyIDo SHwUpb9kPR0+7n2K0jW4hAdnSrkpDErx7+dwOq6rxlWHN+a2Ec6S6gDP5c7e+oF3 ba+2zqV2cu81uF14rdw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3w0ptnh2md-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 02 Feb 2024 01:08:49 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 2 Feb 2024 01:08:48 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 2 Feb 2024 01:08:48 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 0ECE95C6943; Fri, 2 Feb 2024 00:50:38 -0800 (PST) From: To: , , , "Ruifeng Wang" , Bruce Richardson CC: , Pavan Nikhilesh , Chengwen Feng Subject: [PATCH v3 3/3] config/arm: allow WFE to be enabled config time Date: Fri, 2 Feb 2024 14:20:31 +0530 Message-ID: <20240202085031.10237-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240202085031.10237-1-pbhagavatula@marvell.com> References: <20240201215731.4543-1-pbhagavatula@marvell.com> <20240202085031.10237-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: s3guE01wRjgyDHpC7DbdGFCgk__wlKzS X-Proofpoint-GUID: s3guE01wRjgyDHpC7DbdGFCgk__wlKzS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-02_03,2024-01-31_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Allow RTE_ARM_USE_WFE to be enabled at meson configuration time by passing it via c_args instead of modifying `config/arm/meson.build`. Example usage: meson build -Dc_args='-DRTE_ARM_USE_WFE' \ --cross-file config/arm/arm64_cn10k_linux_gcc Signed-off-by: Pavan Nikhilesh Acked-by: Chengwen Feng Acked-by: Ruifeng Wang Reviewed-by: Honnappa Nagarahalli Reviewed-by: Wathsala Vithanage --- config/arm/meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 4e44d1850bae..01870a23328a 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -17,7 +17,9 @@ flags_common = [ # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF], # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false], - ['RTE_ARM_USE_WFE', false], + # Enable use of ARM wait for event instruction. + # ['RTE_ARM_USE_WFE', false], + ['RTE_ARCH_ARM64', true], ['RTE_CACHE_LINE_SIZE', 128] ]