@@ -51,4 +51,19 @@ enum gve_state_flags_bit {
GVE_PRIV_FLAGS_NAPI_ENABLED = 4,
};
+enum gve_rss_hash_algorithm {
+ GVE_RSS_HASH_UNDEFINED = 0,
+ GVE_RSS_HASH_TOEPLITZ = 1,
+};
+
+struct gve_rss_config {
+ uint16_t hash_types;
+ enum gve_rss_hash_algorithm alg;
+ uint16_t key_size;
+ uint16_t indir_size;
+ uint8_t *key;
+ uint32_t *indir;
+};
+
+
#endif /* _GVE_H_ */
@@ -389,6 +389,9 @@ static int gve_adminq_issue_cmd(struct gve_priv *priv,
case GVE_ADMINQ_DECONFIGURE_DEVICE_RESOURCES:
priv->adminq_dcfg_device_resources_cnt++;
break;
+ case GVE_ADMINQ_CONFIGURE_RSS:
+ priv->adminq_cfg_rss_cnt++;
+ break;
case GVE_ADMINQ_SET_DRIVER_PARAMETER:
priv->adminq_set_driver_parameter_cnt++;
break;
@@ -938,3 +941,58 @@ int gve_adminq_get_ptype_map_dqo(struct gve_priv *priv,
gve_free_dma_mem(&ptype_map_dma_mem);
return err;
}
+
+int gve_adminq_configure_rss(struct gve_priv *priv,
+ struct gve_rss_config *rss_config)
+{
+ struct gve_dma_mem indirection_table_dma_mem;
+ struct gve_dma_mem rss_key_dma_mem;
+ union gve_adminq_command cmd;
+ __be32 *indir = NULL;
+ u8 *key = NULL;
+ int err = 0;
+ int i;
+
+ if (!rss_config->indir_size || !rss_config->key_size)
+ return -EINVAL;
+
+ indir = gve_alloc_dma_mem(&indirection_table_dma_mem,
+ rss_config->indir_size *
+ sizeof(*rss_config->indir));
+ if (!indir) {
+ err = -ENOMEM;
+ goto out;
+ }
+ for (i = 0; i < rss_config->indir_size; i++)
+ indir[i] = cpu_to_be32(rss_config->indir[i]);
+
+ key = gve_alloc_dma_mem(&rss_key_dma_mem,
+ rss_config->key_size *
+ sizeof(*rss_config->key));
+ if (!key) {
+ err = -ENOMEM;
+ goto out;
+ }
+ memcpy(key, rss_config->key, rss_config->key_size);
+
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.opcode = cpu_to_be32(GVE_ADMINQ_CONFIGURE_RSS);
+ cmd.configure_rss = (struct gve_adminq_configure_rss) {
+ .hash_types = cpu_to_be16(rss_config->hash_types),
+ .halg = rss_config->alg,
+ .hkey_len = cpu_to_be16(rss_config->key_size),
+ .indir_len = cpu_to_be16(rss_config->indir_size),
+ .hkey_addr = cpu_to_be64(rss_key_dma_mem.pa),
+ .indir_addr = cpu_to_be64(indirection_table_dma_mem.pa),
+ };
+
+ err = gve_adminq_execute_cmd(priv, &cmd);
+
+out:
+ if (indir)
+ gve_free_dma_mem(&indirection_table_dma_mem);
+ if (key)
+ gve_free_dma_mem(&rss_key_dma_mem);
+ return err;
+}
+
@@ -19,6 +19,7 @@ enum gve_adminq_opcodes {
GVE_ADMINQ_DESTROY_TX_QUEUE = 0x7,
GVE_ADMINQ_DESTROY_RX_QUEUE = 0x8,
GVE_ADMINQ_DECONFIGURE_DEVICE_RESOURCES = 0x9,
+ GVE_ADMINQ_CONFIGURE_RSS = 0xA,
GVE_ADMINQ_SET_DRIVER_PARAMETER = 0xB,
GVE_ADMINQ_REPORT_STATS = 0xC,
GVE_ADMINQ_REPORT_LINK_SPEED = 0xD,
@@ -377,6 +378,27 @@ struct gve_adminq_get_ptype_map {
__be64 ptype_map_addr;
};
+#define GVE_RSS_HASH_IPV4 BIT(0)
+#define GVE_RSS_HASH_TCPV4 BIT(1)
+#define GVE_RSS_HASH_IPV6 BIT(2)
+#define GVE_RSS_HASH_IPV6_EX BIT(3)
+#define GVE_RSS_HASH_TCPV6 BIT(4)
+#define GVE_RSS_HASH_TCPV6_EX BIT(5)
+#define GVE_RSS_HASH_UDPV4 BIT(6)
+#define GVE_RSS_HASH_UDPV6 BIT(7)
+#define GVE_RSS_HASH_UDPV6_EX BIT(8)
+
+/* RSS configuration command */
+struct gve_adminq_configure_rss {
+ __be16 hash_types;
+ u8 halg; /* hash algorithm */
+ u8 reserved;
+ __be16 hkey_len;
+ __be16 indir_len;
+ __be64 hkey_addr;
+ __be64 indir_addr;
+};
+
union gve_adminq_command {
struct {
__be32 opcode;
@@ -391,6 +413,7 @@ union gve_adminq_command {
struct gve_adminq_describe_device describe_device;
struct gve_adminq_register_page_list reg_page_list;
struct gve_adminq_unregister_page_list unreg_page_list;
+ struct gve_adminq_configure_rss configure_rss;
struct gve_adminq_set_driver_parameter set_driver_param;
struct gve_adminq_report_stats report_stats;
struct gve_adminq_report_link_speed report_link_speed;
@@ -404,6 +427,8 @@ union gve_adminq_command {
GVE_CHECK_UNION_LEN(64, gve_adminq_command);
+struct gve_priv;
+struct gve_queue_page_list;
int gve_adminq_alloc(struct gve_priv *priv);
void gve_adminq_free(struct gve_priv *priv);
void gve_adminq_release(struct gve_priv *priv);
@@ -433,4 +458,8 @@ int gve_adminq_get_ptype_map_dqo(struct gve_priv *priv,
int gve_adminq_verify_driver_compatibility(struct gve_priv *priv,
u64 driver_info_len,
dma_addr_t driver_info_addr);
+
+int gve_adminq_configure_rss(struct gve_priv *priv,
+ struct gve_rss_config *rss_config);
+
#endif /* _GVE_ADMINQ_H */
@@ -39,7 +39,10 @@
RTE_ETH_RSS_IPV6 | \
RTE_ETH_RSS_IPV6_EX | \
RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
- RTE_ETH_RSS_IPV6_TCP_EX)
+ RTE_ETH_RSS_IPV6_TCP_EX | \
+ RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
+ RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
+ RTE_ETH_RSS_IPV6_UDP_EX)
/* A list of pages registered with the device during setup and used by a queue
* as buffers
@@ -264,6 +267,7 @@ struct gve_priv {
uint32_t adminq_destroy_tx_queue_cnt;
uint32_t adminq_destroy_rx_queue_cnt;
uint32_t adminq_dcfg_device_resources_cnt;
+ uint32_t adminq_cfg_rss_cnt;
uint32_t adminq_set_driver_parameter_cnt;
uint32_t adminq_report_stats_cnt;
uint32_t adminq_report_link_speed_cnt;