[3/6] net/iavf: remove incorrect 16B descriptor read block

Message ID 20240123114053.172189-4-bruce.richardson@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Series remove incorrect code for loading 16B descriptors |


Context Check Description
ci/checkpatch success coding style OK

Commit Message

Bruce Richardson Jan. 23, 2024, 11:40 a.m. UTC
  By default, the driver works with 32B descriptors, but has a separate
descriptor read block for reading two descriptors at a time when using
16B descriptors. However, the 32B reads used are not guaranteed to be
atomic, which will cause issues if that is not the case on a system,
since the descriptors may be read in an undefined order.  Remove the
block, to avoid issues, and just use the regular descriptor reading path
for 16B descriptors, if that support is enabled at build time.

Fixes: af0c246a3800 ("net/iavf: enable AVX2 for iavf")
Cc: stable@dpdk.org

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
 drivers/net/iavf/iavf_rxtx_vec_avx2.c | 13 -------------
 1 file changed, 13 deletions(-)


diff --git a/drivers/net/iavf/iavf_rxtx_vec_avx2.c b/drivers/net/iavf/iavf_rxtx_vec_avx2.c
index 510b4d8f1c..3cec1eef9d 100644
--- a/drivers/net/iavf/iavf_rxtx_vec_avx2.c
+++ b/drivers/net/iavf/iavf_rxtx_vec_avx2.c
@@ -194,19 +194,6 @@  _iavf_recv_raw_pkts_vec_avx2(struct iavf_rx_queue *rxq,
 		__m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
-		/* for AVX we need alignment otherwise loads are not atomic */
-		if (avx_aligned) {
-			/* load in descriptors, 2 at a time, in reverse order */
-			raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6));
-			rte_compiler_barrier();
-			raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4));
-			rte_compiler_barrier();
-			raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2));
-			rte_compiler_barrier();
-			raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0));
-		} else
 			const __m128i raw_desc7 =
 				_mm_load_si128((void *)(rxdp + 7));