From patchwork Tue Jan 23 11:40:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 136058 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2AB27439A7; Tue, 23 Jan 2024 12:41:20 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8DF0D410F2; Tue, 23 Jan 2024 12:41:16 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by mails.dpdk.org (Postfix) with ESMTP id C2DB9402B0; Tue, 23 Jan 2024 12:41:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706010075; x=1737546075; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I/2EzG5KN81ZqWLYgs0vgLi8timi0LOTCBJaIHoyZmk=; b=UajyE49Az+shjREvI5w6vMmLIkHEsmjItAvpfnUhr2K7OpNzo/AmFstc Kqlx3NoO6zk72HTL1QDxglK7KcM/LuGEttejzT/4rlxjCFzv3Qkidh4vP W2P8V/GvbZu9gT727pNnUoc3++LNCiDd8cOyNEo5613OalS/yfywwjNkp TdTv63xJSfSQMi1hKsu4PgF6Ej6qHTKfJ+eSaRKGftlovYjCTrn99PZmX bCeGFPqQGzz0sCNcbJ0y7rx4QXfug+EIpqQXt6wVUsuJq/V3AevNvwaTi bryPSmE16uDE5rPHO+oGb59KcVQjkXaq+reqQK3hUJDJ61dQQC9Pmmy0G w==; X-IronPort-AV: E=McAfee;i="6600,9927,10961"; a="22965757" X-IronPort-AV: E=Sophos;i="6.05,214,1701158400"; d="scan'208";a="22965757" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2024 03:41:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,214,1701158400"; d="scan'208";a="27722314" Received: from silpixa00400957.ir.intel.com (HELO silpixa00401385.ir.intel.com) ([10.237.214.26]) by orviesa002.jf.intel.com with ESMTP; 23 Jan 2024 03:41:14 -0800 From: Bruce Richardson To: dev@dpdk.org Cc: Bruce Richardson , stable@dpdk.org Subject: [PATCH 1/6] net/i40e: remove incorrect 16B descriptor read block Date: Tue, 23 Jan 2024 11:40:48 +0000 Message-Id: <20240123114053.172189-2-bruce.richardson@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240123114053.172189-1-bruce.richardson@intel.com> References: <20240123114053.172189-1-bruce.richardson@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org By default, the driver works with 32B descriptors, but has a separate descriptor read block for reading two descriptors at a time when using 16B descriptors. However, the 32B reads used are not guaranteed to be atomic, which will cause issues if that is not the case on a system, since the descriptors may be read in an undefined order. Remove the block, to avoid issues, and just use the regular descriptor reading path for 16B descriptors, if that support is enabled at build time. Fixes: dafadd73762e ("net/i40e: add AVX2 Rx function") Cc: stable@dpdk.org Signed-off-by: Bruce Richardson --- drivers/net/i40e/i40e_rxtx_vec_avx2.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx_vec_avx2.c b/drivers/net/i40e/i40e_rxtx_vec_avx2.c index f468c1fd90..ce87e185f0 100644 --- a/drivers/net/i40e/i40e_rxtx_vec_avx2.c +++ b/drivers/net/i40e/i40e_rxtx_vec_avx2.c @@ -277,19 +277,6 @@ _recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, #endif __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7; -#ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC - /* for AVX we need alignment otherwise loads are not atomic */ - if (avx_aligned) { - /* load in descriptors, 2 at a time, in reverse order */ - raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6)); - rte_compiler_barrier(); - raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4)); - rte_compiler_barrier(); - raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2)); - rte_compiler_barrier(); - raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0)); - } else -#endif do { const __m128i raw_desc7 = _mm_load_si128((void *)(rxdp + 7)); rte_compiler_barrier();