From patchwork Wed Jan 3 08:11:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 135702 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D6C8143807; Wed, 3 Jan 2024 09:33:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A92E8402DD; Wed, 3 Jan 2024 09:33:00 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id CBF6C4013F for ; Wed, 3 Jan 2024 09:32:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704270779; x=1735806779; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=hgXe+Fy0KegLMycH+D+voaV13UYODjeKWJGMuXLA5c0=; b=haX8YcdkAxJMugcNWCyGsPXWgomnHaQ/IeEYkoo00yHsIpN/z/gGvMre Xo1xLz9sc8y/1vmzew8Cmj7UenAnVCrbj2LkXyhw5XTY2gs7vmGd/OpZl 0IQsZ8hklw6pgtJ7ZQZKeUSttQcbIQOvVDzkJg7IcqTJld94/1T2OaGsE +SIA5BoY0K3yGyXCizPyOqja7gCR0rmQrBXua5qeakpeHj+Ogg3g9GlEB M2njJBrYWPX2BS19vqfzmQOECjwwxg/fPTPgM3OLvDqeCUuDDm0j+EZMz INuC0Nf/3h2biFHD2PXcwHoP/uZmlyvonqyDQ2yIXirF4CI4PTRDFCMXU Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="483164377" X-IronPort-AV: E=Sophos;i="6.04,327,1695711600"; d="scan'208";a="483164377" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2024 00:32:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,327,1695711600"; d="scan'208";a="22029225" Received: from dpdk-qiming3.sh.intel.com ([10.67.110.238]) by fmviesa001.fm.intel.com with ESMTP; 03 Jan 2024 00:32:57 -0800 From: Qiming Yang To: dev@dpdk.org Cc: Qiming Yang Subject: [RFC] net/ice: add E830 support Date: Wed, 3 Jan 2024 08:11:30 +0000 Message-Id: <20240103081130.872611-1-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add E830 device ids. Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 33 ++++++++++++++++++++------- drivers/net/ice/base/ice_ddp.c | 6 +++++ drivers/net/ice/base/ice_ddp.h | 1 + drivers/net/ice/base/ice_devids.h | 8 +++++++ drivers/net/ice/base/ice_hw_autogen.h | 14 ++++++++++++ drivers/net/ice/base/ice_nvm.c | 15 +++++++----- drivers/net/ice/base/ice_type.h | 2 ++ drivers/net/ice/ice_ethdev.c | 4 ++++ 8 files changed, 69 insertions(+), 14 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 8867279c28..f161a365ee 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -177,6 +177,12 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw) case ICE_DEV_ID_E825C_SGMII: hw->mac_type = ICE_MAC_GENERIC_3K_E825; break; + case ICE_DEV_ID_E830_BACKPLANE: + case ICE_DEV_ID_E830_QSFP56: + case ICE_DEV_ID_E830_SFP: + case ICE_DEV_ID_E830_SFP_DD: + hw->mac_type = ICE_MAC_E830; + break; default: hw->mac_type = ICE_MAC_UNKNOWN; break; @@ -810,15 +816,26 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, */ #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX - /* Retrieve the transmit timer */ - val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); - tx_timer_val = val & - PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; - cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); + if ((hw)->mac_type == ICE_MAC_E830) { + /* Retrieve the transmit timer */ + val = rd32(hw, E830_PRTMAC_CL01_PAUSE_QUANTA); + tx_timer_val = val & E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M; + cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); - /* Retrieve the fc threshold */ - val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); - fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; + /* Retrieve the fc threshold */ + val = rd32(hw, E830_PRTMAC_CL01_QUANTA_THRESH); + fc_thres_val = val & E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M; + } else { + /* Retrieve the transmit timer */ + val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); + tx_timer_val = val & + PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; + cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); + + /* Retrieve the fc threshold */ + val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); + fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; + } cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val); } diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index ffcd5a9394..e43aab981d 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -439,6 +439,9 @@ static u32 ice_get_pkg_segment_id(enum ice_mac_type mac_type) u32 seg_id; switch (mac_type) { + case ICE_MAC_E830: + seg_id = SEGMENT_TYPE_ICE_E830; + break; case ICE_MAC_GENERIC: case ICE_MAC_GENERIC_3K: case ICE_MAC_GENERIC_3K_E825: @@ -459,6 +462,9 @@ static u32 ice_get_pkg_sign_type(enum ice_mac_type mac_type) u32 sign_type; switch (mac_type) { + case ICE_MAC_E830: + sign_type = SEGMENT_SIGN_TYPE_RSA3K_SBB; + break; case ICE_MAC_GENERIC_3K: sign_type = SEGMENT_SIGN_TYPE_RSA3K; break; diff --git a/drivers/net/ice/base/ice_ddp.h b/drivers/net/ice/base/ice_ddp.h index 1e02adf0db..6c87f11972 100644 --- a/drivers/net/ice/base/ice_ddp.h +++ b/drivers/net/ice/base/ice_ddp.h @@ -107,6 +107,7 @@ struct ice_generic_seg_hdr { #define SEGMENT_TYPE_METADATA 0x00000001 #define SEGMENT_TYPE_ICE_E810 0x00000010 #define SEGMENT_TYPE_SIGNING 0x00001001 +#define SEGMENT_TYPE_ICE_E830 0x00000017 #define SEGMENT_TYPE_ICE_RUN_TIME_CFG 0x00000020 __le32 seg_type; struct ice_pkg_ver seg_format_ver; diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h index 19478d2db1..3e0f9a16a3 100644 --- a/drivers/net/ice/base/ice_devids.h +++ b/drivers/net/ice/base/ice_devids.h @@ -15,6 +15,14 @@ #define ICE_DEV_ID_E823L_1GBE 0x124F /* Intel(R) Ethernet Connection E823-L for QSFP */ #define ICE_DEV_ID_E823L_QSFP 0x151D +/* Intel(R) Ethernet Controller E830-C for backplane */ +#define ICE_DEV_ID_E830_BACKPLANE 0x12D1 +/* Intel(R) Ethernet Controller E830-C for QSFP */ +#define ICE_DEV_ID_E830_QSFP56 0x12D2 +/* Intel(R) Ethernet Controller E830-C for SFP */ +#define ICE_DEV_ID_E830_SFP 0x12D3 +/* Intel(R) Ethernet Controller E830-C for SFP-DD */ +#define ICE_DEV_ID_E830_SFP_DD 0x12D4 /* Intel(R) Ethernet Controller E810-C for backplane */ #define ICE_DEV_ID_E810C_BACKPLANE 0x1591 /* Intel(R) Ethernet Controller E810-C for QSFP */ diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h index 4610cec6a7..62955e8f63 100644 --- a/drivers/net/ice/base/ice_hw_autogen.h +++ b/drivers/net/ice/base/ice_hw_autogen.h @@ -9458,5 +9458,19 @@ #define VFPE_WQEALLOC1_PEQPID_M MAKEMASK(0x3FFFF, 0) #define VFPE_WQEALLOC1_WQE_DESC_INDEX_S 20 #define VFPE_WQEALLOC1_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20) +/* E830 related */ +#define E830_GL_HICR_EN 0x00082044 /* Reset Source: EMPR */ +#define E830_GL_HICR_EN_EN_S 0 +#define E830_GL_HICR_EN_EN_M BIT(0) +#define E830_PRTMAC_CL01_PAUSE_QUANTA 0x001E32A0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_S 0 +#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_S 16 +#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_CL01_QUANTA_THRESH 0x001E3320 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_S 0 +#define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_S 16 +#define E830_PRTMAC_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) #endif /* !_ICE_HW_AUTOGEN_H_ */ diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index e46aded12a..983a91a148 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -1354,14 +1354,17 @@ ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd, return status; /* Reject requests to write to read-only registers */ - switch (cmd->offset) { - case GL_HICR_EN: - case GLGEN_RSTAT: - return ICE_ERR_OUT_OF_RANGE; - default: - break; + if (hw->mac_type == ICE_MAC_E830) { + if (cmd->offset == E830_GL_HICR_EN) + return ICE_ERR_OUT_OF_RANGE; + } else { + if (cmd->offset == GL_HICR_EN) + return ICE_ERR_OUT_OF_RANGE; } + if (cmd->offset == GLGEN_RSTAT) + return ICE_ERR_OUT_OF_RANGE; + ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n", cmd->offset, data->regval); diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index d13105070b..683f3ea0ae 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -204,6 +204,7 @@ enum ice_set_fc_aq_failures { enum ice_mac_type { ICE_MAC_UNKNOWN = 0, ICE_MAC_E810, + ICE_MAC_E830, ICE_MAC_GENERIC, ICE_MAC_GENERIC_3K, ICE_MAC_GENERIC_3K_E825, @@ -1132,6 +1133,7 @@ struct ice_switch_info { enum ice_phy_cfg { ICE_PHY_E810 = 1, ICE_PHY_E822, + ICE_PHY_E830, ICE_PHY_ETH56G, }; diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 3ccba4db80..0445b9bd6b 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -213,6 +213,10 @@ static const struct rte_pci_id pci_id_ice_map[] = { { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_SFP) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C825X) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_SGMII) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_BACKPLANE) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_QSFP56) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_SFP) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_SFP_DD) }, { .vendor_id = 0, /* sentinel */ }, };