From: Rahul Bhansali <rbhansali@marvell.com>
Add Rx inject config for feature enable/disable, and store
Rx chan value per port.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/common/cnxk/roc_idev.c | 44 +++++++++++++++++++++++++++++
drivers/common/cnxk/roc_idev.h | 5 ++++
drivers/common/cnxk/roc_idev_priv.h | 6 ++++
drivers/common/cnxk/roc_nix.c | 2 ++
drivers/common/cnxk/version.map | 4 +++
5 files changed, 61 insertions(+)
@@ -310,3 +310,47 @@ roc_idev_nix_inl_meta_aura_get(void)
return idev->inl_cfg.meta_aura;
return 0;
}
+
+uint8_t
+roc_idev_nix_rx_inject_get(uint16_t port)
+{
+ struct idev_cfg *idev;
+
+ idev = idev_get_cfg();
+ if (idev != NULL && port < PLT_MAX_ETHPORTS)
+ return idev->inl_rx_inj_cfg.rx_inject_en[port];
+
+ return 0;
+}
+
+void
+roc_idev_nix_rx_inject_set(uint16_t port, uint8_t enable)
+{
+ struct idev_cfg *idev;
+
+ idev = idev_get_cfg();
+ if (idev != NULL && port < PLT_MAX_ETHPORTS)
+ __atomic_store_n(&idev->inl_rx_inj_cfg.rx_inject_en[port], enable,
+ __ATOMIC_RELEASE);
+}
+
+uint16_t *
+roc_idev_nix_rx_chan_base_get(void)
+{
+ struct idev_cfg *idev = idev_get_cfg();
+
+ if (idev != NULL)
+ return (uint16_t *)&idev->inl_rx_inj_cfg.chan;
+
+ return NULL;
+}
+
+void
+roc_idev_nix_rx_chan_set(uint16_t port, uint16_t chan)
+{
+ struct idev_cfg *idev;
+
+ idev = idev_get_cfg();
+ if (idev != NULL && port < PLT_MAX_ETHPORTS)
+ __atomic_store_n(&idev->inl_rx_inj_cfg.chan[port], chan, __ATOMIC_RELEASE);
+}
@@ -22,4 +22,9 @@ struct roc_nix_list *__roc_api roc_idev_nix_list_get(void);
struct roc_mcs *__roc_api roc_idev_mcs_get(uint8_t mcs_idx);
void __roc_api roc_idev_mcs_set(struct roc_mcs *mcs);
void __roc_api roc_idev_mcs_free(struct roc_mcs *mcs);
+
+uint8_t __roc_api roc_idev_nix_rx_inject_get(uint16_t port);
+void __roc_api roc_idev_nix_rx_inject_set(uint16_t port, uint8_t enable);
+uint16_t *__roc_api roc_idev_nix_rx_chan_base_get(void);
+void __roc_api roc_idev_nix_rx_chan_set(uint16_t port, uint16_t chan);
#endif /* _ROC_IDEV_H_ */
@@ -19,6 +19,11 @@ struct idev_nix_inl_cfg {
uint32_t refs;
};
+struct idev_nix_inl_rx_inj_cfg {
+ uint16_t chan[PLT_MAX_ETHPORTS];
+ uint8_t rx_inject_en[PLT_MAX_ETHPORTS];
+};
+
struct idev_cfg {
uint16_t sso_pf_func;
uint16_t npa_pf_func;
@@ -35,6 +40,7 @@ struct idev_cfg {
struct nix_inl_dev *nix_inl_dev;
struct idev_nix_inl_cfg inl_cfg;
struct roc_nix_list roc_nix_list;
+ struct idev_nix_inl_rx_inj_cfg inl_rx_inj_cfg;
plt_spinlock_t nix_inl_dev_lock;
plt_spinlock_t npa_dev_lock;
};
@@ -223,6 +223,8 @@ roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq,
nix->nb_rx_queues = nb_rxq;
nix->nb_tx_queues = nb_txq;
+ roc_idev_nix_rx_chan_set(roc_nix->port_id, rsp->rx_chan_base);
+
nix->rqs = plt_zmalloc(sizeof(struct roc_nix_rq *) * nb_rxq, 0);
if (!nix->rqs) {
rc = -ENOMEM;
@@ -105,6 +105,10 @@ INTERNAL {
roc_idev_num_lmtlines_get;
roc_idev_nix_inl_meta_aura_get;
roc_idev_nix_list_get;
+ roc_idev_nix_rx_chan_base_get;
+ roc_idev_nix_rx_chan_set;
+ roc_idev_nix_rx_inject_get;
+ roc_idev_nix_rx_inject_set;
roc_ml_reg_read64;
roc_ml_reg_write64;
roc_ml_reg_read32;