From patchwork Wed Dec 27 04:21:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 135599 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06A72437A1; Wed, 27 Dec 2023 05:22:58 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ABC7440A87; Wed, 27 Dec 2023 05:21:46 +0100 (CET) Received: from mail-qt1-f179.google.com (mail-qt1-f179.google.com [209.85.160.179]) by mails.dpdk.org (Postfix) with ESMTP id 9976440A6E for ; Wed, 27 Dec 2023 05:21:41 +0100 (CET) Received: by mail-qt1-f179.google.com with SMTP id d75a77b69052e-427dcdebf8fso13378121cf.3 for ; Tue, 26 Dec 2023 20:21:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1703650900; x=1704255700; darn=dpdk.org; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date:message-id:reply-to; bh=fKduRJ+63AKztDn0E0Gtb9a/gMqpGKON5T+kWQQQVRY=; b=P5a2OkqsGUFEttFFfWsntKZB2X1GXGfEkv2X7mHhMMGw3pHjg7vruXQ5WQnjhgKXNi MMRvIZdy7rfqreAMjTpx981L+7FUOtXw0M4kGdtW1qJE0Qt/iC7YILoeg7UoyiMnV1YC cdXF/MGNpvTsCLAhM4Dtyp/uc4w6ZPC2/P9xY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703650900; x=1704255700; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=fKduRJ+63AKztDn0E0Gtb9a/gMqpGKON5T+kWQQQVRY=; b=HpH2/xI8uyo/mRJUTrUiYdaOZbx5wkh8BsvZOdoAtn8Qv+Ac/PuIQwI75y3+dItAUB 9f3u5rexxfZRXgK5ow8fsw70u+ijj5sHAgB7NXrB5yC1Q3APN43Rlr4IFBh22cqUPfMy EJZDDjBnm9+aQGKXIt9tlgzhS6G6lOOrF3ocsw0k/sCQqiOuBhpNUzcjqdSJCYaFSIQ7 4xz7+MVUPe0N1YcKl24vhYWBQIe35fnz95jvO03SdhfhfX4CXoMrPV2UCV0DLgIYh2Tl QkM9BnFnU6H/sVOo7Zc+9tiD4OIcklXrbfh4R4qprZFXcuLisOTBx4CfFjOLlsyXHJG5 FDlg== X-Gm-Message-State: AOJu0YyORnu6BTQvTSwLABCD9NzfHDnXbXKFTgQdgJSZiNn6HzR4p09t VtLO9HCYhhixETl5VKsekGKC6jsiJaHPk7/6GhzEfc2wXSM5sxcNmAOl1WyltBBtRD+Czc3vB6f D45K8xsjtQgJIW7O9kWIbq9a8Vc0uT3mn3Kq2VuPT7hAJ4/LgDC9W2N2XxfYxv0pu5fFvD9aYUG E= X-Google-Smtp-Source: AGHT+IG8lZ+Qo2alCOw5xZB74oL9b+3RRW/qu4qWkSsUSQ1Kt3AIlwurYMRA76kPSz77aLXt5FCvaA== X-Received: by 2002:a05:622a:15c5:b0:425:4043:419e with SMTP id d5-20020a05622a15c500b004254043419emr11589883qty.74.1703650900415; Tue, 26 Dec 2023 20:21:40 -0800 (PST) Received: from localhost.localdomain ([2605:a601:a780:1400:c066:75e3:74c8:50e6]) by smtp.gmail.com with ESMTPSA id bt7-20020ac86907000000b00427e120889bsm1415488qtb.91.2023.12.26.20.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 20:21:39 -0800 (PST) From: Ajit Khaparde To: dev@dpdk.org Cc: Damodharam Ammepalli Subject: [PATCH v3 11/18] net/bnxt: add ESP and AH header based RSS support Date: Tue, 26 Dec 2023 20:21:12 -0800 Message-Id: <20231227042119.72469-12-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20231227042119.72469-1-ajit.khaparde@broadcom.com> References: <20231227042119.72469-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Check if the firmware can support RSS based on these types and program the hardware accordingly when requested when the firmware indicates that the underlying hardware supports the functionality. Signed-off-by: Ajit Khaparde Reviewed-by: Damodharam Ammepalli --- drivers/net/bnxt/bnxt.h | 6 ++ drivers/net/bnxt/bnxt_ethdev.c | 8 ++- drivers/net/bnxt/bnxt_hwrm.c | 104 +++++++++++++++++++++++++-------- drivers/net/bnxt/bnxt_hwrm.h | 1 + drivers/net/bnxt/bnxt_vnic.c | 13 ++++- 5 files changed, 102 insertions(+), 30 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index e7b288c849..576688bbff 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -809,6 +809,12 @@ struct bnxt { #define BNXT_VNIC_CAP_XOR_MODE BIT(5) #define BNXT_VNIC_CAP_CHKSM_MODE BIT(6) #define BNXT_VNIC_CAP_L2_CQE_MODE BIT(8) +#define BNXT_VNIC_CAP_AH_SPI4_CAP BIT(9) +#define BNXT_VNIC_CAP_AH_SPI6_CAP BIT(10) +#define BNXT_VNIC_CAP_ESP_SPI4_CAP BIT(11) +#define BNXT_VNIC_CAP_ESP_SPI6_CAP BIT(12) +#define BNXT_VNIC_CAP_AH_SPI_CAP (BNXT_VNIC_CAP_AH_SPI4_CAP | BNXT_VNIC_CAP_AH_SPI6_CAP) +#define BNXT_VNIC_CAP_ESP_SPI_CAP (BNXT_VNIC_CAP_ESP_SPI4_CAP | BNXT_VNIC_CAP_ESP_SPI6_CAP) unsigned int rx_nr_rings; unsigned int rx_cp_nr_rings; diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index ef5e65ff16..5b775e7716 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -995,8 +995,12 @@ uint64_t bnxt_eth_rss_support(struct bnxt *bp) RTE_ETH_RSS_LEVEL_MASK; if (bp->vnic_cap_flags & BNXT_VNIC_CAP_CHKSM_MODE) - support |= (RTE_ETH_RSS_IPV4_CHKSUM | - RTE_ETH_RSS_L4_CHKSUM); + support |= RTE_ETH_RSS_IPV4_CHKSUM | + RTE_ETH_RSS_L4_CHKSUM; + if (bp->vnic_cap_flags & BNXT_VNIC_CAP_AH_SPI_CAP) + support |= RTE_ETH_RSS_AH; + if (bp->vnic_cap_flags & BNXT_VNIC_CAP_ESP_SPI_CAP) + support |= RTE_ETH_RSS_ESP; return support; } diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 587433a878..1ac3f30074 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -1031,6 +1031,21 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP) bp->vnic_cap_flags |= BNXT_VNIC_CAP_CHKSM_MODE; + if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP) + bp->vnic_cap_flags |= BNXT_VNIC_CAP_L2_CQE_MODE; + + if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP) + bp->vnic_cap_flags |= BNXT_VNIC_CAP_AH_SPI4_CAP; + + if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP) + bp->vnic_cap_flags |= BNXT_VNIC_CAP_AH_SPI6_CAP; + + if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP) + bp->vnic_cap_flags |= BNXT_VNIC_CAP_ESP_SPI4_CAP; + + if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP) + bp->vnic_cap_flags |= BNXT_VNIC_CAP_ESP_SPI6_CAP; + bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported); HWRM_UNLOCK(); @@ -2412,6 +2427,52 @@ int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic) return rc; } +static uint32_t bnxt_sanitize_rss_type(struct bnxt *bp, uint32_t types) +{ + uint32_t hwrm_type = types; + + if (types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 && + !(bp->vnic_cap_flags & BNXT_VNIC_CAP_ESP_SPI4_CAP)) + hwrm_type &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4; + if (types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6 && + !(bp->vnic_cap_flags & BNXT_VNIC_CAP_ESP_SPI6_CAP)) + hwrm_type &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6; + + if (types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 && + !(bp->vnic_cap_flags & BNXT_VNIC_CAP_AH_SPI4_CAP)) + hwrm_type &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4; + + if (types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6 && + !(bp->vnic_cap_flags & BNXT_VNIC_CAP_AH_SPI6_CAP)) + hwrm_type &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6; + + return hwrm_type; +} + +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +static int +bnxt_hwrm_vnic_rss_qcfg_p5(struct bnxt *bp) +{ + struct hwrm_vnic_rss_qcfg_output *resp = bp->hwrm_cmd_resp_addr; + struct hwrm_vnic_rss_qcfg_input req = {0}; + int rc; + + HWRM_PREP(&req, HWRM_VNIC_RSS_QCFG, BNXT_USE_CHIMP_MB); + /* vnic_id and rss_ctx_idx must be set to INVALID to read the + * global hash mode. + */ + req.vnic_id = rte_cpu_to_le_16(BNXT_DFLT_VNIC_ID_INVALID); + req.rss_ctx_idx = rte_cpu_to_le_16(BNXT_RSS_CTX_IDX_INVALID); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), + BNXT_USE_CHIMP_MB); + HWRM_CHECK_RESULT(); + HWRM_UNLOCK(); + PMD_DRV_LOG(DEBUG, "RSS QCFG: Hash level %d\n", resp->hash_mode_flags); + + return rc; +} +#endif + static int bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) { @@ -2425,7 +2486,10 @@ bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB); req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id); - req.hash_type = rte_cpu_to_le_32(vnic->hash_type); + req.hash_type = rte_cpu_to_le_32(bnxt_sanitize_rss_type(bp, vnic->hash_type)); + /* Update req with vnic ring_select_mode for P7 */ + if (BNXT_CHIP_P7(bp)) + req.ring_select_mode = vnic->ring_select_mode; /* When the vnic_id in the request field is a valid * one, the hash_mode_flags in the request field must * be set to DEFAULT. And any request to change the @@ -2524,7 +2588,7 @@ bnxt_hwrm_vnic_rss_cfg_non_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB); - req.hash_type = rte_cpu_to_le_32(vnic->hash_type); + req.hash_type = rte_cpu_to_le_32(bnxt_sanitize_rss_type(bp, vnic->hash_type)); req.hash_mode_flags = vnic->hash_mode; req.ring_grp_tbl_addr = @@ -2550,29 +2614,18 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp, if (!vnic->rss_table) return 0; - if (BNXT_CHIP_P5(bp)) { - rc = bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic); - if (rc) - return rc; - /* Configuring the hash mode has to be done in a - * different VNIC_RSS_CFG HWRM command by setting - * vnic_id & rss_ctx_id to INVALID. The only - * exception to this is if the USER doesn't want - * to change the default behavior. So, ideally - * bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 should be - * called when user is explicitly changing the hash - * mode. However, this logic will unconditionally - * call bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 to - * simplify the logic as there is no harm in calling - * bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 even when - * user is not setting it explicitly. Because, this - * routine will convert the default value to inner - * which is our adapter's default behavior. - */ + /* Handle all the non-thor skus rss here */ + if (!BNXT_CHIP_P5_P7(bp)) + return bnxt_hwrm_vnic_rss_cfg_non_p5(bp, vnic); + + /* Handle Thor2 and Thor skus rss here */ + rc = bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic); + + /* configure hash mode for Thor/Thor2 */ + if (!rc) return bnxt_hwrm_vnic_rss_cfg_hash_mode_p5(bp, vnic); - } - return bnxt_hwrm_vnic_rss_cfg_non_p5(bp, vnic); + return rc; } int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp, @@ -5343,7 +5396,7 @@ int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp, return 0; } -static int +int bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) { struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr; @@ -5363,8 +5416,9 @@ bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB); req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id); - req.hash_type = rte_cpu_to_le_32(vnic->hash_type); + req.hash_type = rte_cpu_to_le_32(bnxt_sanitize_rss_type(bp, vnic->hash_type)); req.hash_mode_flags = vnic->hash_mode; + req.ring_select_mode = vnic->ring_select_mode; req.ring_grp_tbl_addr = rte_cpu_to_le_64(vnic->rss_table_dma_addr + diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index 3d5194257b..56b232d7de 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -357,6 +357,7 @@ void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index); int bnxt_alloc_hwrm_tx_ring(struct bnxt *bp, int queue_index); int bnxt_hwrm_config_host_mtu(struct bnxt *bp); int bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic); +int bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic); int bnxt_hwrm_func_backing_store_qcaps_v2(struct bnxt *bp); int bnxt_hwrm_func_backing_store_cfg_v2(struct bnxt *bp, struct bnxt_ctx_mem *ctxm); diff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c index bf1f0ea09f..5ea34f7cb6 100644 --- a/drivers/net/bnxt/bnxt_vnic.c +++ b/drivers/net/bnxt/bnxt_vnic.c @@ -268,6 +268,8 @@ uint32_t bnxt_rte_to_hwrm_hash_types(uint64_t rte_type) if ((rte_type & RTE_ETH_RSS_IPV4) || (rte_type & RTE_ETH_RSS_ECPRI)) hwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; + if (rte_type & RTE_ETH_RSS_ECPRI) + hwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; if (rte_type & RTE_ETH_RSS_NONFRAG_IPV4_TCP) hwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; if (rte_type & RTE_ETH_RSS_NONFRAG_IPV4_UDP) @@ -278,9 +280,12 @@ uint32_t bnxt_rte_to_hwrm_hash_types(uint64_t rte_type) hwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; if (rte_type & RTE_ETH_RSS_NONFRAG_IPV6_UDP) hwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; - if (rte_type & RTE_ETH_RSS_IPV4_CHKSUM) - hwrm_type |= - HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM; + if (rte_type & RTE_ETH_RSS_ESP) + hwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 | + HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6; + if (rte_type & RTE_ETH_RSS_AH) + hwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 | + HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6; return hwrm_type; } @@ -1327,7 +1332,9 @@ int bnxt_rte_flow_to_hwrm_ring_select_mode(enum rte_eth_hash_function hash_f, /* Checksum mode cannot with hash func makes no sense */ vnic->ring_select_mode = HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM; + vnic->hash_f_local = RTE_ETH_HASH_FUNCTION_TOEPLITZ; /* shadow copy types as !hash_f is always true with default func */ + vnic->rss_types_local = types; return 0; } PMD_DRV_LOG(ERR, "Hash function not supported with checksun type\n");