From patchwork Mon Dec 11 13:23:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 135021 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 60DA6436C8; Mon, 11 Dec 2023 14:23:37 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D5341427E1; Mon, 11 Dec 2023 14:23:34 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 6CA9142830 for ; Mon, 11 Dec 2023 14:23:32 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BB9IIpi009915 for ; Mon, 11 Dec 2023 05:23:31 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=1Uxf8D9w7xNt4NUS6nPnrI7HfM8OEnWIiT+rLRGfaBQ=; b=S0v i1OK12JQXgo8ZGVKaWnExI8KI6+blVl6zJ3WiqxGN4/N2HNWySuJ1v2FEztkxiVG XoPE0qnB7qMSKj7C4FeRw1XZp9MPpKxdjn1lMBflbHjsdGIWQ7zY2gsiVH8Jh0W5 AZaT5msATPO731OBhVGunTZLEEDvRUS//AwHy59rk6Cwxe4icB8+DGLxqfvLARy6 DxB8L9JuBtnVnH4VuXGVJFEFumdVSmYcmjnmzk586mC8ugVwbW7ZvWUuMabVGUgZ tBRBug7toWQZ3eWYX+HDXz0r3Eii06cy33DhLuyte/zHzd32mxyXOwznfGMjM8Ee DhAnBjKXfjkRuO1jYvg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3uwyp4gqpd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 11 Dec 2023 05:23:31 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 11 Dec 2023 05:23:29 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 11 Dec 2023 05:23:29 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id D40983F7096; Mon, 11 Dec 2023 05:23:26 -0800 (PST) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh Subject: [PATCH v2 2/3] common/cnxk: update scheduler base code Date: Mon, 11 Dec 2023 18:53:19 +0530 Message-ID: <20231211132320.1254-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211132320.1254-1-pbhagavatula@marvell.com> References: <20231207065630.4009-1-pbhagavatula@marvell.com> <20231211132320.1254-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: r6TwC1fvcHolyQ4UcbEHfGi8Pzt2CwDf X-Proofpoint-GUID: r6TwC1fvcHolyQ4UcbEHfGi8Pzt2CwDf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Update event scheduler base code. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/hw/ssow.h | 4 ++++ drivers/common/cnxk/roc_sso.c | 34 +++++++++++++++++++++++----------- drivers/common/cnxk/roc_sso.h | 2 +- 3 files changed, 28 insertions(+), 12 deletions(-) diff --git a/drivers/common/cnxk/hw/ssow.h b/drivers/common/cnxk/hw/ssow.h index 618ab7973b..c146a8c3ef 100644 --- a/drivers/common/cnxk/hw/ssow.h +++ b/drivers/common/cnxk/hw/ssow.h @@ -54,6 +54,8 @@ #define SSOW_LF_GWS_OP_SWTAG_FULL1 (0xc28ull) #define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull) +#define SSOW_LF_GWS_MAX_NW_TIM_US (0x400) /* [CN9K, CN10K) */ + /* Enum offsets */ #define SSOW_LF_INT_VEC_IOP (0x0ull) @@ -65,6 +67,8 @@ #define SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT 63 #define SSOW_LF_GWS_TAG_PEND_SWITCH_BIT 62 #define SSOW_LF_GWS_TAG_PEND_DESCHED_BIT 58 +#define SSOW_LF_GWS_TAG_PEND_FLUSH 56 +#define SSOW_LF_GWS_TAG_PEND_SWUNT 54 #define SSOW_LF_GWS_TAG_HEAD_BIT 35 #endif /* __SSOW_HW_H__ */ diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index f09b535c80..e5c16b2a05 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -17,6 +17,11 @@ sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf, struct mbox *mbox = mbox_get(dev->mbox); int rc = -ENOSPC; + if (!nb_lf) { + mbox_put(mbox); + return 0; + } + switch (lf_type) { case SSO_LF_TYPE_HWS: { struct ssow_lf_alloc_req *req; @@ -56,6 +61,11 @@ sso_lf_free(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf) struct mbox *mbox = mbox_get(dev->mbox); int rc = -ENOSPC; + if (!nb_lf) { + mbox_put(mbox); + return 0; + } + switch (lf_type) { case SSO_LF_TYPE_HWS: { struct ssow_lf_free_req *req; @@ -98,6 +108,11 @@ sso_rsrc_attach(struct roc_sso *roc_sso, enum sso_lf_type lf_type, struct rsrc_attach_req *req; int rc = -ENOSPC; + if (!nb_lf) { + mbox_put(mbox); + return 0; + } + req = mbox_alloc_msg_attach_resources(mbox); if (req == NULL) goto exit; @@ -264,13 +279,10 @@ roc_sso_hwgrp_base_get(struct roc_sso *roc_sso, uint16_t hwgrp) } uint64_t -roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns) +roc_sso_ns_to_gw(uint64_t base, uint64_t ns) { - struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; - uint64_t current_us, current_ns, new_ns; - uintptr_t base; + uint64_t current_us; - base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20); current_us = plt_read64(base + SSOW_LF_GWS_NW_TIM); /* From HRM, table 14-19: * The SSOW_LF_GWS_NW_TIM[NW_TIM] period is specified in n-1 notation. @@ -279,14 +291,11 @@ roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns) /* From HRM, table 14-1: * SSOW_LF_GWS_NW_TIM[NW_TIM] specifies the minimum timeout. The SSO - * hardware times out a GET_WORK request within 2 usec of the minimum + * hardware times out a GET_WORK request within 1 usec of the minimum * timeout specified by SSOW_LF_GWS_NW_TIM[NW_TIM]. */ - current_us += 2; - current_ns = current_us * 1E3; - new_ns = (ns - PLT_MIN(ns, current_ns)); - new_ns = !new_ns ? 1 : new_ns; - return (new_ns * plt_tsc_hz()) / 1E9; + current_us += 1; + return PLT_MAX(1UL, (uint64_t)PLT_DIV_CEIL(ns, (current_us * 1E3))); } int @@ -705,6 +714,9 @@ roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps) struct dev *dev = &sso->dev; int rc; + if (!hwgrps) + return 0; + rc = sso_hwgrp_release_xaq(dev, hwgrps); return rc; } diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index 64f14b8119..26061f25f8 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -83,7 +83,7 @@ int __roc_api roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, int __roc_api roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, uint16_t hwgrp, uint8_t weight, uint8_t affinity, uint8_t priority); -uint64_t __roc_api roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns); +uint64_t __roc_api roc_sso_ns_to_gw(uint64_t base, uint64_t ns); int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], uint16_t nb_hwgrp, uint8_t set); int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],