From patchwork Mon Dec 11 13:23:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 135020 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 646A8436C8; Mon, 11 Dec 2023 14:23:30 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 51AEA40608; Mon, 11 Dec 2023 14:23:30 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3EC5940289 for ; Mon, 11 Dec 2023 14:23:29 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BAMrKxp012215 for ; Mon, 11 Dec 2023 05:23:28 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=9I4YeoJhir77Mpx1mo5XF4rSktmMsocP8m3tZsmnySE=; b=dW7 bsaFAHugoqjt52MWztChiKzFrUO1FwkoEFYPY6DNI9m+qaRTMGfCAymkbg23dK4u wYLhYATiuYy8rhQTBGn3SJhH7fw3aYZ89pdMCayXInZJdJ9YqyIqkrvu1M4C7MDU f+i/2S5o5UiyVsIXtc3eUFxjjJiKwAQmf/BE9UoOkm+sax1M/4kP8/NzH1XHoa43 wv0isIaNR83mx3/ycoJVXZjS0BWfh0lBWXaq5hdaxqZipWmuMIjJR36hCGYkvVqv h3tK8eGXO1BDAAj2JKKn7tBUar4dD4e0io5aWJcbdgA6CcPZUwCnjv4QFZ+lk9+7 5Vk1S5CHHqG7jhRZ5vw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3uvrmjmm81-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 11 Dec 2023 05:23:28 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 11 Dec 2023 05:23:26 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 11 Dec 2023 05:23:26 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id D2A683F7068; Mon, 11 Dec 2023 05:23:22 -0800 (PST) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh Subject: [PATCH v2 1/3] common/cnxk: update timer base code Date: Mon, 11 Dec 2023 18:53:18 +0530 Message-ID: <20231211132320.1254-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231207065630.4009-1-pbhagavatula@marvell.com> References: <20231207065630.4009-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: iq3-cV9yWmXjMt_q_0jKjXokJgvtwk9Y X-Proofpoint-ORIG-GUID: iq3-cV9yWmXjMt_q_0jKjXokJgvtwk9Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Update event timer base code. Signed-off-by: Pavan Nikhilesh --- v2 Changes: - Split patches. drivers/common/cnxk/hw/tim.h | 5 +++-- drivers/common/cnxk/roc_mbox.h | 11 +++++++++++ drivers/common/cnxk/roc_sso.c | 2 +- drivers/common/cnxk/roc_tim.c | 27 ++++++++++++++++++++++++++- drivers/common/cnxk/roc_tim.h | 3 +++ 5 files changed, 44 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/drivers/common/cnxk/hw/tim.h b/drivers/common/cnxk/hw/tim.h index 61c38ae175..82b094e3dc 100644 --- a/drivers/common/cnxk/hw/tim.h +++ b/drivers/common/cnxk/hw/tim.h @@ -49,7 +49,8 @@ #define TIM_LF_RING_REL (0x400) #define TIM_MAX_INTERVAL_TICKS ((1ULL << 32) - 1) -#define TIM_MAX_BUCKET_SIZE ((1ULL << 20) - 1) -#define TIM_MIN_BUCKET_SIZE 3 +#define TIM_MAX_BUCKET_SIZE ((1ULL << 20) - 2) +#define TIM_MIN_BUCKET_SIZE 1 +#define TIM_BUCKET_WRAP_SIZE 3 #endif /* __TIM_HW_H__ */ diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 05434aec5a..4590e5f2dd 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -154,6 +154,8 @@ struct mbox_msghdr { M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \ M(TIM_GET_MIN_INTVL, 0x805, tim_get_min_intvl, tim_intvl_req, \ tim_intvl_rsp) \ + M(TIM_CAPTURE_COUNTERS, 0x806, tim_capture_counters, msg_req, \ + tim_capture_rsp) \ /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, msg_rsp) \ M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ @@ -2541,6 +2543,10 @@ enum tim_clk_srcs { TIM_CLK_SRCS_GPIO = 1, TIM_CLK_SRCS_GTI = 2, TIM_CLK_SRCS_PTP = 3, + TIM_CLK_SRCS_SYNCE = 4, + TIM_CLK_SRCS_BTS = 5, + TIM_CLK_SRCS_EXT_MIO = 6, + TIM_CLK_SRCS_EXT_GTI = 7, TIM_CLK_SRSC_INVALID, }; @@ -2652,6 +2658,11 @@ struct tim_intvl_rsp { uint64_t __io intvl_ns; }; +struct tim_capture_rsp { + struct mbox_msghdr hdr; + uint64_t __io counters[TIM_CLK_SRSC_INVALID]; +}; + struct sdp_node_info { /* Node to which this PF belons to */ uint8_t __io node_id; diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 748d287bad..f09b535c80 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -891,7 +891,7 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp, ui goto sso_msix_fail; } - nb_tim_lfs = nb_tim_lfs ? PLT_MIN(nb_tim_lfs, free_tim_lfs) : free_tim_lfs; + nb_tim_lfs = PLT_MIN(nb_tim_lfs, free_tim_lfs); } /* 2 error interrupt per TIM LF */ diff --git a/drivers/common/cnxk/roc_tim.c b/drivers/common/cnxk/roc_tim.c index f8607b2852..095afbb9e6 100644 --- a/drivers/common/cnxk/roc_tim.c +++ b/drivers/common/cnxk/roc_tim.c @@ -91,6 +91,31 @@ tim_err_desc(int rc) } } +int +roc_tim_capture_counters(struct roc_tim *roc_tim, uint64_t *counters, uint8_t nb_cntrs) +{ + struct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso); + struct dev *dev = &sso->dev; + struct mbox *mbox = mbox_get(dev->mbox); + struct tim_capture_rsp *rsp; + int rc, i; + + mbox_alloc_msg_tim_capture_counters(mbox); + rc = mbox_process_msg(dev->mbox, (void **)&rsp); + if (rc) { + tim_err_desc(rc); + rc = -EIO; + goto fail; + } + + for (i = 0; i < nb_cntrs; i++) + counters[i] = rsp->counters[i]; + +fail: + mbox_put(mbox); + return rc; +} + int roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *start_tsc, uint32_t *cur_bkt) @@ -138,7 +163,7 @@ roc_tim_lf_disable(struct roc_tim *roc_tim, uint8_t ring_id) goto fail; req->ring = ring_id; - rc = mbox_process(dev->mbox); + rc = mbox_process(mbox); if (rc) { tim_err_desc(rc); rc = -EIO; diff --git a/drivers/common/cnxk/roc_tim.h b/drivers/common/cnxk/roc_tim.h index 7dc9ae0a61..f9a9ad1887 100644 --- a/drivers/common/cnxk/roc_tim.h +++ b/drivers/common/cnxk/roc_tim.h @@ -14,6 +14,8 @@ enum roc_tim_clk_src { ROC_TIM_CLK_SRC_PTP, ROC_TIM_CLK_SRC_SYNCE, ROC_TIM_CLK_SRC_BTS, + ROC_TIM_CLK_SRC_EXT_MIO, + ROC_TIM_CLK_SRC_EXT_GTI, ROC_TIM_CLK_SRC_INVALID, }; @@ -48,5 +50,6 @@ int __roc_api roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, int __roc_api roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id); uintptr_t __roc_api roc_tim_lf_base_get(struct roc_tim *roc_tim, uint8_t ring_id); +int roc_tim_capture_counters(struct roc_tim *roc_tim, uint64_t *counters, uint8_t nb_cntrs); #endif