diff mbox series

ixgbe: fix interrupt clear mask for eimc register

Message ID 20231208154410.14212-1-simon.ellmann@tum.de (mailing list archive)
State Not Applicable, archived
Delegated to: Qi Zhang
Headers
Series ixgbe: fix interrupt clear mask for eimc register |

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Commit Message

Simon Ellmann Dec. 8, 2023, 3:44 p.m. UTC 
  32nd bit of the eimc register is reserved according to the datasheet

Signed-off-by: Simon Ellmann <simon.ellmann@tum.de>
---
 drivers/net/ixgbe/base/ixgbe_type.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Qi Zhang Dec. 14, 2023, 2:24 a.m. UTC | #1 
> -----Original Message-----
> From: Simon Ellmann <simon.ellmann@tum.de>
> Sent: Friday, December 8, 2023 11:44 PM
> To: Yang, Qiming <qiming.yang@intel.com>; Wu, Wenjun1
> <wenjun1.wu@intel.com>
> Cc: dev@dpdk.org; Simon Ellmann <simon.ellmann@tum.de>
> Subject: [PATCH] ixgbe: fix interrupt clear mask for eimc register
> 
> 32nd bit of the eimc register is reserved according to the datasheet
> 
> Signed-off-by: Simon Ellmann <simon.ellmann@tum.de>
> ---
>  drivers/net/ixgbe/base/ixgbe_type.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ixgbe/base/ixgbe_type.h
> b/drivers/net/ixgbe/base/ixgbe_type.h
> index 1094df5891..03b299cd10 100644
> --- a/drivers/net/ixgbe/base/ixgbe_type.h
> +++ b/drivers/net/ixgbe/base/ixgbe_type.h
> @@ -2023,7 +2023,7 @@ enum {
>  #define IXGBE_FTQF_QUEUE_ENABLE		0x80000000
> 
>  /* Interrupt clear mask */
> -#define IXGBE_IRQ_CLEAR_MASK	0xFFFFFFFF
> +#define IXGBE_IRQ_CLEAR_MASK	0x7FFFFFFF

If it is not harmful, I will prefer to keep the base code aligned with kernel driver's implementation which is 0xFFFFFFFF currently.
> 
>  /* Interrupt Vector Allocation Registers */
>  #define IXGBE_IVAR_REG_NUM		25
> --
> 2.43.0
Simon Ellmann Dec. 14, 2023, 11:02 a.m. UTC | #2 
> On 14. Dec 2023, at 03:24, Zhang, Qi Z <qi.z.zhang@intel.com> wrote:
>> -----Original Message-----
>> From: Simon Ellmann <simon.ellmann@tum.de>
>> Sent: Friday, December 8, 2023 11:44 PM
>> To: Yang, Qiming <qiming.yang@intel.com>; Wu, Wenjun1
>> <wenjun1.wu@intel.com>
>> Cc: dev@dpdk.org; Simon Ellmann <simon.ellmann@tum.de>
>> Subject: [PATCH] ixgbe: fix interrupt clear mask for eimc register
>> 
>> 32nd bit of the eimc register is reserved according to the datasheet
>> 
>> Signed-off-by: Simon Ellmann <simon.ellmann@tum.de>
>> ---
>> drivers/net/ixgbe/base/ixgbe_type.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/net/ixgbe/base/ixgbe_type.h
>> b/drivers/net/ixgbe/base/ixgbe_type.h
>> index 1094df5891..03b299cd10 100644
>> --- a/drivers/net/ixgbe/base/ixgbe_type.h
>> +++ b/drivers/net/ixgbe/base/ixgbe_type.h
>> @@ -2023,7 +2023,7 @@ enum {
>> #define IXGBE_FTQF_QUEUE_ENABLE		0x80000000
>> 
>> /* Interrupt clear mask */
>> -#define IXGBE_IRQ_CLEAR_MASK	0xFFFFFFFF
>> +#define IXGBE_IRQ_CLEAR_MASK	0x7FFFFFFF
> 
> If it is not harmful, I will prefer to keep the base code aligned with kernel driver's implementation which is 0xFFFFFFFF currently.

Alright. We fixed this in our driver implementation – https://github.com/ixy-languages/ixy.rs/issues/29 – and thought we would let you know.

>> 
>> /* Interrupt Vector Allocation Registers */
>> #define IXGBE_IVAR_REG_NUM		25
>> --
>> 2.43.0
>
Qi Zhang Dec. 19, 2023, 3:32 a.m. UTC | #3 
> -----Original Message-----
> From: Simon Ellmann <simon.ellmann@tum.de>
> Sent: Thursday, December 14, 2023 7:03 PM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: Yang, Qiming <qiming.yang@intel.com>; Wu, Wenjun1
> <wenjun1.wu@intel.com>; dev@dpdk.org
> Subject: Re: [PATCH] ixgbe: fix interrupt clear mask for eimc register
> 
> > On 14. Dec 2023, at 03:24, Zhang, Qi Z <qi.z.zhang@intel.com> wrote:
> >> -----Original Message-----
> >> From: Simon Ellmann <simon.ellmann@tum.de>
> >> Sent: Friday, December 8, 2023 11:44 PM
> >> To: Yang, Qiming <qiming.yang@intel.com>; Wu, Wenjun1
> >> <wenjun1.wu@intel.com>
> >> Cc: dev@dpdk.org; Simon Ellmann <simon.ellmann@tum.de>
> >> Subject: [PATCH] ixgbe: fix interrupt clear mask for eimc register
> >>
> >> 32nd bit of the eimc register is reserved according to the datasheet
> >>
> >> Signed-off-by: Simon Ellmann <simon.ellmann@tum.de>
> >> ---
> >> drivers/net/ixgbe/base/ixgbe_type.h | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/net/ixgbe/base/ixgbe_type.h
> >> b/drivers/net/ixgbe/base/ixgbe_type.h
> >> index 1094df5891..03b299cd10 100644
> >> --- a/drivers/net/ixgbe/base/ixgbe_type.h
> >> +++ b/drivers/net/ixgbe/base/ixgbe_type.h
> >> @@ -2023,7 +2023,7 @@ enum {
> >> #define IXGBE_FTQF_QUEUE_ENABLE		0x80000000
> >>
> >> /* Interrupt clear mask */
> >> -#define IXGBE_IRQ_CLEAR_MASK	0xFFFFFFFF
> >> +#define IXGBE_IRQ_CLEAR_MASK	0x7FFFFFFF
> >
> > If it is not harmful, I will prefer to keep the base code aligned with kernel
> driver's implementation which is 0xFFFFFFFF currently.
> 
> Alright. We fixed this in our driver implementation –
> https://github.com/ixy-languages/ixy.rs/issues/29 – and thought we would
> let you know.

Thanks

> 
> >>
> >> /* Interrupt Vector Allocation Registers */
> >> #define IXGBE_IVAR_REG_NUM		25
> >> --
> >> 2.43.0
> >
diff mbox series

Patch

diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h
index 1094df5891..03b299cd10 100644
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -2023,7 +2023,7 @@  enum {
 #define IXGBE_FTQF_QUEUE_ENABLE		0x80000000
 
 /* Interrupt clear mask */
-#define IXGBE_IRQ_CLEAR_MASK	0xFFFFFFFF
+#define IXGBE_IRQ_CLEAR_MASK	0x7FFFFFFF
 
 /* Interrupt Vector Allocation Registers */
 #define IXGBE_IVAR_REG_NUM		25