From patchwork Thu Dec 7 06:49:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 134902 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8B2F743694; Thu, 7 Dec 2023 07:49:50 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1DEF342E7A; Thu, 7 Dec 2023 07:49:50 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 1057240042 for ; Thu, 7 Dec 2023 07:49:48 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3B6JIeYb026191 for ; Wed, 6 Dec 2023 22:49:48 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=7i4/AHstKpCxreUBGJ2VQNE/z3Ulgs5DRrpZjeFor2c=; b=eR/x2OA6oRDWX0ByHLrOjy2Q3TnUzXjpH7DTXaXSjQdnAT7JCEEurPwWn2wRjd0FUWQm 9LPfK0GoSmC8SAAYsO54N9pDhHLp3yuQ66Ij3fi65VAi+qoBO5RGILMEwLqHfx00SYp0 THOnh5f2aOrIHpU8TYXYcxv5Cpr247XdsFc2oFVvHT6xAyAlGJ8pzLuX+30n1er/TR0V 2Nh+URtmZ/e65D9sZzq1Tfs8LC3pxgO+e82wT7BDa3Rtvkl08c3+B3o/nWrRo2LhEs6p VqdJHq2YqH1UUTRVyCvgIFR672+WrwR/W/uU2stXbW7cKHamRl8h9FJyP6CWz0ztvEXi Mw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3uty0jhyrq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 06 Dec 2023 22:49:48 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 6 Dec 2023 22:49:45 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 6 Dec 2023 22:49:45 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id E19173F7051; Wed, 6 Dec 2023 22:49:43 -0800 (PST) From: To: , Vamsi Attunuru CC: , Pavan Nikhilesh Subject: [PATCH v4 1/3] net/octeon_ep: optimize Rx and Tx routines Date: Thu, 7 Dec 2023 12:19:39 +0530 Message-ID: <20231207064941.1256-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231206172419.878-1-pbhagavatula@marvell.com> References: <20231206172419.878-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: fcqAfruiDdvg5J4kwdxx0MPdSApdWWHE X-Proofpoint-ORIG-GUID: fcqAfruiDdvg5J4kwdxx0MPdSApdWWHE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-07_04,2023-12-06_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Preset rearm data to avoid writing multiple fields in fastpath, Increase maximum outstanding Tx instructions from 128 to 256. Signed-off-by: Pavan Nikhilesh --- v4 Changes: - Fix checkpatch. - Update release notes. v3 Chnages: - Add more comments to the code. - Re-enable 32b build to prevent ABI break. v2 Changes: - Skip compiling for 32b x86 targets. drivers/net/octeon_ep/cnxk_ep_rx.c | 12 ++++++++---- drivers/net/octeon_ep/otx_ep_common.h | 3 +++ drivers/net/octeon_ep/otx_ep_rxtx.c | 27 +++++++++++++++++++++++++++ drivers/net/octeon_ep/otx_ep_rxtx.h | 2 +- 4 files changed, 39 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/drivers/net/octeon_ep/cnxk_ep_rx.c b/drivers/net/octeon_ep/cnxk_ep_rx.c index 74f0011283..75bb7225d2 100644 --- a/drivers/net/octeon_ep/cnxk_ep_rx.c +++ b/drivers/net/octeon_ep/cnxk_ep_rx.c @@ -93,7 +93,7 @@ cnxk_ep_check_rx_pkts(struct otx_ep_droq *droq) new_pkts = val - droq->pkts_sent_ism_prev; droq->pkts_sent_ism_prev = val; - if (val > (uint32_t)(1 << 31)) { + if (val > RTE_BIT32(31)) { /* Only subtract the packet count in the HW counter * when count above halfway to saturation. */ @@ -128,7 +128,6 @@ cnxk_ep_process_pkts_scalar(struct rte_mbuf **rx_pkts, struct otx_ep_droq *droq, { struct rte_mbuf **recv_buf_list = droq->recv_buf_list; uint32_t bytes_rsvd = 0, read_idx = droq->read_idx; - uint16_t port_id = droq->otx_ep_dev->port_id; uint16_t nb_desc = droq->nb_desc; uint16_t pkts; @@ -137,14 +136,19 @@ cnxk_ep_process_pkts_scalar(struct rte_mbuf **rx_pkts, struct otx_ep_droq *droq, struct rte_mbuf *mbuf; uint16_t pkt_len; + rte_prefetch0(recv_buf_list[otx_ep_incr_index(read_idx, 2, nb_desc)]); + rte_prefetch0(rte_pktmbuf_mtod(recv_buf_list[otx_ep_incr_index(read_idx, + 2, nb_desc)], + void *)); + mbuf = recv_buf_list[read_idx]; info = rte_pktmbuf_mtod(mbuf, struct otx_ep_droq_info *); read_idx = otx_ep_incr_index(read_idx, 1, nb_desc); pkt_len = rte_bswap16(info->length >> 48); - mbuf->data_off += OTX_EP_INFO_SIZE; mbuf->pkt_len = pkt_len; mbuf->data_len = pkt_len; - mbuf->port = port_id; + + *(uint64_t *)&mbuf->rearm_data = droq->rearm_data; rx_pkts[pkts] = mbuf; bytes_rsvd += pkt_len; } diff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h index 82e57520d3..299b5122d8 100644 --- a/drivers/net/octeon_ep/otx_ep_common.h +++ b/drivers/net/octeon_ep/otx_ep_common.h @@ -365,6 +365,9 @@ struct otx_ep_droq { /* receive buffer list contains mbuf ptr list */ struct rte_mbuf **recv_buf_list; + /* Packet re-arm data. */ + uint64_t rearm_data; + /* Packets pending to be processed */ uint64_t pkts_pending; diff --git a/drivers/net/octeon_ep/otx_ep_rxtx.c b/drivers/net/octeon_ep/otx_ep_rxtx.c index c421ef0a1c..40c4a16a38 100644 --- a/drivers/net/octeon_ep/otx_ep_rxtx.c +++ b/drivers/net/octeon_ep/otx_ep_rxtx.c @@ -284,6 +284,32 @@ otx_ep_droq_setup_ring_buffers(struct otx_ep_droq *droq) return 0; } +static inline uint64_t +otx_ep_set_rearm_data(struct otx_ep_device *otx_ep) +{ + uint16_t port_id = otx_ep->port_id; + struct rte_mbuf mb_def; + uint64_t *tmp; + + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0); + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) - offsetof(struct rte_mbuf, data_off) != + 2); + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) - offsetof(struct rte_mbuf, data_off) != + 4); + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) - offsetof(struct rte_mbuf, data_off) != + 6); + mb_def.nb_segs = 1; + mb_def.data_off = RTE_PKTMBUF_HEADROOM + OTX_EP_INFO_SIZE; + mb_def.port = port_id; + rte_mbuf_refcnt_set(&mb_def, 1); + + /* Prevent compiler reordering: rearm_data covers previous fields */ + rte_compiler_barrier(); + tmp = (uint64_t *)&mb_def.rearm_data; + + return *tmp; +} + /* OQ initialization */ static int otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no, @@ -340,6 +366,7 @@ otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no, goto init_droq_fail; droq->refill_threshold = c_refill_threshold; + droq->rearm_data = otx_ep_set_rearm_data(otx_ep); /* Set up OQ registers */ ret = otx_ep->fn_list.setup_oq_regs(otx_ep, q_no); diff --git a/drivers/net/octeon_ep/otx_ep_rxtx.h b/drivers/net/octeon_ep/otx_ep_rxtx.h index cb68ef3b41..b159c32cae 100644 --- a/drivers/net/octeon_ep/otx_ep_rxtx.h +++ b/drivers/net/octeon_ep/otx_ep_rxtx.h @@ -17,7 +17,7 @@ #define OTX_EP_FSZ 28 #define OTX2_EP_FSZ 24 -#define OTX_EP_MAX_INSTR 128 +#define OTX_EP_MAX_INSTR 256 /* SDP_LENGTH_S specifies packet length and is of 8-byte size */ #define OTX_EP_INFO_SIZE 8