From patchwork Mon Nov 27 13:39:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: huangdengdui X-Patchwork-Id: 134621 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D719A433E5; Mon, 27 Nov 2023 14:39:20 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5235440A6B; Mon, 27 Nov 2023 14:39:09 +0100 (CET) Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by mails.dpdk.org (Postfix) with ESMTP id F312C40273 for ; Mon, 27 Nov 2023 14:39:05 +0100 (CET) Received: from dggpeml500011.china.huawei.com (unknown [172.30.72.53]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4Sf6686cQPz1P8th; Mon, 27 Nov 2023 21:35:28 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 27 Nov 2023 21:39:04 +0800 From: Dengdui Huang To: CC: , , , , , Subject: [PATCH 3/3] net/hns3: fix the VF reset interrupted possibly Date: Mon, 27 Nov 2023 21:39:03 +0800 Message-ID: <20231127133903.1138657-4-huangdengdui@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20231127133903.1138657-1-huangdengdui@huawei.com> References: <20231127133903.1138657-1-huangdengdui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500011.china.huawei.com (7.185.36.84) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Currently, the VF reset interrupt is enabled before the reset process is completed. If the VF reset is triggered by an IMP reset, the initialization of IMP is may not completed, and the VF reset interrupt may continue to be reported. In this scenario, the VF reset being performed by the driver does not need to be interrupted. Therefore, for VF reset, the driver has to enable the interrupt after the end of reset. Fixes: a5475d61fa3 ("net/hns3: support VF") Cc: stable@dpdk.org Signed-off-by: Dengdui Huang --- drivers/net/hns3/hns3_ethdev.h | 12 ++++++++++++ drivers/net/hns3/hns3_ethdev_vf.c | 19 +++++++++++++++++-- drivers/net/hns3/hns3_intr.c | 6 ++---- 3 files changed, 31 insertions(+), 6 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 668f141e32..12d8299def 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -1035,6 +1035,7 @@ void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, uint32_t link_speed, uint8_t link_duplex); void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported); void hns3_clear_reset_event(struct hns3_hw *hw); +void hns3vf_clear_reset_event(struct hns3_hw *hw); const char *hns3_get_media_type_name(uint8_t media_type); @@ -1049,4 +1050,15 @@ is_reset_pending(struct hns3_adapter *hns) return ret; } +static inline void +hns3_clear_reset_status(struct hns3_hw *hw) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + + if (hns->is_vf) + hns3vf_clear_reset_event(hw); + else + hns3_clear_reset_event(hw); +} + #endif /* HNS3_ETHDEV_H */ diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 156fb905f9..53bcc44161 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -531,6 +531,19 @@ hns3vf_enable_irq0(struct hns3_hw *hw) hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); } +void +hns3vf_clear_reset_event(struct hns3_hw *hw) +{ + uint32_t clearval; + uint32_t cmdq_stat_reg; + + cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG); + clearval = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B); + hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, clearval); + + hns3vf_enable_irq0(hw); +} + static enum hns3vf_evt_cause hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) { @@ -605,8 +618,10 @@ hns3vf_interrupt_handler(void *param) break; } - /* Enable interrupt */ - hns3vf_enable_irq0(hw); + /* Enable interrupt if it is not cause by reset */ + if (event_cause == HNS3VF_VECTOR0_EVENT_MBX || + event_cause == HNS3VF_VECTOR0_EVENT_OTHER) + hns3vf_enable_irq0(hw); } void diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 52b5435a23..916bf30dcb 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -2749,8 +2749,7 @@ hns3_reset_post(struct hns3_adapter *hns) /* IMP will wait ready flag before reset */ hns3_notify_reset_ready(hw, false); hns3_clear_reset_level(hw, &hw->reset.pending); - if (!hns->is_vf) - hns3_clear_reset_event(hw); + hns3_clear_reset_status(hw); __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED); hw->reset.attempts = 0; hw->reset.stats.success_cnt++; @@ -2800,8 +2799,7 @@ hns3_reset_fail_handle(struct hns3_adapter *hns) struct timeval tv; hns3_clear_reset_level(hw, &hw->reset.pending); - if (!hns->is_vf) - hns3_clear_reset_event(hw); + hns3_clear_reset_status(hw); if (hns3_reset_err_handle(hns)) { hw->reset.stage = RESET_STAGE_PREWAIT; hns3_schedule_reset(hns);