diff mbox series

event/cnxk: update fc check to use SQEs

Message ID 20231016151055.2436-1-pbhagavatula@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Jerin Jacob
Headers
Series event/cnxk: update fc check to use SQEs |

Checks

Context Check Description
ci/checkpatch warning coding style issues
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/github-robot: build success github build: passed
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-compile-amd64-testing success Testing PASS
ci/iol-unit-arm64-testing success Testing PASS
ci/iol-unit-amd64-testing success Testing PASS
ci/iol-compile-arm64-testing success Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS

Commit Message

Pavan Nikhilesh Bhagavatula Oct. 16, 2023, 3:10 p.m. UTC 
  From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Update fc check to count SQEs instead of SQBs while waiting for
space.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 drivers/event/cnxk/cn10k_tx_worker.h | 33 ++++++++++++++++++----------
 drivers/event/cnxk/cn9k_worker.h     | 33 +++++++++++++++++++++++++---
 2 files changed, 51 insertions(+), 15 deletions(-)

Comments

Jerin Jacob Oct. 19, 2023, 4:31 a.m. UTC | #1 
On Mon, Oct 16, 2023 at 8:52 PM <pbhagavatula@marvell.com> wrote:
>
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>
> Update fc check to count SQEs instead of SQBs while waiting for
> space.
>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>

Applied to dpdk-next-net-eventdev/for-main. Thanks
diff mbox series

Patch

diff --git a/drivers/event/cnxk/cn10k_tx_worker.h b/drivers/event/cnxk/cn10k_tx_worker.h
index dea6cdcde2..53e0dde20c 100644
--- a/drivers/event/cnxk/cn10k_tx_worker.h
+++ b/drivers/event/cnxk/cn10k_tx_worker.h
@@ -24,26 +24,35 @@  cn10k_sso_hws_xtract_meta(struct rte_mbuf *m, const uint64_t *txq_data)
 static __rte_always_inline void
 cn10k_sso_txq_fc_wait(const struct cn10k_eth_txq *txq)
 {
+	int64_t avail;
+
 #ifdef RTE_ARCH_ARM64
-	uint64_t space;
+	int64_t val;
 
 	asm volatile(PLT_CPU_FEATURE_PREAMBLE
-		     "		ldxr %[space], [%[addr]]		\n"
-		     "		cmp %[adj], %[space] 			\n"
-		     "		b.hi .Ldne%=				\n"
+		     "		ldxr %[val], [%[addr]]			\n"
+		     "		sub %[val], %[adj], %[val]		\n"
+		     "		lsl %[refill], %[val], %[shft]		\n"
+		     "		sub %[refill], %[refill], %[val]	\n"
+		     "		cmp %[refill], #0x0			\n"
+		     "		b.gt .Ldne%=				\n"
 		     "		sevl					\n"
 		     ".Lrty%=:	wfe					\n"
-		     "		ldxr %[space], [%[addr]]		\n"
-		     "		cmp %[adj], %[space]			\n"
-		     "		b.ls .Lrty%=				\n"
+		     "		ldxr %[val], [%[addr]]			\n"
+		     "		sub %[val], %[adj], %[val]		\n"
+		     "		lsl %[refill], %[val], %[shft]		\n"
+		     "		sub %[refill], %[refill], %[val]	\n"
+		     "		cmp %[refill], #0x0			\n"
+		     "		b.le .Lrty%=				\n"
 		     ".Ldne%=:						\n"
-		     : [space] "=&r"(space)
-		     : [adj] "r"(txq->nb_sqb_bufs_adj), [addr] "r"(txq->fc_mem)
+		     : [refill] "=&r"(avail), [val] "=&r" (val)
+		     : [addr] "r"(txq->fc_mem), [adj] "r"(txq->nb_sqb_bufs_adj),
+		       [shft] "r"(txq->sqes_per_sqb_log2)
 		     : "memory");
 #else
-	while ((uint64_t)txq->nb_sqb_bufs_adj <=
-	       __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED))
-		;
+	do {
+		avail = txq->nb_sqb_bufs_adj - __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED);
+	} while (((avail << txq->sqes_per_sqb_log2) - avail) <= 0);
 #endif
 }
 
diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h
index 6936b7ad04..0451157812 100644
--- a/drivers/event/cnxk/cn9k_worker.h
+++ b/drivers/event/cnxk/cn9k_worker.h
@@ -542,9 +542,36 @@  NIX_RX_FASTPATH_MODES
 static __rte_always_inline void
 cn9k_sso_txq_fc_wait(const struct cn9k_eth_txq *txq)
 {
-	while ((uint64_t)txq->nb_sqb_bufs_adj <=
-	       __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED))
-		;
+	int64_t avail;
+
+#ifdef RTE_ARCH_ARM64
+	int64_t val;
+
+	asm volatile(PLT_CPU_FEATURE_PREAMBLE
+		     "		ldxr %[val], [%[addr]]			\n"
+		     "		sub %[val], %[adj], %[val]		\n"
+		     "		lsl %[refill], %[val], %[shft]		\n"
+		     "		sub %[refill], %[refill], %[val]	\n"
+		     "		cmp %[refill], #0x0			\n"
+		     "		b.gt .Ldne%=				\n"
+		     "		sevl					\n"
+		     ".Lrty%=:	wfe					\n"
+		     "		ldxr %[val], [%[addr]]			\n"
+		     "		sub %[val], %[adj], %[val]		\n"
+		     "		lsl %[refill], %[val], %[shft]		\n"
+		     "		sub %[refill], %[refill], %[val]	\n"
+		     "		cmp %[refill], #0x0			\n"
+		     "		b.le .Lrty%=				\n"
+		     ".Ldne%=:						\n"
+		     : [refill] "=&r"(avail), [val] "=&r" (val)
+		     : [addr] "r"(txq->fc_mem), [adj] "r"(txq->nb_sqb_bufs_adj),
+		       [shft] "r"(txq->sqes_per_sqb_log2)
+		     : "memory");
+#else
+	do {
+		avail = txq->nb_sqb_bufs_adj - __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED);
+	} while (((avail << txq->sqes_per_sqb_log2) - avail) <= 0);
+#endif
 }
 
 static __rte_always_inline struct cn9k_eth_txq *