diff --git a/doc/guides/bbdevs/features/vrb2.ini b/doc/guides/bbdevs/features/vrb2.ini
new file mode 100644
index 0000000000..23ca6990b7
--- /dev/null
+++ b/doc/guides/bbdevs/features/vrb2.ini
@@ -0,0 +1,14 @@
+;
+; Supported features of the 'Intel vRAN Boost v2' baseband driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G)     = Y
+Turbo Encoder (4G)     = Y
+LDPC Decoder (5G)      = Y
+LDPC Encoder (5G)      = Y
+LLR/HARQ Compression   = Y
+FFT/SRS                = Y
+External DDR Access    = N
+HW Accelerated         = Y
diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
index 77d4c54664..269157d77f 100644
--- a/doc/guides/bbdevs/index.rst
+++ b/doc/guides/bbdevs/index.rst
@@ -15,4 +15,5 @@ Baseband Device Drivers
     fpga_5gnr_fec
     acc100
     vrb1
+    vrb2
     la12xx
diff --git a/doc/guides/bbdevs/vrb2.rst b/doc/guides/bbdevs/vrb2.rst
new file mode 100644
index 0000000000..2a30002e05
--- /dev/null
+++ b/doc/guides/bbdevs/vrb2.rst
@@ -0,0 +1,206 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2023 Intel Corporation
+
+.. include:: <isonum.txt>
+
+Intel\ |reg| vRAN Boost v2 Poll Mode Driver (PMD)
+=================================================
+
+The Intel\ |reg| vRAN Boost integrated accelerator enables
+cost-effective 4G and 5G next-generation virtualized Radio Access Network (vRAN)
+solutions.
+The Intel vRAN Boost v2.0 (VRB2 in the code) is specifically integrated on the
+Intel\ |reg| Xeon\ |reg| Granite Rapids-D Process (GNR-D).
+
+Features
+--------
+
+Intel vRAN Boost v2.0 includes a 5G Low Density Parity Check (LDPC) encoder/decoder,
+rate match/dematch, Hybrid Automatic Repeat Request (HARQ) with access to DDR
+memory for buffer management, a 4G Turbo encoder/decoder,
+a Fast Fourier Transform (FFT) block providing DFT/iDFT processing offload
+for the 5G Sounding Reference Signal (SRS), a MLD-TS accelerator, a Queue Manager (QMGR),
+and a DMA subsystem.
+There is no dedicated on-card memory for HARQ, the coherent memory on the CPU side is being used.
+
+These hardware blocks provide the following features exposed by the PMD:
+
+- LDPC Encode in the Downlink (5GNR)
+- LDPC Decode in the Uplink (5GNR)
+- Turbo Encode in the Downlink (4G)
+- Turbo Decode in the Uplink (4G)
+- FFT processing
+- MLD-TS processing
+- Single Root I/O Virtualization (SR-IOV) with 16 Virtual Functions (VFs) per Physical Function (PF)
+- Maximum of 2048 queues per VF
+- Message Signaled Interrupts (MSIs)
+
+The Intel vRAN Boost v2.0 PMD supports the following bbdev capabilities:
+
+* For the LDPC encode operation:
+   - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH``: set to attach CRC24B to CB(s).
+   - ``RTE_BBDEV_LDPC_RATE_MATCH``: if set then do not do Rate Match bypass.
+   - ``RTE_BBDEV_LDPC_INTERLEAVER_BYPASS``: if set then bypass interleaver.
+   - ``RTE_BBDEV_LDPC_ENC_SCATTER_GATHER``: supports scatter-gather for input/output data.
+   - ``RTE_BBDEV_LDPC_ENC_CONCATENATION``: concatenate code blocks with bit granularity.
+
+* For the LDPC decode operation:
+   - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK``: check CRC24B from CB(s).
+   - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP``: drops CRC24B bits appended while decoding.
+   - ``RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK``: check CRC24A from CB(s).
+   - ``RTE_BBDEV_LDPC_CRC_TYPE_16_CHECK``: check CRC16 from CB(s).
+   - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE``: provides an input for HARQ combining.
+   - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE``: provides an input for HARQ combining.
+   - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE``: disable early termination.
+   - ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER``: supports scatter-gather for input/output data.
+   - ``RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION``: supports compression of the HARQ input/output.
+   - ``RTE_BBDEV_LDPC_LLR_COMPRESSION``: supports LLR input compression.
+   - ``RTE_BBDEV_LDPC_HARQ_4BIT_COMPRESSION``: supports compression of the HARQ input/output.
+   - ``RTE_BBDEV_LDPC_SOFT_OUT_ENABLE``: set the APP LLR soft output.
+   - ``RTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS``: set the APP LLR soft output after rate-matching.
+   - ``RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS``: disables the de-interleaver.
+
+* For the turbo encode operation:
+   - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH``: set to attach CRC24B to CB(s).
+   - ``RTE_BBDEV_TURBO_RATE_MATCH``: if set then do not do Rate Match bypass.
+   - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS``: set for encoder dequeue interrupts.
+   - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS``: set to bypass RV index.
+   - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER``: supports scatter-gather for input/output data.
+
+* For the turbo decode operation:
+   - ``RTE_BBDEV_TURBO_CRC_TYPE_24B``: check CRC24B from CB(s).
+   - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE``: perform subblock de-interleave.
+   - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS``: set for decoder dequeue interrupts.
+   - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN``: set if negative LLR input is supported.
+   - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP``: keep CRC24B bits appended while decoding.
+   - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP``: option to drop the code block CRC after decoding.
+   - ``RTE_BBDEV_TURBO_EARLY_TERMINATION``: set early termination feature.
+   - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER``: supports scatter-gather for input/output data.
+   - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN``: set half iteration granularity.
+   - ``RTE_BBDEV_TURBO_SOFT_OUTPUT``: set the APP LLR soft output.
+   - ``RTE_BBDEV_TURBO_EQUALIZER``: set the turbo equalizer feature.
+   - ``RTE_BBDEV_TURBO_SOFT_OUT_SATURATE``: set the soft output saturation.
+   - ``RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH``: set to run an extra odd iteration after CRC match.
+   - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT``: set if negative APP LLR output supported.
+   - ``RTE_BBDEV_TURBO_MAP_DEC``: supports flexible parallel MAP engine decoding.
+
+* For the FFT operation:
+   - ``RTE_BBDEV_FFT_WINDOWING``: flexible windowing capability.
+   - ``RTE_BBDEV_FFT_CS_ADJUSTMENT``: flexible adjustment of Cyclic Shift time offset.
+   - ``RTE_BBDEV_FFT_DFT_BYPASS``: set for bypass the DFT and get directly into iDFT input.
+   - ``RTE_BBDEV_FFT_IDFT_BYPASS``: set for bypass the IDFT and get directly the DFT output.
+   - ``RTE_BBDEV_FFT_WINDOWING_BYPASS``: set for bypass time domain windowing.
+
+* For the MLD-TS operation:
+   - ``RTE_BBDEV_MLDTS_REP``: set to repeat and reuse channel across operations.
+
+Installation
+------------
+
+Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.
+
+DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
+The bbdev test application has been tested with a configuration 40 x 1GB hugepages.
+The hugepage configuration of a server may be examined using:
+
+.. code-block:: console
+
+   grep Huge* /proc/meminfo
+
+
+Initialization
+--------------
+
+When the device first powers up, its PCI Physical Functions (PF)
+can be listed through these commands for Intel vRAN Boost v2:
+
+.. code-block:: console
+
+   sudo lspci -vd8086:57c2
+
+The physical and virtual functions are compatible with Linux UIO drivers:
+``vfio`` (preferred) and ``igb_uio`` (legacy).
+However, in order to work the 5G/4G FEC device first needs to be bound
+to one of these Linux drivers through DPDK.
+
+
+Configure the VFs through PF
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The PCI virtual functions must be configured before working or getting assigned
+to VMs/Containers.
+The configuration involves allocating the number of hardware queues, priorities,
+load balance, bandwidth and other settings necessary for the device
+to perform FEC functions.
+
+This configuration needs to be executed at least once after reboot or PCI FLR
+and can be achieved by using the functions ``rte_acc_configure()``,
+which sets up the parameters defined in the compatible ``rte_acc_conf`` structure.
+
+
+Test Application
+----------------
+
+The bbdev class is provided with a test application, ``test-bbdev.py``
+and range of test data for testing the functionality of the device,
+depending on the device's capabilities.
+The test application is located under app/test-bbdev folder
+and has the following options:
+
+.. code-block:: console
+
+   "-p", "--testapp-path": specifies path to the bbdev test app.
+   "-e", "--eal-params": EAL arguments which are passed to the test app.
+   "-t", "--timeout": Timeout in seconds (default=300).
+   "-c", "--test-cases": Defines test cases to run. Run all if not specified.
+   "-v", "--test-vector": Test vector path.
+   "-n", "--num-ops": Number of operations to process on device (default=32).
+   "-b", "--burst-size": Operations enqueue/dequeue burst size (default=32).
+   "-s", "--snr": SNR in dB used when generating LLRs for bler tests.
+   "-s", "--iter_max": Number of iterations for LDPC decoder.
+   "-l", "--num-lcores": Number of lcores to run (default=16).
+   "-i", "--init-device": Initialise PF device with default values.
+
+
+To execute the test application tool using simple decode or encode data,
+type one of the following:
+
+.. code-block:: console
+
+  ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data
+  ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data
+
+
+The test application ``test-bbdev.py``, supports the ability to configure the
+PF device with a default set of values, if the "-i" or "- -init-device" option
+is included. The default values are defined in test_bbdev_perf.c.
+
+
+Test Vectors
+~~~~~~~~~~~~
+
+In addition to the simple LDPC decoder and LDPC encoder tests,
+bbdev also provides a range of additional tests under the test_vectors folder,
+which may be useful.
+The results of these tests will depend on the device capabilities which may
+cause some test cases to be skipped, but no failure should be reported.
+
+
+Alternate Baseband Device configuration tool
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+On top of the embedded configuration feature supported in test-bbdev using
+"- -init-device" option mentioned above, there is also a tool available
+to perform that device configuration using a companion application.
+The ``pf_bb_config`` application notably enables then to run bbdev-test
+from the VF and not only limited to the PF as captured above.
+
+See for more details: https://github.com/intel/pf-bb-config
+
+Specifically for the bbdev Intel vRAN Boost v2 PMD, the command below can be used
+(note that ACC200 was used previously to refer to VRB2):
+
+.. code-block:: console
+
+   pf_bb_config VRB2 -c ./vrb2/vrb2_config_vf_5g.cfg
+   test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 64 -l 1 -v ./ldpc_dec_default.data
diff --git a/doc/guides/rel_notes/release_23_11.rst b/doc/guides/rel_notes/release_23_11.rst
index 333e1d95a2..668dd58ee3 100644
--- a/doc/guides/rel_notes/release_23_11.rst
+++ b/doc/guides/rel_notes/release_23_11.rst
@@ -78,6 +78,9 @@ New Features
 * build: Optional libraries can now be selected with the new ``enable_libs``
   build option similarly to the existing ``enable_drivers`` build option.
 
+* **Updated Intel vRAN Boost bbdev PMD.**
+
+  Added support for the new Intel vRAN Boost v2 device variant (GNR-D) within the unified driver.
 
 Removed Items
 -------------
diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c
index c89c26c59a..48e779ce77 100644
--- a/drivers/baseband/acc/rte_vrb_pmd.c
+++ b/drivers/baseband/acc/rte_vrb_pmd.c
@@ -37,6 +37,15 @@ vrb1_queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id
 		return ((qgrp_id << 7) + (aq_id << 3) + VRB1_VfQmgrIngressAq);
 }
 
+static inline uint32_t
+vrb2_queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id)
+{
+	if (pf_device)
+		return ((vf_id << 14) + (qgrp_id << 9) + (aq_id << 3) + VRB2_PfQmgrIngressAq);
+	else
+		return ((qgrp_id << 9) + (aq_id << 3) + VRB2_VfQmgrIngressAq);
+}
+
 enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, FFT, MLD, NUM_ACC};
 
 /* Return the accelerator enum for a Queue Group Index. */
@@ -197,7 +206,7 @@ fetch_acc_config(struct rte_bbdev *dev)
 	struct acc_device *d = dev->data->dev_private;
 	struct rte_acc_conf *acc_conf = &d->acc_conf;
 	uint8_t acc, qg;
-	uint32_t reg_aq, reg_len0, reg_len1, reg0, reg1;
+	uint32_t reg_aq, reg_len0, reg_len1, reg_len2, reg_len3, reg0, reg1, reg2, reg3;
 	uint32_t reg_mode, idx;
 	struct rte_acc_queue_topology *q_top = NULL;
 	int qman_func_id[VRB_NUM_ACCS] = {ACC_ACCMAP_0, ACC_ACCMAP_1,
@@ -219,32 +228,81 @@ fetch_acc_config(struct rte_bbdev *dev)
 	acc_conf->num_vf_bundles = 1;
 	initQTop(acc_conf);
 
-	reg0 = acc_reg_read(d, d->reg_addr->qman_group_func);
-	reg1 = acc_reg_read(d, d->reg_addr->qman_group_func + 4);
-	for (qg = 0; qg < d->num_qgroups; qg++) {
-		reg_aq = acc_reg_read(d, d->queue_offset(d->pf_device, 0, qg, 0));
-		if (reg_aq & ACC_QUEUE_ENABLE) {
-			if (qg < ACC_NUM_QGRPS_PER_WORD)
-				idx = (reg0 >> (qg * 4)) & 0x7;
+	if (d->device_variant == VRB1_VARIANT) {
+		reg0 = acc_reg_read(d, d->reg_addr->qman_group_func);
+		reg1 = acc_reg_read(d, d->reg_addr->qman_group_func + 4);
+		for (qg = 0; qg < d->num_qgroups; qg++) {
+			reg_aq = acc_reg_read(d, d->queue_offset(d->pf_device, 0, qg, 0));
+			if (reg_aq & ACC_QUEUE_ENABLE) {
+				if (qg < ACC_NUM_QGRPS_PER_WORD)
+					idx = (reg0 >> (qg * 4)) & 0x7;
+				else
+					idx = (reg1 >> ((qg - ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;
+				if (idx < VRB1_NUM_ACCS) {
+					acc = qman_func_id[idx];
+					updateQtop(acc, qg, acc_conf, d);
+				}
+			}
+		}
+
+		/* Check the depth of the AQs. */
+		reg_len0 = acc_reg_read(d, d->reg_addr->depth_log0_offset);
+		reg_len1 = acc_reg_read(d, d->reg_addr->depth_log1_offset);
+		for (acc = 0; acc < NUM_ACC; acc++) {
+			qtopFromAcc(&q_top, acc, acc_conf);
+			if (q_top->first_qgroup_index < ACC_NUM_QGRPS_PER_WORD)
+				q_top->aq_depth_log2 =
+						(reg_len0 >> (q_top->first_qgroup_index * 4)) & 0xF;
 			else
-				idx = (reg1 >> ((qg - ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;
-			if (idx < VRB1_NUM_ACCS) {
-				acc = qman_func_id[idx];
-				updateQtop(acc, qg, acc_conf, d);
+				q_top->aq_depth_log2 = (reg_len1 >> ((q_top->first_qgroup_index -
+						ACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;
+		}
+	} else {
+		reg0 = acc_reg_read(d, d->reg_addr->qman_group_func);
+		reg1 = acc_reg_read(d, d->reg_addr->qman_group_func + 4);
+		reg2 = acc_reg_read(d, d->reg_addr->qman_group_func + 8);
+		reg3 = acc_reg_read(d, d->reg_addr->qman_group_func + 12);
+		/* printf("Debug Function %08x %08x %08x %08x\n", reg0, reg1, reg2, reg3);*/
+		for (qg = 0; qg < VRB2_NUM_QGRPS; qg++) {
+			reg_aq = acc_reg_read(d, vrb2_queue_offset(d->pf_device, 0, qg, 0));
+			if (reg_aq & ACC_QUEUE_ENABLE) {
+				/* printf("Qg enabled %d %x\n", qg, reg_aq);*/
+				if (qg / ACC_NUM_QGRPS_PER_WORD == 0)
+					idx = (reg0 >> ((qg % ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;
+				else if (qg / ACC_NUM_QGRPS_PER_WORD == 1)
+					idx = (reg1 >> ((qg % ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;
+				else if (qg / ACC_NUM_QGRPS_PER_WORD == 2)
+					idx = (reg2 >> ((qg % ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;
+				else
+					idx = (reg3 >> ((qg % ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;
+				if (idx < VRB_NUM_ACCS) {
+					acc = qman_func_id[idx];
+					updateQtop(acc, qg, acc_conf, d);
+				}
 			}
 		}
-	}
 
-	/* Check the depth of the AQs. */
-	reg_len0 = acc_reg_read(d, d->reg_addr->depth_log0_offset);
-	reg_len1 = acc_reg_read(d, d->reg_addr->depth_log1_offset);
-	for (acc = 0; acc < NUM_ACC; acc++) {
-		qtopFromAcc(&q_top, acc, acc_conf);
-		if (q_top->first_qgroup_index < ACC_NUM_QGRPS_PER_WORD)
-			q_top->aq_depth_log2 = (reg_len0 >> (q_top->first_qgroup_index * 4)) & 0xF;
-		else
-			q_top->aq_depth_log2 = (reg_len1 >> ((q_top->first_qgroup_index -
-					ACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;
+		/* Check the depth of the AQs. */
+		reg_len0 = acc_reg_read(d, d->reg_addr->depth_log0_offset);
+		reg_len1 = acc_reg_read(d, d->reg_addr->depth_log0_offset + 4);
+		reg_len2 = acc_reg_read(d, d->reg_addr->depth_log0_offset + 8);
+		reg_len3 = acc_reg_read(d, d->reg_addr->depth_log0_offset + 12);
+
+		for (acc = 0; acc < NUM_ACC; acc++) {
+			qtopFromAcc(&q_top, acc, acc_conf);
+			if (q_top->first_qgroup_index / ACC_NUM_QGRPS_PER_WORD == 0)
+				q_top->aq_depth_log2 = (reg_len0 >> ((q_top->first_qgroup_index %
+						ACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;
+			else if (q_top->first_qgroup_index / ACC_NUM_QGRPS_PER_WORD == 1)
+				q_top->aq_depth_log2 = (reg_len1 >> ((q_top->first_qgroup_index %
+						ACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;
+			else if (q_top->first_qgroup_index / ACC_NUM_QGRPS_PER_WORD == 2)
+				q_top->aq_depth_log2 = (reg_len2 >> ((q_top->first_qgroup_index %
+						ACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;
+			else
+				q_top->aq_depth_log2 = (reg_len3 >> ((q_top->first_qgroup_index %
+						ACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;
+		}
 	}
 
 	/* Read PF mode. */
@@ -470,7 +528,10 @@ allocate_info_ring(struct rte_bbdev *dev)
 	phys_low  = (uint32_t)(info_ring_iova);
 	acc_reg_write(d, d->reg_addr->info_ring_hi, phys_high);
 	acc_reg_write(d, d->reg_addr->info_ring_lo, phys_low);
-	acc_reg_write(d, d->reg_addr->info_ring_en, VRB1_REG_IRQ_EN_ALL);
+	if (d->device_variant == VRB1_VARIANT)
+		acc_reg_write(d, d->reg_addr->info_ring_en, VRB1_REG_IRQ_EN_ALL);
+	else
+		acc_reg_write(d, d->reg_addr->info_ring_en, VRB2_REG_IRQ_EN_ALL);
 	d->info_ring_head = (acc_reg_read(d, d->reg_addr->info_ring_ptr) &
 			0xFFF) / sizeof(union acc_info_ring_data);
 	return 0;
@@ -549,6 +610,10 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
 	acc_reg_write(d, d->reg_addr->dma_ring_dl4g_lo, phys_low);
 	acc_reg_write(d, d->reg_addr->dma_ring_fft_hi, phys_high);
 	acc_reg_write(d, d->reg_addr->dma_ring_fft_lo, phys_low);
+	if (d->device_variant == VRB2_VARIANT) {
+		acc_reg_write(d, d->reg_addr->dma_ring_mld_hi, phys_high);
+		acc_reg_write(d, d->reg_addr->dma_ring_mld_lo, phys_low);
+	}
 	/*
 	 * Configure Ring Size to the max queue ring size
 	 * (used for wrapping purpose).
@@ -582,6 +647,10 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
 	acc_reg_write(d, d->reg_addr->tail_ptrs_dl4g_lo, phys_low);
 	acc_reg_write(d, d->reg_addr->tail_ptrs_fft_hi, phys_high);
 	acc_reg_write(d, d->reg_addr->tail_ptrs_fft_lo, phys_low);
+	if (d->device_variant == VRB2_VARIANT) {
+		acc_reg_write(d, d->reg_addr->tail_ptrs_mld_hi, phys_high);
+		acc_reg_write(d, d->reg_addr->tail_ptrs_mld_lo, phys_low);
+	}
 
 	ret = allocate_info_ring(dev);
 	if (ret < 0) {
@@ -679,10 +748,17 @@ vrb_intr_enable(struct rte_bbdev *dev)
 			return ret;
 		}
 
-		if (acc_dev->pf_device)
-			max_queues = VRB1_MAX_PF_MSIX;
-		else
-			max_queues = VRB1_MAX_VF_MSIX;
+		if (d->device_variant == VRB1_VARIANT) {
+			if (acc_dev->pf_device)
+				max_queues = VRB1_MAX_PF_MSIX;
+			else
+				max_queues = VRB1_MAX_VF_MSIX;
+		} else {
+			if (acc_dev->pf_device)
+				max_queues = VRB2_MAX_PF_MSIX;
+			else
+				max_queues = VRB2_MAX_VF_MSIX;
+		}
 
 		if (rte_intr_efd_enable(dev->intr_handle, max_queues)) {
 			rte_bbdev_log(ERR, "Failed to create fds for %u queues",
@@ -1158,6 +1234,10 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info)
 		RTE_BBDEV_END_OF_CAPABILITIES_LIST()
 	};
 
+	static const struct rte_bbdev_op_cap vrb2_bbdev_capabilities[] = {
+		RTE_BBDEV_END_OF_CAPABILITIES_LIST()
+	};
+
 	static struct rte_bbdev_queue_conf default_queue_conf;
 	default_queue_conf.socket = dev->data->socket_id;
 	default_queue_conf.queue_size = ACC_MAX_QUEUE_DEPTH;
@@ -1202,7 +1282,10 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info)
 	dev_info->default_queue_conf = default_queue_conf;
 	dev_info->cpu_flag_reqs = NULL;
 	dev_info->min_alignment = 1;
-	dev_info->capabilities = vrb1_bbdev_capabilities;
+	if (d->device_variant == VRB1_VARIANT)
+		dev_info->capabilities = vrb1_bbdev_capabilities;
+	else
+		dev_info->capabilities = vrb2_bbdev_capabilities;
 	dev_info->harq_buffer_size = 0;
 
 	vrb_check_ir(d);
@@ -1251,6 +1334,9 @@ static struct rte_pci_id pci_id_vrb_pf_map[] = {
 	{
 		RTE_PCI_DEVICE(RTE_VRB1_VENDOR_ID, RTE_VRB1_PF_DEVICE_ID)
 	},
+	{
+		RTE_PCI_DEVICE(RTE_VRB2_VENDOR_ID, RTE_VRB2_PF_DEVICE_ID)
+	},
 	{.device_id = 0},
 };
 
@@ -1259,6 +1345,9 @@ static struct rte_pci_id pci_id_vrb_vf_map[] = {
 	{
 		RTE_PCI_DEVICE(RTE_VRB1_VENDOR_ID, RTE_VRB1_VF_DEVICE_ID)
 	},
+	{
+		RTE_PCI_DEVICE(RTE_VRB2_VENDOR_ID, RTE_VRB2_VF_DEVICE_ID)
+	},
 	{.device_id = 0},
 };
 
@@ -3444,6 +3533,15 @@ vrb_bbdev_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)
 			d->reg_addr = &vrb1_pf_reg_addr;
 		else
 			d->reg_addr = &vrb1_vf_reg_addr;
+	} else {
+		d->device_variant = VRB2_VARIANT;
+		d->queue_offset = vrb2_queue_offset;
+		d->num_qgroups = VRB2_NUM_QGRPS;
+		d->num_aqs = VRB2_NUM_AQS;
+		if (d->pf_device)
+			d->reg_addr = &vrb2_pf_reg_addr;
+		else
+			d->reg_addr = &vrb2_vf_reg_addr;
 	}
 
 	rte_bbdev_log_debug("Init device %s [%s] @ vaddr %p paddr %#"PRIx64"",
diff --git a/drivers/baseband/acc/vrb2_pf_enum.h b/drivers/baseband/acc/vrb2_pf_enum.h
new file mode 100644
index 0000000000..28f10dc35b
--- /dev/null
+++ b/drivers/baseband/acc/vrb2_pf_enum.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Intel Corporation
+ */
+
+#ifndef VRB2_PF_ENUM_H
+#define VRB2_PF_ENUM_H
+
+/*
+ * VRB2 Register mapping on PF BAR0
+ * This is automatically generated from RDL, format may change with new RDL
+ * Release.
+ * Variable names are as is
+ */
+enum {
+	VRB2_PfQmgrEgressQueuesTemplate             = 0x0007FC00,
+	VRB2_PfQmgrIngressAq                        = 0x00100000,
+	VRB2_PfQmgrSoftReset                        = 0x00A00034,
+	VRB2_PfQmgrAramAllocEn	                    = 0x00A000a0,
+	VRB2_PfQmgrAramAllocSetupN0                 = 0x00A000b0,
+	VRB2_PfQmgrAramAllocSetupN1                 = 0x00A000b4,
+	VRB2_PfQmgrAramAllocSetupN2                 = 0x00A000b8,
+	VRB2_PfQmgrAramAllocSetupN3                 = 0x00A000bc,
+	VRB2_PfQmgrDepthLog2Grp                     = 0x00A00200,
+	VRB2_PfQmgrTholdGrp                         = 0x00A00300,
+	VRB2_PfQmgrGrpTmplateReg0Indx               = 0x00A00600,
+	VRB2_PfQmgrGrpTmplateReg1Indx               = 0x00A00700,
+	VRB2_PfQmgrGrpTmplateReg2Indx               = 0x00A00800,
+	VRB2_PfQmgrGrpTmplateReg3Indx               = 0x00A00900,
+	VRB2_PfQmgrGrpTmplateReg4Indx               = 0x00A00A00,
+	VRB2_PfQmgrGrpTmplateReg5Indx               = 0x00A00B00,
+	VRB2_PfQmgrGrpTmplateReg6Indx               = 0x00A00C00,
+	VRB2_PfQmgrGrpTmplateReg7Indx               = 0x00A00D00,
+	VRB2_PfQmgrGrpTmplateEnRegIndx              = 0x00A00E00,
+	VRB2_PfQmgrArbQDepthGrp                     = 0x00A02F00,
+	VRB2_PfQmgrGrpFunction0                     = 0x00A02F80,
+	VRB2_PfQmgrGrpPriority                      = 0x00A02FC0,
+	VRB2_PfQmgrVfBaseAddr                       = 0x00A08000,
+	VRB2_PfQmgrAqEnableVf                       = 0x00A10000,
+	VRB2_PfQmgrRingSizeVf                       = 0x00A20010,
+	VRB2_PfQmgrGrpDepthLog20Vf                  = 0x00A20020,
+	VRB2_PfQmgrGrpDepthLog21Vf                  = 0x00A20024,
+	VRB2_PfFabricM2iBufferReg                   = 0x00B30000,
+	VRB2_PfFecUl5gIbDebug0Reg                   = 0x00B401FC,
+	VRB2_PfFftConfig0                           = 0x00B58004,
+	VRB2_PfFftParityMask8                       = 0x00B5803C,
+	VRB2_PfDmaConfig0Reg                        = 0x00B80000,
+	VRB2_PfDmaConfig1Reg                        = 0x00B80004,
+	VRB2_PfDmaQmgrAddrReg                       = 0x00B80008,
+	VRB2_PfDmaAxcacheReg                        = 0x00B80010,
+	VRB2_PfDmaAxiControl                        = 0x00B8002C,
+	VRB2_PfDmaQmanen                            = 0x00B80040,
+	VRB2_PfDmaQmanenSelect                      = 0x00B80044,
+	VRB2_PfDmaCfgRrespBresp                     = 0x00B80814,
+	VRB2_PfDmaDescriptorSignature               = 0x00B80868,
+	VRB2_PfDmaErrorDetectionEn                  = 0x00B80870,
+	VRB2_PfDmaFec5GulDescBaseLoRegVf            = 0x00B88020,
+	VRB2_PfDmaFec5GulDescBaseHiRegVf            = 0x00B88024,
+	VRB2_PfDmaFec5GulRespPtrLoRegVf             = 0x00B88028,
+	VRB2_PfDmaFec5GulRespPtrHiRegVf             = 0x00B8802C,
+	VRB2_PfDmaFec5GdlDescBaseLoRegVf            = 0x00B88040,
+	VRB2_PfDmaFec5GdlDescBaseHiRegVf            = 0x00B88044,
+	VRB2_PfDmaFec5GdlRespPtrLoRegVf             = 0x00B88048,
+	VRB2_PfDmaFec5GdlRespPtrHiRegVf             = 0x00B8804C,
+	VRB2_PfDmaFec4GulDescBaseLoRegVf            = 0x00B88060,
+	VRB2_PfDmaFec4GulDescBaseHiRegVf            = 0x00B88064,
+	VRB2_PfDmaFec4GulRespPtrLoRegVf             = 0x00B88068,
+	VRB2_PfDmaFec4GulRespPtrHiRegVf             = 0x00B8806C,
+	VRB2_PfDmaFec4GdlDescBaseLoRegVf            = 0x00B88080,
+	VRB2_PfDmaFec4GdlDescBaseHiRegVf            = 0x00B88084,
+	VRB2_PfDmaFec4GdlRespPtrLoRegVf             = 0x00B88088,
+	VRB2_PfDmaFec4GdlRespPtrHiRegVf             = 0x00B8808C,
+	VRB2_PfDmaFftDescBaseLoRegVf                = 0x00B880A0,
+	VRB2_PfDmaFftDescBaseHiRegVf                = 0x00B880A4,
+	VRB2_PfDmaFftRespPtrLoRegVf                 = 0x00B880A8,
+	VRB2_PfDmaFftRespPtrHiRegVf                 = 0x00B880AC,
+	VRB2_PfDmaMldDescBaseLoRegVf                = 0x00B880C0,
+	VRB2_PfDmaMldDescBaseHiRegVf                = 0x00B880C4,
+	VRB2_PfQosmonAEvalOverflow0                 = 0x00B90008,
+	VRB2_PfPermonACntrlRegVf                    = 0x00B98000,
+	VRB2_PfQosmonBEvalOverflow0                 = 0x00BA0008,
+	VRB2_PfPermonBCntrlRegVf                    = 0x00BA8000,
+	VRB2_PfPermonCCntrlRegVf                    = 0x00BB8000,
+	VRB2_PfHiInfoRingBaseLoRegPf                = 0x00C84014,
+	VRB2_PfHiInfoRingBaseHiRegPf                = 0x00C84018,
+	VRB2_PfHiInfoRingPointerRegPf               = 0x00C8401C,
+	VRB2_PfHiInfoRingIntWrEnRegPf               = 0x00C84020,
+	VRB2_PfHiBlockTransmitOnErrorEn             = 0x00C84038,
+	VRB2_PfHiCfgMsiIntWrEnRegPf                 = 0x00C84040,
+	VRB2_PfHiMsixVectorMapperPf                 = 0x00C84060,
+	VRB2_PfHiPfMode                             = 0x00C84108,
+	VRB2_PfHiClkGateHystReg                     = 0x00C8410C,
+	VRB2_PfHiMsiDropEnableReg                   = 0x00C84114,
+	VRB2_PfHiSectionPowerGatingReq              = 0x00C84128,
+	VRB2_PfHiSectionPowerGatingAck              = 0x00C8412C,
+};
+
+/* TIP PF Interrupt numbers */
+enum {
+	VRB2_PF_INT_QMGR_AQ_OVERFLOW = 0,
+	VRB2_PF_INT_DOORBELL_VF_2_PF = 1,
+	VRB2_PF_INT_ILLEGAL_FORMAT = 2,
+	VRB2_PF_INT_QMGR_DISABLED_ACCESS = 3,
+	VRB2_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4,
+	VRB2_PF_INT_DMA_DL_DESC_IRQ = 5,
+	VRB2_PF_INT_DMA_UL_DESC_IRQ = 6,
+	VRB2_PF_INT_DMA_FFT_DESC_IRQ = 7,
+	VRB2_PF_INT_DMA_UL5G_DESC_IRQ = 8,
+	VRB2_PF_INT_DMA_DL5G_DESC_IRQ = 9,
+	VRB2_PF_INT_DMA_MLD_DESC_IRQ = 10,
+	VRB2_PF_INT_ARAM_ACCESS_ERR = 11,
+	VRB2_PF_INT_ARAM_ECC_1BIT_ERR = 12,
+	VRB2_PF_INT_PARITY_ERR = 13,
+	VRB2_PF_INT_QMGR_OVERFLOW = 14,
+	VRB2_PF_INT_QMGR_ERR = 15,
+	VRB2_PF_INT_ATS_ERR = 22,
+	VRB2_PF_INT_ARAM_FUUL = 23,
+	VRB2_PF_INT_EXTRA_READ = 24,
+	VRB2_PF_INT_COMPLETION_TIMEOUT = 25,
+	VRB2_PF_INT_CORE_HANG = 26,
+	VRB2_PF_INT_DMA_HANG = 28,
+	VRB2_PF_INT_DS_HANG = 27,
+};
+
+#endif /* VRB2_PF_ENUM_H */
diff --git a/drivers/baseband/acc/vrb2_vf_enum.h b/drivers/baseband/acc/vrb2_vf_enum.h
new file mode 100644
index 0000000000..9c6e451010
--- /dev/null
+++ b/drivers/baseband/acc/vrb2_vf_enum.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Intel Corporation
+ */
+
+#ifndef VRB2_VF_ENUM_H
+#define VRB2_VF_ENUM_H
+
+/*
+ * VRB2 Register mapping on VF BAR0
+ * This is automatically generated from RDL, format may change with new RDL
+ */
+enum {
+	VRB2_VfHiVfToPfDbellVf           = 0x00000000,
+	VRB2_VfHiPfToVfDbellVf           = 0x00000008,
+	VRB2_VfHiInfoRingBaseLoVf        = 0x00000010,
+	VRB2_VfHiInfoRingBaseHiVf        = 0x00000014,
+	VRB2_VfHiInfoRingPointerVf       = 0x00000018,
+	VRB2_VfHiInfoRingIntWrEnVf       = 0x00000020,
+	VRB2_VfHiInfoRingPf2VfWrEnVf     = 0x00000024,
+	VRB2_VfHiMsixVectorMapperVf      = 0x00000060,
+	VRB2_VfHiDeviceStatus            = 0x00000068,
+	VRB2_VfHiInterruptSrc            = 0x00000070,
+	VRB2_VfDmaFec5GulDescBaseLoRegVf = 0x00000120,
+	VRB2_VfDmaFec5GulDescBaseHiRegVf = 0x00000124,
+	VRB2_VfDmaFec5GulRespPtrLoRegVf  = 0x00000128,
+	VRB2_VfDmaFec5GulRespPtrHiRegVf  = 0x0000012C,
+	VRB2_VfDmaFec5GdlDescBaseLoRegVf = 0x00000140,
+	VRB2_VfDmaFec5GdlDescBaseHiRegVf = 0x00000144,
+	VRB2_VfDmaFec5GdlRespPtrLoRegVf  = 0x00000148,
+	VRB2_VfDmaFec5GdlRespPtrHiRegVf  = 0x0000014C,
+	VRB2_VfDmaFec4GulDescBaseLoRegVf = 0x00000160,
+	VRB2_VfDmaFec4GulDescBaseHiRegVf = 0x00000164,
+	VRB2_VfDmaFec4GulRespPtrLoRegVf  = 0x00000168,
+	VRB2_VfDmaFec4GulRespPtrHiRegVf  = 0x0000016C,
+	VRB2_VfDmaFec4GdlDescBaseLoRegVf = 0x00000180,
+	VRB2_VfDmaFec4GdlDescBaseHiRegVf = 0x00000184,
+	VRB2_VfDmaFec4GdlRespPtrLoRegVf  = 0x00000188,
+	VRB2_VfDmaFec4GdlRespPtrHiRegVf  = 0x0000018C,
+	VRB2_VfDmaFftDescBaseLoRegVf     = 0x000001A0,
+	VRB2_VfDmaFftDescBaseHiRegVf     = 0x000001A4,
+	VRB2_VfDmaFftRespPtrLoRegVf      = 0x000001A8,
+	VRB2_VfDmaFftRespPtrHiRegVf      = 0x000001AC,
+	VRB2_VfDmaMldDescBaseLoRegVf     = 0x000001C0,
+	VRB2_VfDmaMldDescBaseHiRegVf     = 0x000001C4,
+	VRB2_VfDmaMldRespPtrLoRegVf      = 0x000001C8,
+	VRB2_VfDmaMldRespPtrHiRegVf      = 0x000001CC,
+	VRB2_VfPmACntrlRegVf             = 0x00000200,
+	VRB2_VfPmACountVf                = 0x00000208,
+	VRB2_VfPmAKCntLoVf               = 0x00000210,
+	VRB2_VfPmAKCntHiVf               = 0x00000214,
+	VRB2_VfPmADeltaCntLoVf           = 0x00000220,
+	VRB2_VfPmADeltaCntHiVf           = 0x00000224,
+	VRB2_VfPmBCntrlRegVf             = 0x00000240,
+	VRB2_VfPmBCountVf                = 0x00000248,
+	VRB2_VfPmBKCntLoVf               = 0x00000250,
+	VRB2_VfPmBKCntHiVf               = 0x00000254,
+	VRB2_VfPmBDeltaCntLoVf           = 0x00000260,
+	VRB2_VfPmBDeltaCntHiVf           = 0x00000264,
+	VRB2_VfPmCCntrlRegVf             = 0x00000280,
+	VRB2_VfPmCCountVf                = 0x00000288,
+	VRB2_VfPmCKCntLoVf               = 0x00000290,
+	VRB2_VfPmCKCntHiVf               = 0x00000294,
+	VRB2_VfPmCDeltaCntLoVf           = 0x000002A0,
+	VRB2_VfPmCDeltaCntHiVf           = 0x000002A4,
+	VRB2_VfPmDCntrlRegVf             = 0x000002C0,
+	VRB2_VfPmDCountVf                = 0x000002C8,
+	VRB2_VfPmDKCntLoVf               = 0x000002D0,
+	VRB2_VfPmDKCntHiVf               = 0x000002D4,
+	VRB2_VfPmDDeltaCntLoVf           = 0x000002E0,
+	VRB2_VfPmDDeltaCntHiVf           = 0x000002E4,
+	VRB2_VfPmECntrlRegVf             = 0x00000300,
+	VRB2_VfPmECountVf                = 0x00000308,
+	VRB2_VfPmEKCntLoVf               = 0x00000310,
+	VRB2_VfPmEKCntHiVf               = 0x00000314,
+	VRB2_VfPmEDeltaCntLoVf           = 0x00000320,
+	VRB2_VfPmEDeltaCntHiVf           = 0x00000324,
+	VRB2_VfPmFCntrlRegVf             = 0x00000340,
+	VRB2_VfPmFCountVf                = 0x00000348,
+	VRB2_VfPmFKCntLoVf               = 0x00000350,
+	VRB2_VfPmFKCntHiVf               = 0x00000354,
+	VRB2_VfPmFDeltaCntLoVf           = 0x00000360,
+	VRB2_VfPmFDeltaCntHiVf           = 0x00000364,
+	VRB2_VfQmgrAqReset0              = 0x00000600,
+	VRB2_VfQmgrAqReset1              = 0x00000604,
+	VRB2_VfQmgrAqReset2              = 0x00000608,
+	VRB2_VfQmgrAqReset3              = 0x0000060C,
+	VRB2_VfQmgrRingSizeVf            = 0x00000610,
+	VRB2_VfQmgrGrpDepthLog20Vf       = 0x00000620,
+	VRB2_VfQmgrGrpDepthLog21Vf       = 0x00000624,
+	VRB2_VfQmgrGrpDepthLog22Vf       = 0x00000628,
+	VRB2_VfQmgrGrpDepthLog23Vf       = 0x0000062C,
+	VRB2_VfQmgrGrpFunction0Vf        = 0x00000630,
+	VRB2_VfQmgrGrpFunction1Vf        = 0x00000634,
+	VRB2_VfQmgrAramUsageN0           = 0x00000640,
+	VRB2_VfQmgrAramUsageN1           = 0x00000644,
+	VRB2_VfQmgrAramUsageN2           = 0x00000648,
+	VRB2_VfQmgrAramUsageN3           = 0x0000064C,
+	VRB2_VfHiMSIXBaseLoRegVf         = 0x00001000,
+	VRB2_VfHiMSIXBaseHiRegVf         = 0x00001004,
+	VRB2_VfHiMSIXBaseDataRegVf       = 0x00001008,
+	VRB2_VfHiMSIXBaseMaskRegVf       = 0x0000100C,
+	VRB2_VfHiMSIXPBABaseLoRegVf      = 0x00003000,
+	VRB2_VfQmgrIngressAq             = 0x00004000,
+};
+
+/* TIP VF Interrupt numbers */
+enum {
+	VRB2_VF_INT_QMGR_AQ_OVERFLOW = 0,
+	VRB2_VF_INT_DOORBELL_PF_2_VF = 1,
+	VRB2_VF_INT_ILLEGAL_FORMAT = 2,
+	VRB2_VF_INT_QMGR_DISABLED_ACCESS = 3,
+	VRB2_VF_INT_QMGR_AQ_OVERTHRESHOLD = 4,
+	VRB2_VF_INT_DMA_DL_DESC_IRQ = 5,
+	VRB2_VF_INT_DMA_UL_DESC_IRQ = 6,
+	VRB2_VF_INT_DMA_FFT_DESC_IRQ = 7,
+	VRB2_VF_INT_DMA_UL5G_DESC_IRQ = 8,
+	VRB2_VF_INT_DMA_DL5G_DESC_IRQ = 9,
+	VRB2_VF_INT_DMA_MLD_DESC_IRQ = 10,
+};
+
+#endif /* VRB2_VF_ENUM_H */
diff --git a/drivers/baseband/acc/vrb_pmd.h b/drivers/baseband/acc/vrb_pmd.h
index 1cabc0b7f4..0371db9972 100644
--- a/drivers/baseband/acc/vrb_pmd.h
+++ b/drivers/baseband/acc/vrb_pmd.h
@@ -8,6 +8,8 @@
 #include "acc_common.h"
 #include "vrb1_pf_enum.h"
 #include "vrb1_vf_enum.h"
+#include "vrb2_pf_enum.h"
+#include "vrb2_vf_enum.h"
 #include "vrb_cfg.h"
 
 /* Helper macro for logging */
@@ -31,12 +33,13 @@
 #define RTE_VRB1_VENDOR_ID           (0x8086)
 #define RTE_VRB1_PF_DEVICE_ID        (0x57C0)
 #define RTE_VRB1_VF_DEVICE_ID        (0x57C1)
-
-#define VRB1_VARIANT               2
+#define RTE_VRB2_VENDOR_ID           (0x8086)
+#define RTE_VRB2_PF_DEVICE_ID        (0x57C2)
+#define RTE_VRB2_VF_DEVICE_ID        (0x57C3)
 
 #define VRB_NUM_ACCS                 6
 #define VRB_MAX_QGRPS                32
-#define VRB_MAX_AQS                  32
+#define VRB_MAX_AQS                  64
 
 #define ACC_STATUS_WAIT      10
 #define ACC_STATUS_TO        100
@@ -46,8 +49,6 @@
 #define VRB1_NUM_VFS                  16
 #define VRB1_NUM_QGRPS                16
 #define VRB1_NUM_AQS                  16
-#define VRB1_GRP_ID_SHIFT    10 /* Queue Index Hierarchy */
-#define VRB1_VF_ID_SHIFT     4  /* Queue Index Hierarchy */
 #define VRB1_WORDS_IN_ARAM_SIZE (256 * 1024 / 4)
 
 /* VRB1 Mapping of signals for the available engines */
@@ -61,7 +62,6 @@
 #define VRB1_SIG_DL_4G_LAST 23
 #define VRB1_SIG_FFT        24
 #define VRB1_SIG_FFT_LAST   24
-
 #define VRB1_NUM_ACCS       5
 
 /* VRB1 Configuration */
@@ -90,6 +90,67 @@
 #define VRB1_MAX_PF_MSIX            (256+32)
 #define VRB1_MAX_VF_MSIX            (256+7)
 
+/* VRB2 specific flags */
+
+#define VRB2_NUM_VFS        64
+#define VRB2_NUM_QGRPS      32
+#define VRB2_NUM_AQS        64
+#define VRB2_WORDS_IN_ARAM_SIZE (512 * 1024 / 4)
+#define VRB2_NUM_ACCS        6
+#define VRB2_AQ_REG_NUM      4
+
+/* VRB2 Mapping of signals for the available engines */
+#define VRB2_SIG_UL_5G       0
+#define VRB2_SIG_UL_5G_LAST  5
+#define VRB2_SIG_DL_5G       9
+#define VRB2_SIG_DL_5G_LAST 11
+#define VRB2_SIG_UL_4G      12
+#define VRB2_SIG_UL_4G_LAST 16
+#define VRB2_SIG_DL_4G      21
+#define VRB2_SIG_DL_4G_LAST 23
+#define VRB2_SIG_FFT        24
+#define VRB2_SIG_FFT_LAST   26
+#define VRB2_SIG_MLD        30
+#define VRB2_SIG_MLD_LAST   31
+#define VRB2_FFT_NUM        3
+
+#define VRB2_FCW_MLDTS_BLEN 32
+#define VRB2_MLD_MIN_LAYER   2
+#define VRB2_MLD_MAX_LAYER   4
+#define VRB2_MLD_MAX_RREP    5
+#define VRB2_MLD_LAY_SIZE    3
+#define VRB2_MLD_RREP_SIZE   6
+#define VRB2_MLD_M2DLEN      3
+
+#define VRB2_MAX_PF_MSIX      (256+32)
+#define VRB2_MAX_VF_MSIX      (64+7)
+#define VRB2_REG_IRQ_EN_ALL   0xFFFFFFFF  /* Enable all interrupts */
+#define VRB2_FABRIC_MODE      0x8000103
+#define VRB2_CFG_DMA_ERROR    0x7DF
+#define VRB2_CFG_AXI_CACHE    0x11
+#define VRB2_CFG_QMGR_HI_P    0x0F0F
+#define VRB2_RESET_HARD       0x1FF
+#define VRB2_ENGINES_MAX      9
+#define VRB2_GPEX_AXIMAP_NUM  17
+#define VRB2_CLOCK_GATING_EN  0x30000
+#define VRB2_FFT_CFG_0        0x2001
+#define VRB2_FFT_ECC          0x60
+#define VRB2_FFT_RAM_EN       0x80008000
+#define VRB2_FFT_RAM_DIS      0x0
+#define VRB2_FFT_RAM_SIZE     512
+#define VRB2_CLK_EN           0x00010A01
+#define VRB2_CLK_DIS          0x01F10A01
+#define VRB2_PG_MASK_0        0x1F
+#define VRB2_PG_MASK_1        0xF
+#define VRB2_PG_MASK_2        0x1
+#define VRB2_PG_MASK_3        0x0
+#define VRB2_PG_MASK_FFT      1
+#define VRB2_PG_MASK_4GUL     4
+#define VRB2_PG_MASK_5GUL     8
+#define VRB2_PF_PM_REG_OFFSET 0x10000
+#define VRB2_VF_PM_REG_OFFSET 0x40
+#define VRB2_PM_START         0x2
+
 struct acc_registry_addr {
 	unsigned int dma_ring_dl5g_hi;
 	unsigned int dma_ring_dl5g_lo;
@@ -218,4 +279,92 @@ static const struct acc_registry_addr vrb1_vf_reg_addr = {
 	.pf2vf_doorbell = VRB1_VfHiPfToVfDbellVf,
 };
 
+
+/* Structure holding registry addresses for PF */
+static const struct acc_registry_addr vrb2_pf_reg_addr = {
+	.dma_ring_dl5g_hi =  VRB2_PfDmaFec5GdlDescBaseHiRegVf,
+	.dma_ring_dl5g_lo =  VRB2_PfDmaFec5GdlDescBaseLoRegVf,
+	.dma_ring_ul5g_hi =  VRB2_PfDmaFec5GulDescBaseHiRegVf,
+	.dma_ring_ul5g_lo =  VRB2_PfDmaFec5GulDescBaseLoRegVf,
+	.dma_ring_dl4g_hi =  VRB2_PfDmaFec4GdlDescBaseHiRegVf,
+	.dma_ring_dl4g_lo =  VRB2_PfDmaFec4GdlDescBaseLoRegVf,
+	.dma_ring_ul4g_hi =  VRB2_PfDmaFec4GulDescBaseHiRegVf,
+	.dma_ring_ul4g_lo =  VRB2_PfDmaFec4GulDescBaseLoRegVf,
+	.dma_ring_fft_hi =   VRB2_PfDmaFftDescBaseHiRegVf,
+	.dma_ring_fft_lo =   VRB2_PfDmaFftDescBaseLoRegVf,
+	.dma_ring_mld_hi =   VRB2_PfDmaMldDescBaseHiRegVf,
+	.dma_ring_mld_lo =   VRB2_PfDmaMldDescBaseLoRegVf,
+	.ring_size =         VRB2_PfQmgrRingSizeVf,
+	.info_ring_hi =      VRB2_PfHiInfoRingBaseHiRegPf,
+	.info_ring_lo =      VRB2_PfHiInfoRingBaseLoRegPf,
+	.info_ring_en =      VRB2_PfHiInfoRingIntWrEnRegPf,
+	.info_ring_ptr =     VRB2_PfHiInfoRingPointerRegPf,
+	.tail_ptrs_dl5g_hi = VRB2_PfDmaFec5GdlRespPtrHiRegVf,
+	.tail_ptrs_dl5g_lo = VRB2_PfDmaFec5GdlRespPtrLoRegVf,
+	.tail_ptrs_ul5g_hi = VRB2_PfDmaFec5GulRespPtrHiRegVf,
+	.tail_ptrs_ul5g_lo = VRB2_PfDmaFec5GulRespPtrLoRegVf,
+	.tail_ptrs_dl4g_hi = VRB2_PfDmaFec4GdlRespPtrHiRegVf,
+	.tail_ptrs_dl4g_lo = VRB2_PfDmaFec4GdlRespPtrLoRegVf,
+	.tail_ptrs_ul4g_hi = VRB2_PfDmaFec4GulRespPtrHiRegVf,
+	.tail_ptrs_ul4g_lo = VRB2_PfDmaFec4GulRespPtrLoRegVf,
+	.tail_ptrs_fft_hi =  VRB2_PfDmaFftRespPtrHiRegVf,
+	.tail_ptrs_fft_lo =  VRB2_PfDmaFftRespPtrLoRegVf,
+	.tail_ptrs_mld_hi =  VRB2_PfDmaFftRespPtrHiRegVf,
+	.tail_ptrs_mld_lo =  VRB2_PfDmaFftRespPtrLoRegVf,
+	.depth_log0_offset = VRB2_PfQmgrGrpDepthLog20Vf,
+	.depth_log1_offset = VRB2_PfQmgrGrpDepthLog21Vf,
+	.qman_group_func =   VRB2_PfQmgrGrpFunction0,
+	.hi_mode =           VRB2_PfHiMsixVectorMapperPf,
+	.pf_mode =           VRB2_PfHiPfMode,
+	.pmon_ctrl_a =       VRB2_PfPermonACntrlRegVf,
+	.pmon_ctrl_b =       VRB2_PfPermonBCntrlRegVf,
+	.pmon_ctrl_c =       VRB2_PfPermonCCntrlRegVf,
+	.vf2pf_doorbell =    0,
+	.pf2vf_doorbell =    0,
+};
+
+/* Structure holding registry addresses for VF */
+static const struct acc_registry_addr vrb2_vf_reg_addr = {
+	.dma_ring_dl5g_hi =  VRB2_VfDmaFec5GdlDescBaseHiRegVf,
+	.dma_ring_dl5g_lo =  VRB2_VfDmaFec5GdlDescBaseLoRegVf,
+	.dma_ring_ul5g_hi =  VRB2_VfDmaFec5GulDescBaseHiRegVf,
+	.dma_ring_ul5g_lo =  VRB2_VfDmaFec5GulDescBaseLoRegVf,
+	.dma_ring_dl4g_hi =  VRB2_VfDmaFec4GdlDescBaseHiRegVf,
+	.dma_ring_dl4g_lo =  VRB2_VfDmaFec4GdlDescBaseLoRegVf,
+	.dma_ring_ul4g_hi =  VRB2_VfDmaFec4GulDescBaseHiRegVf,
+	.dma_ring_ul4g_lo =  VRB2_VfDmaFec4GulDescBaseLoRegVf,
+	.dma_ring_fft_hi =   VRB2_VfDmaFftDescBaseHiRegVf,
+	.dma_ring_fft_lo =   VRB2_VfDmaFftDescBaseLoRegVf,
+	.dma_ring_mld_hi =   VRB2_VfDmaMldDescBaseHiRegVf,
+	.dma_ring_mld_lo =   VRB2_VfDmaMldDescBaseLoRegVf,
+	.ring_size =         VRB2_VfQmgrRingSizeVf,
+	.info_ring_hi =      VRB2_VfHiInfoRingBaseHiVf,
+	.info_ring_lo =      VRB2_VfHiInfoRingBaseLoVf,
+	.info_ring_en =      VRB2_VfHiInfoRingIntWrEnVf,
+	.info_ring_ptr =     VRB2_VfHiInfoRingPointerVf,
+	.tail_ptrs_dl5g_hi = VRB2_VfDmaFec5GdlRespPtrHiRegVf,
+	.tail_ptrs_dl5g_lo = VRB2_VfDmaFec5GdlRespPtrLoRegVf,
+	.tail_ptrs_ul5g_hi = VRB2_VfDmaFec5GulRespPtrHiRegVf,
+	.tail_ptrs_ul5g_lo = VRB2_VfDmaFec5GulRespPtrLoRegVf,
+	.tail_ptrs_dl4g_hi = VRB2_VfDmaFec4GdlRespPtrHiRegVf,
+	.tail_ptrs_dl4g_lo = VRB2_VfDmaFec4GdlRespPtrLoRegVf,
+	.tail_ptrs_ul4g_hi = VRB2_VfDmaFec4GulRespPtrHiRegVf,
+	.tail_ptrs_ul4g_lo = VRB2_VfDmaFec4GulRespPtrLoRegVf,
+	.tail_ptrs_fft_hi =  VRB2_VfDmaFftRespPtrHiRegVf,
+	.tail_ptrs_fft_lo =  VRB2_VfDmaFftRespPtrLoRegVf,
+	.tail_ptrs_mld_hi =  VRB2_VfDmaMldRespPtrHiRegVf,
+	.tail_ptrs_mld_lo =  VRB2_VfDmaMldRespPtrLoRegVf,
+	.depth_log0_offset = VRB2_VfQmgrGrpDepthLog20Vf,
+	.depth_log1_offset = VRB2_VfQmgrGrpDepthLog21Vf,
+	.qman_group_func =   VRB2_VfQmgrGrpFunction0Vf,
+	.hi_mode =           VRB2_VfHiMsixVectorMapperVf,
+	.pf_mode =           0,
+	.pmon_ctrl_a =       VRB2_VfPmACntrlRegVf,
+	.pmon_ctrl_b =       VRB2_VfPmBCntrlRegVf,
+	.pmon_ctrl_c =       VRB2_VfPmCCntrlRegVf,
+	.vf2pf_doorbell =    VRB2_VfHiVfToPfDbellVf,
+	.pf2vf_doorbell =    VRB2_VfHiPfToVfDbellVf,
+};
+
+
 #endif /* _VRB_PMD_H_ */
