From patchwork Wed Sep 20 06:22:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131662 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 85332425E9; Wed, 20 Sep 2023 08:22:50 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2367940A8A; Wed, 20 Sep 2023 08:22:28 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 3D52240A79 for ; Wed, 20 Sep 2023 08:22:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695190947; x=1726726947; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+Wh15aWIk/wzfgF29k4NXHSyOqacjwu1IeVkW3v0Muo=; b=dB10+CLhjm34vRhAS1vyn+6+QSotIZPm/Sq2/h8JjRWucPWr0SL8Td4M avQ+Dh41eWnX4aFDtZixjVcxazswUHXr5WDakOHJh4flsJfshWtPls4kA SklhtI0Erxd2HO4hC5KqbisMc9V5/xnLatzd2bEkjTOYW5ZPBN4dIlREw iGtOWNimtLD6nm+MbEFJNjQq++qeGnW7zaL5lpM6qYodvfzMg+2nZNq9c LnljHXSWq1ryTIj5ncxgAsNHkazFC/y1iKbCVZQM0M+8kfGApQxUea2lj eGI1OiFkx49aYyNgI1efTaoYoeFOJ/xhSWmSeLnWJTMCF1Tq+txyibnqu g==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="466453251" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="466453251" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 23:22:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="920154629" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="920154629" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:24 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Madhu Chittim Subject: [PATCH v5 05/11] common/idpf/base: remove mailbox registers Date: Wed, 20 Sep 2023 14:22:30 +0800 Message-Id: <20230920062236.375308-6-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove mailbox register offsets because individual drivers will define the offsets based on how registers address the registers. Signed-off-by: Madhu Chittim Signed-off-by: Simei Su Acked-by: Beilei Xing --- .mailmap | 1 + drivers/common/idpf/base/siov_regs.h | 13 ++----------- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/.mailmap b/.mailmap index 91d8cca78f..d8782cd67e 100644 --- a/.mailmap +++ b/.mailmap @@ -1642,3 +1642,4 @@ Zyta Szpak Jayaprakash Shanmugam Zhenning Xiao Josh Hay +Madhu Chittim diff --git a/drivers/common/idpf/base/siov_regs.h b/drivers/common/idpf/base/siov_regs.h index fad329601a..7e1ae2e300 100644 --- a/drivers/common/idpf/base/siov_regs.h +++ b/drivers/common/idpf/base/siov_regs.h @@ -4,16 +4,6 @@ #ifndef _SIOV_REGS_H_ #define _SIOV_REGS_H_ #define VDEV_MBX_START 0x20000 /* Begin at 128KB */ -#define VDEV_MBX_ATQBAL (VDEV_MBX_START + 0x0000) -#define VDEV_MBX_ATQBAH (VDEV_MBX_START + 0x0004) -#define VDEV_MBX_ATQLEN (VDEV_MBX_START + 0x0008) -#define VDEV_MBX_ATQH (VDEV_MBX_START + 0x000C) -#define VDEV_MBX_ATQT (VDEV_MBX_START + 0x0010) -#define VDEV_MBX_ARQBAL (VDEV_MBX_START + 0x0014) -#define VDEV_MBX_ARQBAH (VDEV_MBX_START + 0x0018) -#define VDEV_MBX_ARQLEN (VDEV_MBX_START + 0x001C) -#define VDEV_MBX_ARQH (VDEV_MBX_START + 0x0020) -#define VDEV_MBX_ARQT (VDEV_MBX_START + 0x0024) #define VDEV_GET_RSTAT 0x21000 /* 132KB for RSTAT */ /* Begin at offset after 1MB (after 256 4k pages) */ @@ -43,5 +33,6 @@ #define VDEV_INT_ITR_1(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x08) #define VDEV_INT_ITR_2(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x0C) -/* Next offset to begin at 42MB (0x2A00000) */ +#define SIOV_REG_BAR_SIZE 0x2A00000 +/* Next offset to begin at 42MB + 4K (0x2A00000 + 0x1000) */ #endif /* _SIOV_REGS_H_ */