From patchwork Mon Sep 18 12:07:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Itamar Gozlan X-Patchwork-Id: 131563 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06ED3425D1; Mon, 18 Sep 2023 14:07:32 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C4402402E2; Mon, 18 Sep 2023 14:07:31 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by mails.dpdk.org (Postfix) with ESMTP id C75034021F for ; Mon, 18 Sep 2023 14:07:30 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=d0dQHzziXGyqELyfxyEpdyKbwQM19wdNr+/6/hcBZ817MHuZIxJG4vjxJulifU7JMEj+WUF0yoIbtbFJXwH0CcluUNOlD96pOaH7DKkin99ardTwUBGlaeBwegch0tKesVwCVc5wGCITonPc+J2pkdBY2cHvqCG84jRU2CqFn4I2wcrzOieIDlStKKUK9KOq9RFURgnP5kGj3t/vqL+vNe9irOzwtCAj4ef+NGTtwfRV5fPkRF1Ej+2/Rzp4+FTIeMevL3CyOisvhKbqeb9nZLwDhk6IzGBEGoqPihuk4z/tVcsGmXhEYl2kNmX6ZnKft5X84BEaddpJOsBzg5C/EQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=J4vaqdCmhooNXc7C2v40622Ui02UYwp9hyapDGx8xHY=; b=RTcJOts6LlDyBB9muGdZC8E3vyoks5FBqXd6oq1/51T8m7nEfJ0SxXi/reLyrtReXjxZk+2+DvPmO9X4Sk0qDveUwajyFHByHQjQLSTtlDgCs374oXZI2XN3fICfeCgkBbxfyIheCxp8w6jJgE+XfJXRLwlNPQqloT11FcFs2j8ZUP89iZ+AGDaElt56pUJipS84WUBntkUnEr/BJmTULAwlfDdaVIxYiUghmkngHmhmU1wNN3HXshonVKTHJkFnx7Qg+t0k1tgJQGuKV2vQFTs9Ls5vOjWIolOiaHe8QSvTNx7psWId8IwCj5GhMWfiU/uRf//l6EsIoJshvql3yQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=J4vaqdCmhooNXc7C2v40622Ui02UYwp9hyapDGx8xHY=; b=KrBk9ziYIHlasArt5hfwZgYQMqeBkZez1rWpvGmRXZjXtfO13zUZLtXoKan5g6njCmjvRZW6HFe9f4+35M+y+Q1gT/x14f4PFI31FztGVUerMqxgP5mPCjKk5rAya3Oz7a3tQ4fa3qvPXlvbu7JkR1w0Z808vbuzBkIMNFqbMEAgLru15/P4ttLLfB9Mux1g5Ky5DhMeAKf7vY/2LJzoK/Mj85ZaFUmAm46oWYkteSsAQ93+9Ysq9aP9C9NACImYgiAFt4ftaXb/Oj3WWEpVLoIbCrrE81Ma/GeOFZW2alH8Z/TzgRn3m+L9koQOUVSuRMUTJyQSzLO+hcoCF6Q6tw== Received: from CYXPR02CA0034.namprd02.prod.outlook.com (2603:10b6:930:cc::22) by DS7PR12MB5720.namprd12.prod.outlook.com (2603:10b6:8:73::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6792.26; Mon, 18 Sep 2023 12:07:29 +0000 Received: from CY4PEPF0000E9CD.namprd03.prod.outlook.com (2603:10b6:930:cc:cafe::db) by CYXPR02CA0034.outlook.office365.com (2603:10b6:930:cc::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6792.27 via Frontend Transport; Mon, 18 Sep 2023 12:07:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000E9CD.mail.protection.outlook.com (10.167.241.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6792.20 via Frontend Transport; Mon, 18 Sep 2023 12:07:28 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 18 Sep 2023 05:07:19 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 18 Sep 2023 05:07:19 -0700 Received: from nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41 via Frontend Transport; Mon, 18 Sep 2023 05:07:17 -0700 From: Itamar Gozlan To: , , , , Matan Azrad , Ori Kam CC: Subject: [PATCH 2/5] net/mlx5/hws: support additional 4 C registers Date: Mon, 18 Sep 2023 15:07:02 +0300 Message-ID: <20230918120705.265025-2-igozlan@nvidia.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230918120705.265025-1-igozlan@nvidia.com> References: <20230918120705.265025-1-igozlan@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|DS7PR12MB5720:EE_ X-MS-Office365-Filtering-Correlation-Id: 6caee545-eaa4-4c26-2212-08dbb83fd45e X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LWnd8gi+tgxW3djiULydC9SmnBJcsASi0OWGwsyiOMXadWG/dHRcCGDopRW9W1Hh+vrDLq2m18sL9xSGMWvhL+RrG+FPjGZxzK06vm7Yg0aIvMptLfyiLtRV7ny4nrWR7vP2ZVsGZOWdGDXj9/jVTiLIXv5ldtXD/ZSc7K2+8OERVFs1WuMfS+bApT2d9dYktTFvTFEdCzC/DkisFSWi8zB1IeriXNcddoPARJ0GgjPzX/o2Jknn2DTsJPixUYmRKZvQvJxeryjqd9PtjumSsUNuBHwP4MU5j+XiJa2LV4/B9rPnnMRBQgelC7MJDPoOCdtYmH/hqayx1OWMJupXjE58s4qQ+WaiShx1zSPEldNL0gLO2T0+Tje3KfomHguyP1LE9kCf1rRhLmu5jAH27oDId/T0MRsUvnOaVK5ai81dL2dpj4JibVMkyq1KxYREA4Lcm8zOvL/urLm3lXvIbN9+rDQhDhF4h7aErd8zwBZTT+qtT6ARi0hK4pfMtNTXHIDFFu5VGykku4dTYEcaMoFfLDtUjdEQnSTats1S2JeF/o5AG7zWA4Wn24nla6vcvJHth+TKddNkXZo4OM0s1LTD9E7Ok5RVCUCEGaDNiw27UwdxiS0dB7b7DocWgxhrddy/eyQ2WMAjp7XOakgDBANNKAo65kAqVWPo6id4HneK+FIW44I91+Qytf+0jVkAAGO+Z5i5nzu3HY/mJzsOt3CAjZ5AbGt6aAEOLTcsG4UDCfGbAOGNmKVe3z82bZ1z X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(136003)(346002)(396003)(376002)(39860400002)(82310400011)(1800799009)(186009)(451199024)(46966006)(36840700001)(40470700004)(7636003)(356005)(26005)(6286002)(82740400003)(2616005)(8936002)(8676002)(4326008)(1076003)(40460700003)(36860700001)(2906002)(36756003)(47076005)(426003)(336012)(40480700001)(55016003)(5660300002)(86362001)(7696005)(478600001)(6666004)(6636002)(316002)(70206006)(70586007)(110136005)(41300700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2023 12:07:28.7040 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6caee545-eaa4-4c26-2212-08dbb83fd45e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5720 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org New connectX devices have 4 additional registers which can be used by the application. This support will allow matching on these new registers. Signed-off-by: Itamar Gozlan --- drivers/common/mlx5/mlx5_prm.h | 4 ++++ drivers/net/mlx5/hws/mlx5dr_definer.c | 16 ++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_definer.h | 4 ++++ 3 files changed, 24 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 51f426c614..4ead9ba2c7 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -857,6 +857,10 @@ enum modify_reg { REG_C_5, REG_C_6, REG_C_7, + REG_C_8, + REG_C_9, + REG_C_10, + REG_C_11, }; /* Modification sub command. */ diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index b82af9d102..2f6f91892b 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -1412,6 +1412,22 @@ mlx5dr_definer_get_register_fc(struct mlx5dr_definer_conv_data *cd, int reg) fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_7]; DR_CALC_SET_HDR(fc, registers, register_c_7); break; + case REG_C_8: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_8]; + DR_CALC_SET_HDR(fc, registers, register_c_8); + break; + case REG_C_9: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_9]; + DR_CALC_SET_HDR(fc, registers, register_c_9); + break; + case REG_C_10: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_10]; + DR_CALC_SET_HDR(fc, registers, register_c_10); + break; + case REG_C_11: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_11]; + DR_CALC_SET_HDR(fc, registers, register_c_11); + break; case REG_A: fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_A]; DR_CALC_SET_HDR(fc, metadata, general_purpose); diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index bf026fa6bb..f5a541bc17 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -100,6 +100,10 @@ enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_REG_5, MLX5DR_DEFINER_FNAME_REG_6, MLX5DR_DEFINER_FNAME_REG_7, + MLX5DR_DEFINER_FNAME_REG_8, + MLX5DR_DEFINER_FNAME_REG_9, + MLX5DR_DEFINER_FNAME_REG_10, + MLX5DR_DEFINER_FNAME_REG_11, MLX5DR_DEFINER_FNAME_REG_A, MLX5DR_DEFINER_FNAME_REG_B, MLX5DR_DEFINER_FNAME_GRE_KEY_PRESENT,