From patchwork Mon Aug 21 17:49:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Prakash Shukla X-Patchwork-Id: 130619 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9E2C6430C3; Mon, 21 Aug 2023 19:50:36 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6492343067; Mon, 21 Aug 2023 19:50:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C8C7842FB2 for ; Mon, 21 Aug 2023 19:50:26 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37LDE6Zv004948 for ; Mon, 21 Aug 2023 10:50:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=2RzzJlSjwG/Rd3vsnqJgyTahbwLwqPF/guc4jA7nppM=; b=SDL45ica/uZPPiU2k8D4DuXV+OyMgI/OyRc1VhjMU1AoHztN0ZCN6sxUJLHjJhaXBKPM dECKPrMNtt228HPOYccWyB7HApodWRj0FBColvAbo4Z62vN3AMXEbSJq4KJYXP+peWKm GikQG2vW2/i5gMNNDTmLKinHB18Vo2knfAdhqDHITlYL/+Wm550oucZuR4rFvJxk1WZi Tay87SBNu5wVrlu58SmW1H/Jb9yPChOZggmY1SsxLlLdcGniJ1d/Z9CDEyqna4Y6jrPn N91qPUlVAhUDyphkjTUPxdWt/IrdfeOU4Keq7HfXE2z6Dm/Lf6yfjnR/VG7mnooLGnro Mg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sju3qp3ax-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 21 Aug 2023 10:50:25 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 21 Aug 2023 10:50:11 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 21 Aug 2023 10:50:11 -0700 Received: from localhost.localdomain (unknown [10.28.36.157]) by maili.marvell.com (Postfix) with ESMTP id 32B683F7092; Mon, 21 Aug 2023 10:50:09 -0700 (PDT) From: Amit Prakash Shukla To: Vamsi Attunuru CC: , Subject: [PATCH v4 7/8] dma/cnxk: add completion ring tail wrap check Date: Mon, 21 Aug 2023 23:19:41 +0530 Message-ID: <20230821174942.3165191-7-amitprakashs@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821174942.3165191-1-amitprakashs@marvell.com> References: <20230818090159.2597468-1-amitprakashs@marvell.com> <20230821174942.3165191-1-amitprakashs@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: xrZYA3qSWrKUDWwPr2W83LrJ_lvNFRmH X-Proofpoint-ORIG-GUID: xrZYA3qSWrKUDWwPr2W83LrJ_lvNFRmH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-21_06,2023-08-18_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vamsi Attunuru Adds a check to avoid tail wrap when completion desc ring is full. Also patch increase max desc size to 2048. Signed-off-by: Vamsi Attunuru --- v2: - Fix for bugs observed in v1. - Squashed few commits. v3: - Resolved review suggestions. - Code improvement. v4: - Resolved checkpatch warnings. drivers/dma/cnxk/cnxk_dmadev.c | 22 ++++++++++++++++++++-- drivers/dma/cnxk/cnxk_dmadev.h | 2 +- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c index 9fb3bb264a..288606bb3d 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.c +++ b/drivers/dma/cnxk/cnxk_dmadev.c @@ -434,6 +434,11 @@ cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, rte_iova_t d header->cn9k.ptr = (uint64_t)comp_ptr; STRM_INC(dpi_conf->c_desc, tail); + if (unlikely(dpi_conf->c_desc.tail == dpi_conf->c_desc.head)) { + STRM_DEC(dpi_conf->c_desc, tail); + return -ENOSPC; + } + header->cn9k.nfst = 1; header->cn9k.nlst = 1; @@ -494,6 +499,11 @@ cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge header->cn9k.ptr = (uint64_t)comp_ptr; STRM_INC(dpi_conf->c_desc, tail); + if (unlikely(dpi_conf->c_desc.tail == dpi_conf->c_desc.head)) { + STRM_DEC(dpi_conf->c_desc, tail); + return -ENOSPC; + } + /* * For inbound case, src pointers are last pointers. * For all other cases, src pointers are first pointers. @@ -561,6 +571,11 @@ cn10k_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, rte_iova_t header->cn10k.ptr = (uint64_t)comp_ptr; STRM_INC(dpi_conf->c_desc, tail); + if (unlikely(dpi_conf->c_desc.tail == dpi_conf->c_desc.head)) { + STRM_DEC(dpi_conf->c_desc, tail); + return -ENOSPC; + } + header->cn10k.nfst = 1; header->cn10k.nlst = 1; @@ -613,6 +628,11 @@ cn10k_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge header->cn10k.ptr = (uint64_t)comp_ptr; STRM_INC(dpi_conf->c_desc, tail); + if (unlikely(dpi_conf->c_desc.tail == dpi_conf->c_desc.head)) { + STRM_DEC(dpi_conf->c_desc, tail); + return -ENOSPC; + } + header->cn10k.nfst = nb_src & DPI_MAX_POINTER; header->cn10k.nlst = nb_dst & DPI_MAX_POINTER; fptr = &src[0]; @@ -695,8 +715,6 @@ cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan, const uint16_t n struct cnxk_dpi_compl_s *comp_ptr; int cnt; - RTE_SET_USED(last_idx); - for (cnt = 0; cnt < nb_cpls; cnt++) { comp_ptr = c_desc->compl_ptr[c_desc->head]; status[cnt] = comp_ptr->cdata; diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h index f375143b16..9c6c898d23 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.h +++ b/drivers/dma/cnxk/cnxk_dmadev.h @@ -9,7 +9,7 @@ #define DPI_MAX_POINTER 15 #define STRM_INC(s, var) ((s).var = ((s).var + 1) & (s).max_cnt) #define STRM_DEC(s, var) ((s).var = ((s).var - 1) == -1 ? (s).max_cnt : ((s).var - 1)) -#define DPI_MAX_DESC 1024 +#define DPI_MAX_DESC 2048 #define DPI_MIN_DESC 2 #define MAX_VCHANS_PER_QUEUE 4