From patchwork Fri May 26 07:38:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xing, Beilei" X-Patchwork-Id: 127541 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 655D342BA9; Fri, 26 May 2023 10:03:05 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0056742BC9; Fri, 26 May 2023 10:02:44 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 920F642D33 for ; Fri, 26 May 2023 10:02:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685088162; x=1716624162; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0J3kCWXQyej1pfHQj5Q0eZprYBPaCR3/PoNyi/pb6ZU=; b=gqJaUz8Ed2dHjFy0Okfn5UAwlbRz8l5H+nhAryKR7hc9+WQO58U4d7JL QFDtmQHGeU8iqseKvpmsyKItz4jhd7W2qMKfQeiwrEAjxOiA9wTsL1oZ9 vZvgpsnzcGamlcxyRIZtQWikhmqJDo/GxVNT8PvxflGVyeaXfoArXzWah 6Q/fmwlJycd5SqM8/vaTCkXTW342ssCop4HxP8PXB0E6xDXxXcmSN7ZZe aIVesndqITrAwi1tFiASpcXzxv+DX2vaatmX55Ud8m0+fWbxdIpTIHUxf fhlfLosIukIN7g9brPGhbnWq60MvHOyGyejyDSLsv4tIx8HKsWGygsoz2 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10721"; a="338742695" X-IronPort-AV: E=Sophos;i="6.00,193,1681196400"; d="scan'208";a="338742695" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2023 01:02:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10721"; a="849483873" X-IronPort-AV: E=Sophos;i="6.00,193,1681196400"; d="scan'208";a="849483873" Received: from dpdk-beileix-3.sh.intel.com ([10.67.110.253]) by fmsmga001.fm.intel.com with ESMTP; 26 May 2023 01:02:39 -0700 From: beilei.xing@intel.com To: jingjing.wu@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing , Xiao Wang Subject: [PATCH v4 04/13] net/cpfl: support hairpin queue capbility get Date: Fri, 26 May 2023 07:38:41 +0000 Message-Id: <20230526073850.101079-5-beilei.xing@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20230526073850.101079-1-beilei.xing@intel.com> References: <20230519073116.56749-1-beilei.xing@intel.com> <20230526073850.101079-1-beilei.xing@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Beilei Xing This patch adds hairpin_cap_get ops support. Signed-off-by: Xiao Wang Signed-off-by: Mingxia Liu Signed-off-by: Beilei Xing --- drivers/net/cpfl/cpfl_ethdev.c | 18 ++++++++++++++++++ drivers/net/cpfl/cpfl_rxtx.h | 3 +++ 2 files changed, 21 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index c1273a7478..40b4515539 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -154,6 +154,23 @@ cpfl_dev_link_update(struct rte_eth_dev *dev, return rte_eth_linkstatus_set(dev, &new_link); } +static int +cpfl_hairpin_cap_get(struct rte_eth_dev *dev, + struct rte_eth_hairpin_cap *cap) +{ + struct cpfl_vport *cpfl_vport = dev->data->dev_private; + + if (cpfl_vport->p2p_q_chunks_info == NULL) + return -ENOTSUP; + + cap->max_nb_queues = CPFL_MAX_P2P_NB_QUEUES; + cap->max_rx_2_tx = CPFL_MAX_HAIRPINQ_RX_2_TX; + cap->max_tx_2_rx = CPFL_MAX_HAIRPINQ_TX_2_RX; + cap->max_nb_desc = CPFL_MAX_HAIRPINQ_NB_DESC; + + return 0; +} + static int cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) { @@ -904,6 +921,7 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .xstats_get = cpfl_dev_xstats_get, .xstats_get_names = cpfl_dev_xstats_get_names, .xstats_reset = cpfl_dev_xstats_reset, + .hairpin_cap_get = cpfl_hairpin_cap_get, }; static int diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h index 1fe65778f0..a4a164d462 100644 --- a/drivers/net/cpfl/cpfl_rxtx.h +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -14,6 +14,9 @@ #define CPFL_MAX_RING_DESC 4096 #define CPFL_DMA_MEM_ALIGN 4096 +#define CPFL_MAX_HAIRPINQ_RX_2_TX 1 +#define CPFL_MAX_HAIRPINQ_TX_2_RX 1 +#define CPFL_MAX_HAIRPINQ_NB_DESC 1024 #define CPFL_MAX_P2P_NB_QUEUES 16 #define CPFL_P2P_NB_RX_BUFQ 1 #define CPFL_P2P_NB_TX_COMPLQ 1