[v3,05/11] net/bnxt: update ULP shared session support

Message ID 20230504173612.17696-6-ajit.khaparde@broadcom.com (mailing list archive)
State Superseded, archived
Delegated to: Ajit Khaparde
Headers
Series sync Truflow support with latest release |

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Ajit Khaparde May 4, 2023, 5:36 p.m. UTC
  From: Randy Schacher <stuart.schacher@broadcom.com>

- Update ulp generic templates
- Modify code to support shared sessions

This should allow more than one application to share a TruFlow
session.

Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/bnxt.h                       |    16 +-
 drivers/net/bnxt/bnxt_ethdev.c                |     8 +-
 drivers/net/bnxt/bnxt_reps.c                  |     4 +-
 drivers/net/bnxt/tf_core/tf_rm.c              |    28 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c            |   548 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp.h            |   109 +-
 .../bnxt/tf_ulp/generic_templates/meson.build |    18 +-
 .../generic_templates/ulp_template_db_act.c   |  7000 +++-
 .../generic_templates/ulp_template_db_class.c | 33556 +++++++++++-----
 .../generic_templates/ulp_template_db_enum.h  |  4366 +-
 .../generic_templates/ulp_template_db_field.h |   689 +-
 .../generic_templates/ulp_template_db_tbl.c   | 16055 ++++++--
 .../ulp_template_db_thor_act.c                |  8714 ++--
 .../ulp_template_db_thor_class.c              | 10746 +++--
 .../ulp_template_db_wh_plus_act.c             |  1157 +-
 .../ulp_template_db_wh_plus_class.c           |   288 +-
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c       |    16 +-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c          |    25 +-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h          |     7 +-
 drivers/net/bnxt/tf_ulp/ulp_flow_db.c         |    29 +-
 drivers/net/bnxt/tf_ulp/ulp_flow_db.h         |    15 +-
 drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c          |    10 +-
 drivers/net/bnxt/tf_ulp/ulp_mapper.c          |   281 +-
 drivers/net/bnxt/tf_ulp/ulp_port_db.c         |     6 +-
 drivers/net/bnxt/tf_ulp/ulp_port_db.h         |    10 +-
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c      |    17 +-
 drivers/net/bnxt/tf_ulp/ulp_template_struct.h |    22 +-
 27 files changed, 63079 insertions(+), 20661 deletions(-)
  

Patch

diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 2bccdec7e0..bb2e7fe003 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -1,5 +1,5 @@ 
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
  * All rights reserved.
  */
 
@@ -633,6 +633,13 @@  struct bnxt_ring_stats {
 	uint64_t	rx_agg_aborts;
 };
 
+enum bnxt_session_type {
+	BNXT_SESSION_TYPE_REGULAR = 0,
+	BNXT_SESSION_TYPE_SHARED_COMMON,
+	BNXT_SESSION_TYPE_SHARED_WC,
+	BNXT_SESSION_TYPE_LAST
+};
+
 struct bnxt {
 	void				*bar0;
 
@@ -690,6 +697,9 @@  struct bnxt {
 #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED		BIT(1)
 #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp)	\
 	((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED)
+#define BNXT_FLAGS2_TESTPMD_EN                  BIT(3)
+#define BNXT_TESTPMD_EN(bp)                     \
+	((bp)->flags2 & BNXT_FLAGS2_TESTPMD_EN)
 
 	uint16_t		chip_num;
 #define CHIP_NUM_58818		0xd818
@@ -855,8 +865,7 @@  struct bnxt {
 	uint16_t		func_svif;
 	uint16_t		port_svif;
 
-	struct tf		tfp;
-	struct tf		tfp_shared;
+	struct tf		tfp[BNXT_SESSION_TYPE_LAST];
 	struct bnxt_ulp_context	*ulp_ctx;
 	struct bnxt_flow_stat_info *flow_stat;
 	uint16_t		max_num_kflows;
@@ -1044,4 +1053,5 @@  int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
 int bnxt_dev_start_op(struct rte_eth_dev *eth_dev);
 int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev);
 void bnxt_handle_vf_cfg_change(void *arg);
+struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type);
 #endif
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index ef7b8859d9..bcde44bb14 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1,5 +1,5 @@ 
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
  * All rights reserved.
  */
 
@@ -6415,6 +6415,12 @@  bool is_bnxt_supported(struct rte_eth_dev *dev)
 	return is_device_supported(dev, &bnxt_rte_pmd);
 }
 
+struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type)
+{
+	return (type >= BNXT_SESSION_TYPE_LAST) ?
+		&bp->tfp[BNXT_SESSION_TYPE_REGULAR] : &bp->tfp[type];
+}
+
 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 8a5b777793..78337431af 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -1,5 +1,5 @@ 
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
  * All rights reserved.
  */
 
@@ -327,7 +327,7 @@  static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 		(void)bnxt_hwrm_cfa_pair_free(parent_bp, vfr);
 
 	/* Update the ULP portdata base with the new VFR interface */
-	rc = ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev);
+	rc = ulp_port_db_port_update(parent_bp->ulp_ctx, vfr_ethdev);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Failed to update ulp port details vfr:%u\n",
 			    vfr->vf_id);
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 1fccb698d0..9b85f5397d 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -364,8 +364,7 @@  tf_rm_update_parent_reservations(struct tf *tfp,
 				 struct tf_rm_element_cfg *cfg,
 				 uint16_t *alloc_cnt,
 				 uint16_t num_elements,
-				 uint16_t *req_cnt,
-				 bool shared_session)
+				 uint16_t *req_cnt)
 {
 	int parent, child;
 	const char *type_str = NULL;
@@ -376,11 +375,7 @@  tf_rm_update_parent_reservations(struct tf *tfp,
 
 		/* If I am a parent */
 		if (cfg[parent].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) {
-			uint8_t p_slices = 1;
-
-			/* Shared session doesn't support slices */
-			if (!shared_session)
-				p_slices = cfg[parent].slices;
+			uint8_t p_slices = cfg[parent].slices;
 
 			RTE_ASSERT(p_slices);
 
@@ -402,12 +397,9 @@  tf_rm_update_parent_reservations(struct tf *tfp,
 				    TF_RM_ELEM_CFG_HCAPI_BA_CHILD &&
 				    cfg[child].parent_subtype == parent &&
 				    alloc_cnt[child]) {
-					uint8_t c_slices = 1;
+					uint8_t c_slices = cfg[child].slices;
 					uint16_t cnt = 0;
 
-					if (!shared_session)
-						c_slices = cfg[child].slices;
-
 					RTE_ASSERT(c_slices);
 
 					dev->ops->tf_dev_get_resource_str(tfp,
@@ -429,7 +421,7 @@  tf_rm_update_parent_reservations(struct tf *tfp,
 				}
 			}
 			/* Save the parent count to be requested */
-			req_cnt[parent] = combined_cnt;
+			req_cnt[parent] = combined_cnt * 2;
 		}
 	}
 	return 0;
@@ -452,7 +444,6 @@  tf_rm_create_db(struct tf *tfp,
 	struct tf_rm_new_db *rm_db;
 	struct tf_rm_element *db;
 	uint32_t pool_size;
-	bool shared_session = 0;
 
 	TF_CHECK_PARMS2(tfp, parms);
 
@@ -505,15 +496,12 @@  tf_rm_create_db(struct tf *tfp,
 	tfp_memcpy(req_cnt, parms->alloc_cnt,
 		   parms->num_elements * sizeof(uint16_t));
 
-	shared_session = tf_session_is_shared_session(tfs);
-
 	/* Update the req_cnt based upon the element configuration
 	 */
 	tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
 					 parms->alloc_cnt,
 					 parms->num_elements,
-					 req_cnt,
-					 shared_session);
+					 req_cnt);
 
 	/* Process capabilities against DB requirements. However, as a
 	 * DB can hold elements that are not HCAPI we can reduce the
@@ -733,7 +721,6 @@  tf_rm_create_db_no_reservation(struct tf *tfp,
 	struct tf_rm_new_db *rm_db;
 	struct tf_rm_element *db;
 	uint32_t pool_size;
-	bool shared_session = 0;
 
 	TF_CHECK_PARMS2(tfp, parms);
 
@@ -763,15 +750,12 @@  tf_rm_create_db_no_reservation(struct tf *tfp,
 	tfp_memcpy(req_cnt, parms->alloc_cnt,
 		   parms->num_elements * sizeof(uint16_t));
 
-	shared_session = tf_session_is_shared_session(tfs);
-
 	/* Update the req_cnt based upon the element configuration
 	 */
 	tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
 					 parms->alloc_cnt,
 					 parms->num_elements,
-					 req_cnt,
-					 shared_session);
+					 req_cnt);
 
 	/* Process capabilities against DB requirements. However, as a
 	 * DB can hold elements that are not HCAPI we can reduce the
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 8513ee06a9..109bd0652a 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -1,5 +1,5 @@ 
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
  * All rights reserved.
  */
 
@@ -13,6 +13,7 @@ 
 #include "bnxt.h"
 #include "bnxt_ulp.h"
 #include "bnxt_tf_common.h"
+#include "hsi_struct_def_dpdk.h"
 #include "tf_core.h"
 #include "tf_ext_flow_handle.h"
 
@@ -26,6 +27,7 @@ 
 #include "ulp_tun.h"
 #include "ulp_ha_mgr.h"
 #include "bnxt_tf_pmd_shim.h"
+#include "ulp_template_db_tbl.h"
 
 /* Linked list of all TF sessions. */
 STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list =
@@ -91,6 +93,17 @@  bnxt_ulp_app_cap_list_get(uint32_t *num_entries)
 	return ulp_app_cap_info_list;
 }
 
+struct bnxt_ulp_shared_act_info *
+bnxt_ulp_shared_act_info_get(uint32_t *num_entries)
+{
+	if (!num_entries)
+		return NULL;
+
+	*num_entries = BNXT_ULP_GEN_TBL_MAX_SZ;
+
+	return ulp_shared_act_info;
+}
+
 static struct bnxt_ulp_resource_resv_info *
 bnxt_ulp_app_resource_resv_list_get(uint32_t *num_entries)
 {
@@ -122,6 +135,7 @@  static int32_t
 bnxt_ulp_named_resources_calc(struct bnxt_ulp_context *ulp_ctx,
 			      struct bnxt_ulp_glb_resource_info *info,
 			      uint32_t num,
+			      enum bnxt_ulp_session_type stype,
 			      struct tf_session_resources *res)
 {
 	uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST, res_type, i;
@@ -149,6 +163,11 @@  bnxt_ulp_named_resources_calc(struct bnxt_ulp_context *ulp_ctx,
 	for (i = 0; i < num; i++) {
 		if (dev_id != info[i].device_id || app_id != info[i].app_id)
 			continue;
+		/* check to see if the session type matches only then include */
+		if ((stype || info[i].session_type) &&
+		    !(info[i].session_type & stype))
+			continue;
+
 		dir = info[i].direction;
 		res_type = info[i].resource_type;
 
@@ -179,6 +198,7 @@  static int32_t
 bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx,
 				struct bnxt_ulp_resource_resv_info *info,
 				uint32_t num,
+				enum bnxt_ulp_session_type stype,
 				struct tf_session_resources *res)
 {
 	uint32_t dev_id, res_type, i;
@@ -206,6 +226,12 @@  bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx,
 	for (i = 0; i < num; i++) {
 		if (app_id != info[i].app_id || dev_id != info[i].device_id)
 			continue;
+
+		/* check to see if the session type matches only then include */
+		if ((stype || info[i].session_type) &&
+		    !(info[i].session_type & stype))
+			continue;
+
 		dir = info[i].direction;
 		res_type = info[i].resource_type;
 
@@ -231,6 +257,7 @@  bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx,
 
 static int32_t
 bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx,
+			  enum bnxt_ulp_session_type stype,
 			  struct tf_session_resources *res)
 {
 	struct bnxt_ulp_resource_resv_info *unnamed = NULL;
@@ -242,13 +269,18 @@  bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx,
 		return -EINVAL;
 	}
 
+	/* use DEFAULT_NON_HA instead of DEFAULT resources if HA is disabled */
+	if (ULP_APP_HA_IS_DYNAMIC(ulp_ctx))
+		stype = ulp_ctx->cfg_data->def_session_type;
+
 	unnamed = bnxt_ulp_resource_resv_list_get(&unum);
 	if (unnamed == NULL) {
 		BNXT_TF_DBG(ERR, "Unable to get resource resv list.\n");
 		return -EINVAL;
 	}
 
-	rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, res);
+	rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, stype,
+					     res);
 	if (rc)
 		BNXT_TF_DBG(ERR, "Unable to calc resources for session.\n");
 
@@ -257,6 +289,7 @@  bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx,
 
 static int32_t
 bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
+					 enum bnxt_ulp_session_type stype,
 					 struct tf_session_resources *res)
 {
 	struct bnxt_ulp_resource_resv_info *unnamed;
@@ -272,6 +305,10 @@  bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
 	/* Make sure the resources are zero before accumulating. */
 	memset(res, 0, sizeof(struct tf_session_resources));
 
+	if (bnxt_ulp_cntxt_ha_enabled(ulp_ctx) &&
+	    stype == BNXT_ULP_SESSION_TYPE_SHARED)
+		stype = ulp_ctx->cfg_data->hu_session_type;
+
 	/*
 	 * Shared resources are comprised of both named and unnamed resources.
 	 * First get the unnamed counts, and then add the named to the result.
@@ -282,9 +319,11 @@  bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
 		BNXT_TF_DBG(ERR, "Unable to get shared resource resv list.\n");
 		return -EINVAL;
 	}
-	rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, res);
+	rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, stype,
+					     res);
 	if (rc) {
-		BNXT_TF_DBG(ERR, "Unable to calc resources for shared session.\n");
+		BNXT_TF_DBG(ERR,
+			    "Unable to calc resources for shared session.\n");
 		return -EINVAL;
 	}
 
@@ -294,7 +333,7 @@  bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
 		BNXT_TF_DBG(ERR, "Unable to get app global resource list\n");
 		return -EINVAL;
 	}
-	rc = bnxt_ulp_named_resources_calc(ulp_ctx, named, nnum, res);
+	rc = bnxt_ulp_named_resources_calc(ulp_ctx, named, nnum, stype, res);
 	if (rc)
 		BNXT_TF_DBG(ERR, "Unable to calc named resources\n");
 
@@ -356,17 +395,127 @@  bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
 	return 0;
 }
 
+/* Function to set the number for vxlan_ip (custom vxlan) port into the context */
+int
+bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
+			   uint32_t vxlan_ip_port)
+{
+	if (!ulp_ctx || !ulp_ctx->cfg_data)
+		return -EINVAL;
+
+	ulp_ctx->cfg_data->vxlan_ip_port = vxlan_ip_port;
+
+	return 0;
+}
+
+/* Function to retrieve the vxlan_ip (custom vxlan) port from the context. */
+unsigned int
+bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx)
+{
+	if (!ulp_ctx || !ulp_ctx->cfg_data)
+		return 0;
+
+	return (unsigned int)ulp_ctx->cfg_data->vxlan_ip_port;
+}
+
+/* Function to set the number for vxlan port into the context */
+int
+bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx,
+			uint32_t vxlan_port)
+{
+	if (!ulp_ctx || !ulp_ctx->cfg_data)
+		return -EINVAL;
+
+	ulp_ctx->cfg_data->vxlan_port = vxlan_port;
+
+	return 0;
+}
+
+/* Function to retrieve the vxlan port from the context. */
+unsigned int
+bnxt_ulp_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx)
+{
+	if (!ulp_ctx || !ulp_ctx->cfg_data)
+		return 0;
+
+	return (unsigned int)ulp_ctx->cfg_data->vxlan_port;
+}
+
+static inline uint32_t
+bnxt_ulp_session_idx_get(enum bnxt_ulp_session_type session_type) {
+	if (session_type & BNXT_ULP_SESSION_TYPE_SHARED)
+		return 1;
+	else if (session_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+		return 2;
+	return 0;
+}
+
+/* Function to set the tfp session details in session */
+static int32_t
+bnxt_ulp_session_tfp_set(struct bnxt_ulp_session_state *session,
+			 enum bnxt_ulp_session_type session_type,
+			 struct tf *tfp)
+{
+	uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+	int32_t rc = 0;
+
+	if (!session->session_opened[idx]) {
+		session->g_tfp[idx] = rte_zmalloc("bnxt_ulp_session_tfp",
+						  sizeof(struct tf), 0);
+		if (!session->g_tfp[idx]) {
+			BNXT_TF_DBG(DEBUG, "Failed to alloc session tfp\n");
+			return -ENOMEM;
+		}
+		session->g_tfp[idx]->session  = tfp->session;
+		session->session_opened[idx] = 1;
+	}
+	return rc;
+}
+
+/* Function to get the tfp session details in session */
+static struct tf_session_info *
+bnxt_ulp_session_tfp_get(struct bnxt_ulp_session_state *session,
+			 enum bnxt_ulp_session_type session_type)
+{
+	uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+
+	if (session->session_opened[idx])
+		return session->g_tfp[idx]->session;
+	return NULL;
+}
+
+static uint32_t
+bnxt_ulp_session_is_open(struct bnxt_ulp_session_state *session,
+			 enum bnxt_ulp_session_type session_type)
+{
+	uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+
+	return session->session_opened[idx];
+}
+
+/* Function to reset the tfp session details in session */
+static void
+bnxt_ulp_session_tfp_reset(struct bnxt_ulp_session_state *session,
+			   enum bnxt_ulp_session_type session_type)
+{
+	uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+
+	if (session->session_opened[idx]) {
+		session->session_opened[idx] = 0;
+		rte_free(session->g_tfp[idx]);
+		session->g_tfp[idx] = NULL;
+	}
+}
+
 static void
 ulp_ctx_shared_session_close(struct bnxt *bp,
+			     enum bnxt_ulp_session_type session_type,
 			     struct bnxt_ulp_session_state *session)
 {
 	struct tf *tfp;
 	int32_t rc;
 
-	if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
-		return;
-
-	tfp = bnxt_ulp_cntxt_shared_tfp_get(bp->ulp_ctx);
+	tfp = bnxt_ulp_cntxt_tfp_get(bp->ulp_ctx, session_type);
 	if (!tfp) {
 		/*
 		 * Log it under debug since this is likely a case of the
@@ -380,29 +529,26 @@  ulp_ctx_shared_session_close(struct bnxt *bp,
 	if (rc)
 		BNXT_TF_DBG(ERR, "Failed to close the shared session rc=%d.\n",
 			    rc);
-	(void)bnxt_ulp_cntxt_shared_tfp_set(bp->ulp_ctx, NULL);
-
-	session->g_shared_tfp.session = NULL;
+	(void)bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, NULL);
+	bnxt_ulp_session_tfp_reset(session, session_type);
 }
 
 static int32_t
 ulp_ctx_shared_session_open(struct bnxt *bp,
+			    enum bnxt_ulp_session_type session_type,
 			    struct bnxt_ulp_session_state *session)
 {
 	struct rte_eth_dev *ethdev = bp->eth_dev;
 	struct tf_session_resources *resources;
 	struct tf_open_session_parms parms;
-	size_t copy_nbytes;
+	size_t nb;
 	uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
 	int32_t	rc = 0;
 	uint8_t app_id;
-
-	/* only perform this if shared session is enabled. */
-	if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
-		return 0;
+	struct tf *tfp;
+	uint8_t pool_id;
 
 	memset(&parms, 0, sizeof(parms));
-
 	rc = rte_eth_dev_get_name_by_port(ethdev->data->port_id,
 					  parms.ctrl_chan_name);
 	if (rc) {
@@ -416,21 +562,39 @@  ulp_ctx_shared_session_open(struct bnxt *bp,
 	 * Need to account for size of ctrl_chan_name and 1 extra for Null
 	 * terminator
 	 */
-	copy_nbytes = sizeof(parms.ctrl_chan_name) -
-		strlen(parms.ctrl_chan_name) - 1;
+	nb = sizeof(parms.ctrl_chan_name) - strlen(parms.ctrl_chan_name) - 1;
 
 	/*
 	 * Build the ctrl_chan_name with shared token.
 	 * When HA is enabled, the WC TCAM needs extra management by the core,
 	 * so add the wc_tcam string to the control channel.
 	 */
-	if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx))
-		strncat(parms.ctrl_chan_name, "-tf_shared-wc_tcam",
-			copy_nbytes);
-	else
-		strncat(parms.ctrl_chan_name, "-tf_shared", copy_nbytes);
+	pool_id = bp->ulp_ctx->cfg_data->ha_pool_id;
+	if (!bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+		if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx))
+			strncat(parms.ctrl_chan_name, "-tf_shared-wc_tcam", nb);
+		else
+			strncat(parms.ctrl_chan_name, "-tf_shared", nb);
+	} else if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+		if (session_type == BNXT_ULP_SESSION_TYPE_SHARED) {
+			strncat(parms.ctrl_chan_name, "-tf_shared", nb);
+		} else if (session_type == BNXT_ULP_SESSION_TYPE_SHARED_WC) {
+			char session_pool_name[64];
+
+			sprintf(session_pool_name, "-tf_shared-pool%d",
+				pool_id);
+
+			if (nb >= strlen(session_pool_name)) {
+				strncat(parms.ctrl_chan_name, session_pool_name, nb);
+			} else {
+				BNXT_TF_DBG(ERR, "No space left for session_name\n");
+				return -EINVAL;
+			}
+		}
+	}
 
-	rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, resources);
+	rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, session_type,
+						      resources);
 	if (rc)
 		return rc;
 
@@ -446,32 +610,15 @@  ulp_ctx_shared_session_open(struct bnxt *bp,
 		return rc;
 	}
 
-	switch (ulp_dev_id) {
-	case BNXT_ULP_DEVICE_ID_WH_PLUS:
-		parms.device_type = TF_DEVICE_TYPE_P5;
-		break;
-	case BNXT_ULP_DEVICE_ID_STINGRAY:
-		parms.device_type = TF_DEVICE_TYPE_SR;
-		break;
-	case BNXT_ULP_DEVICE_ID_THOR:
-		parms.device_type = TF_DEVICE_TYPE_P4;
-		break;
-	default:
-		BNXT_TF_DBG(ERR, "Unable to determine dev for opening session.\n");
-		return rc;
-	}
-
+	tfp = bnxt_ulp_bp_tfp_get(bp, session_type);
+	parms.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id);
 	parms.bp = bp;
-	if (app_id == 0)
-		parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
-	else
-		parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
 
 	/*
 	 * Open the session here, but the collect the resources during the
 	 * mapper initialization.
 	 */
-	rc = tf_open_session(&bp->tfp_shared, &parms);
+	rc = tf_open_session(tfp, &parms);
 	if (rc)
 		return rc;
 
@@ -481,40 +628,70 @@  ulp_ctx_shared_session_open(struct bnxt *bp,
 		BNXT_TF_DBG(DEBUG, "Shared session attached.\n");
 
 	/* Save the shared session in global data */
-	if (!session->g_shared_tfp.session)
-		session->g_shared_tfp.session = bp->tfp_shared.session;
+	rc = bnxt_ulp_session_tfp_set(session, session_type, tfp);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to add shared tfp to session\n");
+		return rc;
+	}
 
-	rc = bnxt_ulp_cntxt_shared_tfp_set(bp->ulp_ctx, &bp->tfp_shared);
-	if (rc)
+	rc = bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, tfp);
+	if (rc) {
 		BNXT_TF_DBG(ERR, "Failed to add shared tfp to ulp (%d)\n", rc);
+		return rc;
+	}
 
 	return rc;
 }
 
 static int32_t
 ulp_ctx_shared_session_attach(struct bnxt *bp,
-			      struct bnxt_ulp_session_state *session)
+			      struct bnxt_ulp_session_state *ses)
 {
+	enum bnxt_ulp_session_type type;
+	struct tf *tfp;
 	int32_t rc = 0;
 
 	/* Simply return success if shared session not enabled */
 	if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) {
-		bp->tfp_shared.session = session->g_shared_tfp.session;
-		rc = ulp_ctx_shared_session_open(bp, session);
+		type = BNXT_ULP_SESSION_TYPE_SHARED;
+		tfp = bnxt_ulp_bp_tfp_get(bp, type);
+		tfp->session = bnxt_ulp_session_tfp_get(ses, type);
+		rc = ulp_ctx_shared_session_open(bp, type, ses);
+	}
+
+	if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+		type = BNXT_ULP_SESSION_TYPE_SHARED_WC;
+		tfp = bnxt_ulp_bp_tfp_get(bp, type);
+		tfp->session = bnxt_ulp_session_tfp_get(ses, type);
+		rc = ulp_ctx_shared_session_open(bp, type, ses);
 	}
 
+	if (!rc)
+		bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true);
+
 	return rc;
 }
 
 static void
 ulp_ctx_shared_session_detach(struct bnxt *bp)
 {
+	struct tf *tfp;
+
 	if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) {
-		if (bp->tfp_shared.session) {
-			tf_close_session(&bp->tfp_shared);
-			bp->tfp_shared.session = NULL;
+		tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED);
+		if (tfp->session) {
+			tf_close_session(tfp);
+			tfp->session = NULL;
 		}
 	}
+	if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+		tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED_WC);
+		if (tfp->session) {
+			tf_close_session(tfp);
+			tfp->session = NULL;
+		}
+	}
+	bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false);
 }
 
 /*
@@ -538,6 +715,7 @@  ulp_ctx_session_open(struct bnxt *bp,
 	struct tf_session_resources	*resources;
 	uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
 	uint8_t app_id;
+	struct tf *tfp;
 
 	memset(&params, 0, sizeof(params));
 
@@ -561,43 +739,29 @@  ulp_ctx_session_open(struct bnxt *bp,
 		return rc;
 	}
 
-	switch (ulp_dev_id) {
-	case BNXT_ULP_DEVICE_ID_WH_PLUS:
-		params.device_type = TF_DEVICE_TYPE_P5;
-		break;
-	case BNXT_ULP_DEVICE_ID_STINGRAY:
-		params.device_type = TF_DEVICE_TYPE_SR;
-		break;
-	case BNXT_ULP_DEVICE_ID_THOR:
-		params.device_type = TF_DEVICE_TYPE_P4;
-		break;
-	default:
-		BNXT_TF_DBG(ERR, "Unable to determine device for opening session.\n");
-		return rc;
-	}
-
+	params.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id);
 	resources = &params.resources;
-	rc = bnxt_ulp_tf_resources_get(bp->ulp_ctx, resources);
+	rc = bnxt_ulp_tf_resources_get(bp->ulp_ctx,
+				       BNXT_ULP_SESSION_TYPE_DEFAULT,
+				       resources);
 	if (rc)
 		return rc;
 
 	params.bp = bp;
-	if (app_id == 0)
-		params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
-	else
-		params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
 
-	rc = tf_open_session(&bp->tfp, &params);
+	tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+	rc = tf_open_session(tfp, &params);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Failed to open TF session - %s, rc = %d\n",
 			    params.ctrl_chan_name, rc);
 		return -EINVAL;
 	}
-	if (!session->session_opened) {
-		session->session_opened = 1;
-		session->g_tfp = rte_zmalloc("bnxt_ulp_session_tfp",
-					     sizeof(struct tf), 0);
-		session->g_tfp->session = bp->tfp.session;
+	rc = bnxt_ulp_session_tfp_set(session,
+				      BNXT_ULP_SESSION_TYPE_DEFAULT, tfp);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to set TF session - %s, rc = %d\n",
+			    params.ctrl_chan_name, rc);
+		return -EINVAL;
 	}
 	return rc;
 }
@@ -610,12 +774,14 @@  static void
 ulp_ctx_session_close(struct bnxt *bp,
 		      struct bnxt_ulp_session_state *session)
 {
+	struct tf *tfp;
+
 	/* close the session in the hardware */
-	if (session->session_opened)
-		tf_close_session(&bp->tfp);
-	session->session_opened = 0;
-	rte_free(session->g_tfp);
-	session->g_tfp = NULL;
+	if (bnxt_ulp_session_is_open(session, BNXT_ULP_SESSION_TYPE_DEFAULT)) {
+		tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+		tf_close_session(tfp);
+	}
+	bnxt_ulp_session_tfp_reset(session, BNXT_ULP_SESSION_TYPE_DEFAULT);
 }
 
 static void
@@ -678,6 +844,7 @@  ulp_eem_tbl_scope_init(struct bnxt *bp)
 	struct bnxt_ulp_device_params *dparms;
 	enum bnxt_ulp_flow_mem_type mtype;
 	uint32_t dev_id;
+	struct tf *tfp;
 	int rc;
 
 	/* Get the dev specific number of flows that needed to be supported. */
@@ -700,12 +867,14 @@  ulp_eem_tbl_scope_init(struct bnxt *bp)
 	}
 
 	bnxt_init_tbl_scope_parms(bp, &params);
-	rc = tf_alloc_tbl_scope(&bp->tfp, &params);
+	tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+	rc = tf_alloc_tbl_scope(tfp, &params);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Unable to allocate eem table scope rc = %d\n",
 			    rc);
 		return rc;
 	}
+
 	rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Unable to set table scope id\n");
@@ -729,7 +898,7 @@  ulp_eem_tbl_scope_deinit(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx)
 	if (!ulp_ctx || !ulp_ctx->cfg_data)
 		return -EINVAL;
 
-	tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+	tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
 	if (!tfp) {
 		BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
 		return -EINVAL;
@@ -777,7 +946,16 @@  ulp_ctx_deinit(struct bnxt *bp,
 	ulp_ctx_session_close(bp, session);
 
 	/* The shared session must be closed last. */
-	ulp_ctx_shared_session_close(bp, session);
+	if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
+		ulp_ctx_shared_session_close(bp, BNXT_ULP_SESSION_TYPE_SHARED,
+					     session);
+
+	if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx))
+		ulp_ctx_shared_session_close(bp,
+					     BNXT_ULP_SESSION_TYPE_SHARED_WC,
+					     session);
+
+	bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false);
 
 	/* Free the contents */
 	if (session->cfg_data) {
@@ -796,6 +974,8 @@  ulp_ctx_init(struct bnxt *bp,
 	struct bnxt_ulp_data	*ulp_data;
 	int32_t			rc = 0;
 	enum bnxt_ulp_device_id devid;
+	enum bnxt_ulp_session_type stype;
+	struct tf *tfp;
 
 	/* Initialize the context entries list */
 	bnxt_ulp_cntxt_list_init();
@@ -851,22 +1031,42 @@  ulp_ctx_init(struct bnxt *bp,
 	 * Shared session must be created before first regular session but after
 	 * the ulp_ctx is valid.
 	 */
-	rc = ulp_ctx_shared_session_open(bp, session);
-	if (rc) {
-		BNXT_TF_DBG(ERR, "Unable to open shared session (%d)\n", rc);
-		goto error_deinit;
+	if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) {
+		rc = ulp_ctx_shared_session_open(bp,
+						 BNXT_ULP_SESSION_TYPE_SHARED,
+						 session);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Unable to open shared session (%d)\n",
+				    rc);
+			goto error_deinit;
+		}
 	}
 
+	/* Multiple session support */
+	if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+		stype = BNXT_ULP_SESSION_TYPE_SHARED_WC;
+		rc = ulp_ctx_shared_session_open(bp, stype, session);
+		if (rc) {
+			BNXT_TF_DBG(ERR,
+				    "Unable to open shared wc session (%d)\n",
+				    rc);
+			goto error_deinit;
+		}
+	}
+	bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true);
+
+
 	/* Open the ulp session. */
 	rc = ulp_ctx_session_open(bp, session);
 	if (rc)
 		goto error_deinit;
 
-	bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
+	tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+	bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp);
 	return rc;
 
 error_deinit:
-	session->session_opened = 1;
+	session->session_opened[BNXT_ULP_SESSION_TYPE_DEFAULT] = 1;
 	(void)ulp_ctx_deinit(bp, session);
 	return rc;
 }
@@ -932,6 +1132,7 @@  ulp_ctx_attach(struct bnxt *bp,
 {
 	int32_t rc = 0;
 	uint32_t flags, dev_id = BNXT_ULP_DEVICE_ID_LAST;
+	struct tf *tfp;
 	uint8_t app_id;
 
 	/* Increment the ulp context data reference count usage. */
@@ -939,7 +1140,9 @@  ulp_ctx_attach(struct bnxt *bp,
 	bp->ulp_ctx->cfg_data->ref_cnt++;
 
 	/* update the session details in bnxt tfp */
-	bp->tfp.session = session->g_tfp->session;
+	tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+	tfp->session = bnxt_ulp_session_tfp_get(session,
+						BNXT_ULP_SESSION_TYPE_DEFAULT);
 
 	/* Add the context to the context entries list */
 	rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx);
@@ -975,20 +1178,23 @@  ulp_ctx_attach(struct bnxt *bp,
 	rc = ulp_ctx_session_open(bp, session);
 	if (rc) {
 		PMD_DRV_LOG(ERR, "Failed to open ctxt session, rc:%d\n", rc);
-		bp->tfp.session = NULL;
+		tfp->session = NULL;
 		return rc;
 	}
 
-	bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
+	bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp);
 	return rc;
 }
 
 static void
 ulp_ctx_detach(struct bnxt *bp)
 {
-	if (bp->tfp.session) {
-		tf_close_session(&bp->tfp);
-		bp->tfp.session = NULL;
+	struct tf *tfp;
+
+	tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+	if (tfp->session) {
+		tf_close_session(tfp);
+		tfp->session = NULL;
 	}
 }
 
@@ -1121,6 +1327,7 @@  bnxt_ulp_global_cfg_update(struct bnxt *bp,
 	uint32_t global_cfg = 0;
 	int rc;
 	struct tf_global_cfg_parms parms = { 0 };
+	struct tf *tfp;
 
 	/* Initialize the params */
 	parms.dir = dir,
@@ -1129,7 +1336,8 @@  bnxt_ulp_global_cfg_update(struct bnxt *bp,
 	parms.config = (uint8_t *)&global_cfg,
 	parms.config_sz_in_bytes = sizeof(global_cfg);
 
-	rc = tf_get_global_cfg(&bp->tfp, &parms);
+	tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+	rc = tf_get_global_cfg(tfp, &parms);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Failed to get global cfg 0x%x rc:%d\n",
 			    type, rc);
@@ -1142,7 +1350,7 @@  bnxt_ulp_global_cfg_update(struct bnxt *bp,
 		global_cfg &= ~value;
 
 	/* SET the register RE_CFA_REG_ACT_TECT */
-	rc = tf_set_global_cfg(&bp->tfp, &parms);
+	rc = tf_set_global_cfg(tfp, &parms);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Failed to set global cfg 0x%x rc:%d\n",
 			    type, rc);
@@ -1473,7 +1681,7 @@  bnxt_ulp_port_init(struct bnxt *bp)
 	}
 
 	/* update the port database for the given interface */
-	rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp->eth_dev);
+	rc = ulp_port_db_port_update(bp->ulp_ctx, bp->eth_dev);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Failed to update port database\n");
 		goto jump_to_error;
@@ -1624,6 +1832,12 @@  bnxt_ulp_cntxt_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx)
 	return ULP_SHARED_SESSION_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags);
 }
 
+bool
+bnxt_ulp_cntxt_multi_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx)
+{
+	return ULP_MULTI_SHARED_IS_SUPPORTED(ulp_ctx);
+}
+
 int32_t
 bnxt_ulp_cntxt_app_id_set(struct bnxt_ulp_context *ulp_ctx, uint8_t app_id)
 {
@@ -1721,74 +1935,86 @@  bnxt_ulp_cntxt_tbl_scope_id_set(struct bnxt_ulp_context *ulp_ctx,
 	return -EINVAL;
 }
 
-/* Function to set the shared tfp session details from the ulp context. */
-int32_t
-bnxt_ulp_cntxt_shared_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp)
-{
-	if (!ulp) {
-		BNXT_TF_DBG(ERR, "Invalid arguments\n");
-		return -EINVAL;
-	}
-
-	if (tfp == NULL) {
-		if (ulp->cfg_data->num_shared_clients > 0)
-			ulp->cfg_data->num_shared_clients--;
-	} else {
-		ulp->cfg_data->num_shared_clients++;
-	}
-
-	ulp->g_shared_tfp = tfp;
-	return 0;
-}
-
-/* Function to get the shared tfp session details from the ulp context. */
-struct tf *
-bnxt_ulp_cntxt_shared_tfp_get(struct bnxt_ulp_context *ulp)
+/* Function to get the number of shared clients attached */
+uint8_t
+bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp)
 {
-	if (!ulp) {
+	if (ulp == NULL || ulp->cfg_data == NULL) {
 		BNXT_TF_DBG(ERR, "Invalid arguments\n");
-		return NULL;
+		return 0;
 	}
-	return ulp->g_shared_tfp;
+	return ulp->cfg_data->num_shared_clients;
 }
 
-/* Function to get the number of shared clients attached */
-uint8_t
-bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp)
+/* Function to set the number of shared clients */
+int
+bnxt_ulp_cntxt_num_shared_clients_set(struct bnxt_ulp_context *ulp, bool incr)
 {
 	if (ulp == NULL || ulp->cfg_data == NULL) {
 		BNXT_TF_DBG(ERR, "Invalid arguments\n");
 		return 0;
 	}
-	return ulp->cfg_data->num_shared_clients;
+	if (incr)
+		ulp->cfg_data->num_shared_clients++;
+	else if (ulp->cfg_data->num_shared_clients)
+		ulp->cfg_data->num_shared_clients--;
+
+	BNXT_TF_DBG(DEBUG, "%d:clients(%d)\n", incr,
+		    ulp->cfg_data->num_shared_clients);
+
+	return 0;
 }
 
 /* Function to set the tfp session details from the ulp context. */
 int32_t
-bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp)
+bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp,
+		       enum bnxt_ulp_session_type s_type,
+		       struct tf *tfp)
 {
+	uint32_t idx = 0;
+
 	if (!ulp) {
 		BNXT_TF_DBG(ERR, "Invalid arguments\n");
 		return -EINVAL;
 	}
+	if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) {
+		if (s_type & BNXT_ULP_SESSION_TYPE_SHARED)
+			idx = 1;
+		else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+			idx = 2;
+
+	} else {
+		if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) ||
+		    (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC))
+			idx = 1;
+	}
 
-	ulp->g_tfp = tfp;
+	ulp->g_tfp[idx] = tfp;
 	return 0;
 }
 
 /* Function to get the tfp session details from the ulp context. */
 struct tf *
 bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp,
-		       enum bnxt_ulp_shared_session shared)
+		       enum bnxt_ulp_session_type s_type)
 {
+	uint32_t idx = 0;
+
 	if (!ulp) {
 		BNXT_TF_DBG(ERR, "Invalid arguments\n");
 		return NULL;
 	}
-	if (shared)
-		return ulp->g_shared_tfp;
-	else
-		return ulp->g_tfp;
+	if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) {
+		if (s_type & BNXT_ULP_SESSION_TYPE_SHARED)
+			idx = 1;
+		else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+			idx = 2;
+	} else {
+		if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) ||
+		    (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC))
+			idx = 1;
+	}
+	return ulp->g_tfp[idx];
 }
 
 /*
@@ -2079,3 +2305,41 @@  bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp)
 
 	return ulp->cfg_data->app_tun;
 }
+
+/* Function to convert ulp dev id to regular dev id. */
+uint32_t
+bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id)
+{
+	enum tf_device_type type = 0;
+
+	switch (ulp_dev_id) {
+	case BNXT_ULP_DEVICE_ID_WH_PLUS:
+		type = TF_DEVICE_TYPE_P4;
+		break;
+	case BNXT_ULP_DEVICE_ID_STINGRAY:
+		type = TF_DEVICE_TYPE_SR;
+		break;
+	case BNXT_ULP_DEVICE_ID_THOR:
+		type = TF_DEVICE_TYPE_P5;
+		break;
+	default:
+		BNXT_TF_DBG(ERR, "Invalid device id\n");
+		break;
+	}
+	return type;
+}
+
+struct tf*
+bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type)
+{
+	enum bnxt_session_type btype;
+
+	if (type & BNXT_ULP_SESSION_TYPE_SHARED)
+		btype = BNXT_SESSION_TYPE_SHARED_COMMON;
+	else if (type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+		btype = BNXT_SESSION_TYPE_SHARED_WC;
+	else
+		btype = BNXT_SESSION_TYPE_REGULAR;
+
+	return bnxt_get_tfp_session(bp, btype);
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 906d933af5..9b30851b13 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -1,5 +1,5 @@ 
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
  * All rights reserved.
  */
 
@@ -35,6 +35,11 @@ 
 #define BNXT_ULP_HIGH_AVAIL_ENABLED	0x8
 #define BNXT_ULP_APP_UNICAST_ONLY	0x10
 #define BNXT_ULP_APP_SOCKET_DIRECT	0x20
+#define BNXT_ULP_APP_TOS_PROTO_SUPPORT	0x40
+#define BNXT_ULP_APP_BC_MC_SUPPORT	0x80
+#define BNXT_ULP_CUST_VXLAN_SUPPORT	0x100
+#define BNXT_ULP_MULTI_SHARED_SUPPORT	0x200
+#define BNXT_ULP_APP_HA_DYNAMIC		0x400
 
 #define ULP_VF_REP_IS_ENABLED(flag)	((flag) & BNXT_ULP_VF_REP_ENABLED)
 #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\
@@ -43,6 +48,17 @@ 
 						 BNXT_ULP_APP_DEV_UNSUPPORTED)
 #define ULP_HIGH_AVAIL_IS_ENABLED(flag)	((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED)
 #define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT)
+#define ULP_APP_TOS_PROTO_SUPPORT(ctx)	((ctx)->cfg_data->ulp_flags &\
+					BNXT_ULP_APP_TOS_PROTO_SUPPORT)
+#define ULP_APP_BC_MC_SUPPORT(ctx)	((ctx)->cfg_data->ulp_flags &\
+					BNXT_ULP_APP_BC_MC_SUPPORT)
+#define ULP_MULTI_SHARED_IS_SUPPORTED(ctx)	((ctx)->cfg_data->ulp_flags &\
+					BNXT_ULP_MULTI_SHARED_SUPPORT)
+#define ULP_APP_HA_IS_DYNAMIC(ctx)	((ctx)->cfg_data->ulp_flags &\
+					BNXT_ULP_APP_HA_DYNAMIC)
+
+#define ULP_APP_CUST_VXLAN_SUPPORT(ctx)	   ((ctx)->cfg_data->vxlan_port != 0)
+#define ULP_APP_CUST_VXLAN_IP_SUPPORT(ctx) ((ctx)->cfg_data->vxlan_ip_port != 0)
 
 enum bnxt_ulp_flow_mem_type {
 	BNXT_ULP_FLOW_MEM_TYPE_INT = 0,
@@ -95,12 +111,19 @@  struct bnxt_ulp_data {
 	uint8_t				app_id;
 	uint8_t				num_shared_clients;
 	struct bnxt_flow_app_tun_ent	app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];
+	uint32_t			vxlan_port;
+	uint32_t			vxlan_ip_port;
+	uint8_t				hu_reg_state;
+	uint8_t				hu_reg_cnt;
+	uint32_t			hu_session_type;
+	uint8_t				ha_pool_id;
+	enum bnxt_ulp_session_type	def_session_type;
 };
 
+#define BNXT_ULP_SESSION_MAX 3
 struct bnxt_ulp_context {
 	struct bnxt_ulp_data	*cfg_data;
-	struct tf		*g_tfp;
-	struct tf		*g_shared_tfp;
+	struct tf		*g_tfp[BNXT_ULP_SESSION_MAX];
 };
 
 struct bnxt_ulp_pci_info {
@@ -110,13 +133,12 @@  struct bnxt_ulp_pci_info {
 
 struct bnxt_ulp_session_state {
 	STAILQ_ENTRY(bnxt_ulp_session_state)	next;
-	bool					bnxt_ulp_init;
-	pthread_mutex_t				bnxt_ulp_mutex;
-	struct bnxt_ulp_pci_info		pci_info;
-	struct bnxt_ulp_data			*cfg_data;
-	struct tf				*g_tfp;
-	struct tf				g_shared_tfp;
-	uint32_t				session_opened;
+	bool				bnxt_ulp_init;
+	pthread_mutex_t			bnxt_ulp_mutex;
+	struct bnxt_ulp_pci_info	pci_info;
+	struct bnxt_ulp_data		*cfg_data;
+	struct tf			*g_tfp[BNXT_ULP_SESSION_MAX];
+	uint32_t			session_opened[BNXT_ULP_SESSION_MAX];
 };
 
 /* ULP flow id structure */
@@ -172,20 +194,14 @@  bnxt_ulp_cntxt_tbl_scope_id_get(struct bnxt_ulp_context *ulp_ctx,
 
 /* Function to set the tfp session details in the ulp context. */
 int32_t
-bnxt_ulp_cntxt_shared_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp);
-
-/* Function to get the tfp session details from ulp context. */
-struct tf *
-bnxt_ulp_cntxt_shared_tfp_get(struct bnxt_ulp_context *ulp);
-
-/* Function to set the tfp session details in the ulp context. */
-int32_t
-bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp);
+bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp,
+		       enum bnxt_ulp_session_type s_type,
+		       struct tf *tfp);
 
 /* Function to get the tfp session details from ulp context. */
 struct tf *
 bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp,
-		       enum bnxt_ulp_shared_session shared);
+		       enum bnxt_ulp_session_type s_type);
 
 /* Get the device table entry based on the device id. */
 struct bnxt_ulp_device_params *
@@ -238,6 +254,7 @@  int32_t
 ulp_default_flow_create(struct rte_eth_dev *eth_dev,
 			struct ulp_tlv_param *param_list,
 			uint32_t ulp_class_tid,
+			uint16_t port_id,
 			uint32_t *flow_id);
 
 /* Function to destroy default flows. */
@@ -274,6 +291,20 @@  bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context	*ulp_ctx);
 void
 bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context	*ulp_ctx);
 
+int32_t
+bnxt_get_action_handle_type(const struct rte_flow_action_handle *handle,
+			    uint32_t *action_handle_type);
+
+struct bnxt_ulp_shared_act_info *
+bnxt_ulp_shared_act_info_get(uint32_t *num_entries);
+
+int32_t
+bnxt_get_action_handle_direction(const struct rte_flow_action_handle *handle,
+				 uint32_t *dir);
+
+uint32_t
+bnxt_get_action_handle_index(const struct rte_flow_action_handle *handle);
+
 struct bnxt_ulp_glb_resource_info *
 bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries);
 
@@ -286,6 +317,9 @@  bnxt_ulp_cntxt_app_id_get(struct bnxt_ulp_context *ulp_ctx, uint8_t *app_id);
 bool
 bnxt_ulp_cntxt_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx);
 
+bool
+bnxt_ulp_cntxt_multi_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx);
+
 struct bnxt_ulp_app_capabilities_info *
 bnxt_ulp_app_cap_list_get(uint32_t *num_entries);
 
@@ -315,6 +349,41 @@  bnxt_ulp_cntxt_entry_release(void);
 uint8_t
 bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx);
 
+int
+bnxt_ulp_cntxt_num_shared_clients_set(struct bnxt_ulp_context *ulp_ctx,
+				      bool incr);
+
 struct bnxt_flow_app_tun_ent *
 bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp);
+
+/* Function to get the truflow app id. This defined in the build file */
+uint32_t
+bnxt_ulp_default_app_id_get(void);
+
+int
+bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx,
+			uint32_t vxlan_port);
+unsigned int
+bnxt_ulp_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx);
+int
+bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
+			   uint32_t vxlan_ip_port);
+unsigned int
+bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx);
+
+uint32_t
+bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id);
+
+int32_t
+bnxt_ulp_ha_reg_set(struct bnxt_ulp_context *ulp_ctx,
+		    uint8_t state, uint8_t cnt);
+
+uint32_t
+bnxt_ulp_ha_reg_state_get(struct bnxt_ulp_context *ulp_ctx);
+
+uint32_t
+bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx);
+
+struct tf*
+bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type);
 #endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
index 4ace838a3c..b1b92e61ab 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
@@ -2,15 +2,13 @@ 
 # Copyright(c) 2018 Intel Corporation
 # Copyright(c) 2020 Broadcom
 
-#Include the folder for headers
 includes += include_directories('.')
-
-#Add the source files
 sources += files(
-        'ulp_template_db_class.c',
-        'ulp_template_db_act.c',
-        'ulp_template_db_tbl.c',
-        'ulp_template_db_wh_plus_act.c',
-        'ulp_template_db_wh_plus_class.c',
-        'ulp_template_db_thor_act.c',
-        'ulp_template_db_thor_class.c')
+	'ulp_template_db_class.c',
+	'ulp_template_db_act.c',
+	'ulp_template_db_tbl.c',
+	'ulp_template_db_wh_plus_act.c',
+	'ulp_template_db_wh_plus_class.c',
+	'ulp_template_db_thor_act.c',
+	'ulp_template_db_thor_class.c')
+
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
index ce878d8e02..c626fc64f5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
@@ -1,10 +1,8 @@ 
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
  * All rights reserved.
  */
 
-/* date: Wed Aug 25 14:37:06 2021 */
-
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
 #include "ulp_template_struct.h"
@@ -16,98 +14,550 @@ 
  */
 uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_ACT_HID_0000] = 1,
-	[BNXT_ULP_ACT_HID_0001] = 2,
-	[BNXT_ULP_ACT_HID_0400] = 3,
-	[BNXT_ULP_ACT_HID_01ab] = 4,
-	[BNXT_ULP_ACT_HID_0010] = 5,
-	[BNXT_ULP_ACT_HID_05ab] = 6,
-	[BNXT_ULP_ACT_HID_01bb] = 7,
-	[BNXT_ULP_ACT_HID_0002] = 8,
-	[BNXT_ULP_ACT_HID_0003] = 9,
-	[BNXT_ULP_ACT_HID_0402] = 10,
-	[BNXT_ULP_ACT_HID_01ad] = 11,
-	[BNXT_ULP_ACT_HID_0012] = 12,
-	[BNXT_ULP_ACT_HID_05ad] = 13,
-	[BNXT_ULP_ACT_HID_01bd] = 14,
-	[BNXT_ULP_ACT_HID_0613] = 15,
-	[BNXT_ULP_ACT_HID_02a9] = 16,
-	[BNXT_ULP_ACT_HID_0054] = 17,
-	[BNXT_ULP_ACT_HID_0622] = 18,
-	[BNXT_ULP_ACT_HID_0454] = 19,
-	[BNXT_ULP_ACT_HID_0064] = 20,
-	[BNXT_ULP_ACT_HID_0614] = 21,
-	[BNXT_ULP_ACT_HID_0615] = 22,
-	[BNXT_ULP_ACT_HID_02ab] = 23,
-	[BNXT_ULP_ACT_HID_0056] = 24,
-	[BNXT_ULP_ACT_HID_0624] = 25,
-	[BNXT_ULP_ACT_HID_0456] = 26,
-	[BNXT_ULP_ACT_HID_0066] = 27,
-	[BNXT_ULP_ACT_HID_048d] = 28,
-	[BNXT_ULP_ACT_HID_048f] = 29,
-	[BNXT_ULP_ACT_HID_04bc] = 30,
-	[BNXT_ULP_ACT_HID_00a9] = 31,
-	[BNXT_ULP_ACT_HID_020f] = 32,
-	[BNXT_ULP_ACT_HID_0153] = 33,
-	[BNXT_ULP_ACT_HID_04a9] = 34,
-	[BNXT_ULP_ACT_HID_01fc] = 35,
-	[BNXT_ULP_ACT_HID_04be] = 36,
-	[BNXT_ULP_ACT_HID_00ab] = 37,
-	[BNXT_ULP_ACT_HID_0211] = 38,
-	[BNXT_ULP_ACT_HID_0155] = 39,
-	[BNXT_ULP_ACT_HID_04ab] = 40,
-	[BNXT_ULP_ACT_HID_01fe] = 41,
-	[BNXT_ULP_ACT_HID_0667] = 42,
-	[BNXT_ULP_ACT_HID_0254] = 43,
-	[BNXT_ULP_ACT_HID_03ba] = 44,
-	[BNXT_ULP_ACT_HID_02fe] = 45,
-	[BNXT_ULP_ACT_HID_0654] = 46,
-	[BNXT_ULP_ACT_HID_03a7] = 47,
-	[BNXT_ULP_ACT_HID_0669] = 48,
-	[BNXT_ULP_ACT_HID_0256] = 49,
-	[BNXT_ULP_ACT_HID_03bc] = 50,
-	[BNXT_ULP_ACT_HID_0300] = 51,
-	[BNXT_ULP_ACT_HID_0656] = 52,
-	[BNXT_ULP_ACT_HID_03a9] = 53,
-	[BNXT_ULP_ACT_HID_021b] = 54,
-	[BNXT_ULP_ACT_HID_021c] = 55,
-	[BNXT_ULP_ACT_HID_021e] = 56,
-	[BNXT_ULP_ACT_HID_063f] = 57,
-	[BNXT_ULP_ACT_HID_0510] = 58,
-	[BNXT_ULP_ACT_HID_03c6] = 59,
-	[BNXT_ULP_ACT_HID_0082] = 60,
-	[BNXT_ULP_ACT_HID_06bb] = 61,
-	[BNXT_ULP_ACT_HID_021d] = 62,
-	[BNXT_ULP_ACT_HID_0641] = 63,
-	[BNXT_ULP_ACT_HID_0512] = 64,
-	[BNXT_ULP_ACT_HID_03c8] = 65,
-	[BNXT_ULP_ACT_HID_0084] = 66,
-	[BNXT_ULP_ACT_HID_06bd] = 67,
-	[BNXT_ULP_ACT_HID_06d7] = 68,
-	[BNXT_ULP_ACT_HID_02c4] = 69,
-	[BNXT_ULP_ACT_HID_042a] = 70,
-	[BNXT_ULP_ACT_HID_036e] = 71,
-	[BNXT_ULP_ACT_HID_06c4] = 72,
-	[BNXT_ULP_ACT_HID_0417] = 73,
-	[BNXT_ULP_ACT_HID_06d9] = 74,
-	[BNXT_ULP_ACT_HID_02c6] = 75,
-	[BNXT_ULP_ACT_HID_042c] = 76,
-	[BNXT_ULP_ACT_HID_0370] = 77,
-	[BNXT_ULP_ACT_HID_06c6] = 78,
-	[BNXT_ULP_ACT_HID_0419] = 79,
-	[BNXT_ULP_ACT_HID_0119] = 80,
-	[BNXT_ULP_ACT_HID_046f] = 81,
-	[BNXT_ULP_ACT_HID_05d5] = 82,
-	[BNXT_ULP_ACT_HID_0519] = 83,
-	[BNXT_ULP_ACT_HID_0106] = 84,
-	[BNXT_ULP_ACT_HID_05c2] = 85,
-	[BNXT_ULP_ACT_HID_011b] = 86,
-	[BNXT_ULP_ACT_HID_0471] = 87,
-	[BNXT_ULP_ACT_HID_05d7] = 88,
-	[BNXT_ULP_ACT_HID_051b] = 89,
-	[BNXT_ULP_ACT_HID_0108] = 90,
-	[BNXT_ULP_ACT_HID_05c4] = 91,
-	[BNXT_ULP_ACT_HID_00a2] = 92,
-	[BNXT_ULP_ACT_HID_00a4] = 93
+	[BNXT_ULP_ACT_HID_0008] = 2,
+	[BNXT_ULP_ACT_HID_2000] = 3,
+	[BNXT_ULP_ACT_HID_1988] = 4,
+	[BNXT_ULP_ACT_HID_0080] = 5,
+	[BNXT_ULP_ACT_HID_3988] = 6,
+	[BNXT_ULP_ACT_HID_1a08] = 7,
+	[BNXT_ULP_ACT_HID_0010] = 8,
+	[BNXT_ULP_ACT_HID_0040] = 9,
+	[BNXT_ULP_ACT_HID_0050] = 10,
+	[BNXT_ULP_ACT_HID_0018] = 11,
+	[BNXT_ULP_ACT_HID_2010] = 12,
+	[BNXT_ULP_ACT_HID_1998] = 13,
+	[BNXT_ULP_ACT_HID_0090] = 14,
+	[BNXT_ULP_ACT_HID_3998] = 15,
+	[BNXT_ULP_ACT_HID_1a18] = 16,
+	[BNXT_ULP_ACT_HID_32ea] = 17,
+	[BNXT_ULP_ACT_HID_32f2] = 18,
+	[BNXT_ULP_ACT_HID_52ea] = 19,
+	[BNXT_ULP_ACT_HID_4c72] = 20,
+	[BNXT_ULP_ACT_HID_336a] = 21,
+	[BNXT_ULP_ACT_HID_6c72] = 22,
+	[BNXT_ULP_ACT_HID_4cf2] = 23,
+	[BNXT_ULP_ACT_HID_32fa] = 24,
+	[BNXT_ULP_ACT_HID_3302] = 25,
+	[BNXT_ULP_ACT_HID_52fa] = 26,
+	[BNXT_ULP_ACT_HID_4c82] = 27,
+	[BNXT_ULP_ACT_HID_337a] = 28,
+	[BNXT_ULP_ACT_HID_6c82] = 29,
+	[BNXT_ULP_ACT_HID_4d02] = 30,
+	[BNXT_ULP_ACT_HID_0808] = 31,
+	[BNXT_ULP_ACT_HID_1008] = 32,
+	[BNXT_ULP_ACT_HID_1808] = 33,
+	[BNXT_ULP_ACT_HID_0818] = 34,
+	[BNXT_ULP_ACT_HID_1018] = 35,
+	[BNXT_ULP_ACT_HID_1818] = 36,
+	[BNXT_ULP_ACT_HID_0880] = 37,
+	[BNXT_ULP_ACT_HID_1080] = 38,
+	[BNXT_ULP_ACT_HID_1880] = 39,
+	[BNXT_ULP_ACT_HID_0890] = 40,
+	[BNXT_ULP_ACT_HID_1090] = 41,
+	[BNXT_ULP_ACT_HID_1890] = 42,
+	[BNXT_ULP_ACT_HID_3af2] = 43,
+	[BNXT_ULP_ACT_HID_42f2] = 44,
+	[BNXT_ULP_ACT_HID_4af2] = 45,
+	[BNXT_ULP_ACT_HID_3b02] = 46,
+	[BNXT_ULP_ACT_HID_4302] = 47,
+	[BNXT_ULP_ACT_HID_4b02] = 48,
+	[BNXT_ULP_ACT_HID_3b6a] = 49,
+	[BNXT_ULP_ACT_HID_436a] = 50,
+	[BNXT_ULP_ACT_HID_4b6a] = 51,
+	[BNXT_ULP_ACT_HID_3b7a] = 52,
+	[BNXT_ULP_ACT_HID_437a] = 53,
+	[BNXT_ULP_ACT_HID_4b7a] = 54,
+	[BNXT_ULP_ACT_HID_640d] = 55,
+	[BNXT_ULP_ACT_HID_641d] = 56,
+	[BNXT_ULP_ACT_HID_071a] = 57,
+	[BNXT_ULP_ACT_HID_0800] = 58,
+	[BNXT_ULP_ACT_HID_1000] = 59,
+	[BNXT_ULP_ACT_HID_1800] = 60,
+	[BNXT_ULP_ACT_HID_0810] = 61,
+	[BNXT_ULP_ACT_HID_1010] = 62,
+	[BNXT_ULP_ACT_HID_1810] = 63,
+	[BNXT_ULP_ACT_HID_1110] = 64,
+	[BNXT_ULP_ACT_HID_4420] = 65,
+	[BNXT_ULP_ACT_HID_2220] = 66,
+	[BNXT_ULP_ACT_HID_0c84] = 67,
+	[BNXT_ULP_ACT_HID_3f94] = 68,
+	[BNXT_ULP_ACT_HID_3330] = 69,
+	[BNXT_ULP_ACT_HID_50a4] = 70,
+	[BNXT_ULP_ACT_HID_1910] = 71,
+	[BNXT_ULP_ACT_HID_4c20] = 72,
+	[BNXT_ULP_ACT_HID_2a20] = 73,
+	[BNXT_ULP_ACT_HID_1484] = 74,
+	[BNXT_ULP_ACT_HID_4794] = 75,
+	[BNXT_ULP_ACT_HID_3b30] = 76,
+	[BNXT_ULP_ACT_HID_58a4] = 77,
+	[BNXT_ULP_ACT_HID_2110] = 78,
+	[BNXT_ULP_ACT_HID_5420] = 79,
+	[BNXT_ULP_ACT_HID_3220] = 80,
+	[BNXT_ULP_ACT_HID_1c84] = 81,
+	[BNXT_ULP_ACT_HID_4f94] = 82,
+	[BNXT_ULP_ACT_HID_4330] = 83,
+	[BNXT_ULP_ACT_HID_60a4] = 84,
+	[BNXT_ULP_ACT_HID_2910] = 85,
+	[BNXT_ULP_ACT_HID_5c20] = 86,
+	[BNXT_ULP_ACT_HID_3a20] = 87,
+	[BNXT_ULP_ACT_HID_2484] = 88,
+	[BNXT_ULP_ACT_HID_5794] = 89,
+	[BNXT_ULP_ACT_HID_4b30] = 90,
+	[BNXT_ULP_ACT_HID_68a4] = 91,
+	[BNXT_ULP_ACT_HID_1120] = 92,
+	[BNXT_ULP_ACT_HID_4430] = 93,
+	[BNXT_ULP_ACT_HID_2230] = 94,
+	[BNXT_ULP_ACT_HID_0c94] = 95,
+	[BNXT_ULP_ACT_HID_3fa4] = 96,
+	[BNXT_ULP_ACT_HID_3340] = 97,
+	[BNXT_ULP_ACT_HID_50b4] = 98,
+	[BNXT_ULP_ACT_HID_1920] = 99,
+	[BNXT_ULP_ACT_HID_4c30] = 100,
+	[BNXT_ULP_ACT_HID_2a30] = 101,
+	[BNXT_ULP_ACT_HID_1494] = 102,
+	[BNXT_ULP_ACT_HID_47a4] = 103,
+	[BNXT_ULP_ACT_HID_3b40] = 104,
+	[BNXT_ULP_ACT_HID_58b4] = 105,
+	[BNXT_ULP_ACT_HID_2120] = 106,
+	[BNXT_ULP_ACT_HID_5430] = 107,
+	[BNXT_ULP_ACT_HID_3230] = 108,
+	[BNXT_ULP_ACT_HID_1c94] = 109,
+	[BNXT_ULP_ACT_HID_4fa4] = 110,
+	[BNXT_ULP_ACT_HID_4340] = 111,
+	[BNXT_ULP_ACT_HID_60b4] = 112,
+	[BNXT_ULP_ACT_HID_2920] = 113,
+	[BNXT_ULP_ACT_HID_5c30] = 114,
+	[BNXT_ULP_ACT_HID_3a30] = 115,
+	[BNXT_ULP_ACT_HID_2494] = 116,
+	[BNXT_ULP_ACT_HID_57a4] = 117,
+	[BNXT_ULP_ACT_HID_4b40] = 118,
+	[BNXT_ULP_ACT_HID_68b4] = 119,
+	[BNXT_ULP_ACT_HID_2a98] = 120,
+	[BNXT_ULP_ACT_HID_5da8] = 121,
+	[BNXT_ULP_ACT_HID_3ba8] = 122,
+	[BNXT_ULP_ACT_HID_260c] = 123,
+	[BNXT_ULP_ACT_HID_591c] = 124,
+	[BNXT_ULP_ACT_HID_6a2c] = 125,
+	[BNXT_ULP_ACT_HID_2aa8] = 126,
+	[BNXT_ULP_ACT_HID_5db8] = 127,
+	[BNXT_ULP_ACT_HID_3bb8] = 128,
+	[BNXT_ULP_ACT_HID_261c] = 129,
+	[BNXT_ULP_ACT_HID_592c] = 130,
+	[BNXT_ULP_ACT_HID_6a3c] = 131,
+	[BNXT_ULP_ACT_HID_3298] = 132,
+	[BNXT_ULP_ACT_HID_65a8] = 133,
+	[BNXT_ULP_ACT_HID_43a8] = 134,
+	[BNXT_ULP_ACT_HID_2e0c] = 135,
+	[BNXT_ULP_ACT_HID_611c] = 136,
+	[BNXT_ULP_ACT_HID_722c] = 137,
+	[BNXT_ULP_ACT_HID_32a8] = 138,
+	[BNXT_ULP_ACT_HID_65b8] = 139,
+	[BNXT_ULP_ACT_HID_43b8] = 140,
+	[BNXT_ULP_ACT_HID_2e1c] = 141,
+	[BNXT_ULP_ACT_HID_612c] = 142,
+	[BNXT_ULP_ACT_HID_723c] = 143,
+	[BNXT_ULP_ACT_HID_3a98] = 144,
+	[BNXT_ULP_ACT_HID_6da8] = 145,
+	[BNXT_ULP_ACT_HID_4ba8] = 146,
+	[BNXT_ULP_ACT_HID_360c] = 147,
+	[BNXT_ULP_ACT_HID_691c] = 148,
+	[BNXT_ULP_ACT_HID_7a2c] = 149,
+	[BNXT_ULP_ACT_HID_3aa8] = 150,
+	[BNXT_ULP_ACT_HID_6db8] = 151,
+	[BNXT_ULP_ACT_HID_4bb8] = 152,
+	[BNXT_ULP_ACT_HID_361c] = 153,
+	[BNXT_ULP_ACT_HID_692c] = 154,
+	[BNXT_ULP_ACT_HID_7a3c] = 155,
+	[BNXT_ULP_ACT_HID_4298] = 156,
+	[BNXT_ULP_ACT_HID_75a8] = 157,
+	[BNXT_ULP_ACT_HID_53a8] = 158,
+	[BNXT_ULP_ACT_HID_3e0c] = 159,
+	[BNXT_ULP_ACT_HID_711c] = 160,
+	[BNXT_ULP_ACT_HID_0670] = 161,
+	[BNXT_ULP_ACT_HID_42a8] = 162,
+	[BNXT_ULP_ACT_HID_75b8] = 163,
+	[BNXT_ULP_ACT_HID_53b8] = 164,
+	[BNXT_ULP_ACT_HID_3e1c] = 165,
+	[BNXT_ULP_ACT_HID_712c] = 166,
+	[BNXT_ULP_ACT_HID_0680] = 167,
+	[BNXT_ULP_ACT_HID_3aea] = 168,
+	[BNXT_ULP_ACT_HID_42ea] = 169,
+	[BNXT_ULP_ACT_HID_4aea] = 170,
+	[BNXT_ULP_ACT_HID_3afa] = 171,
+	[BNXT_ULP_ACT_HID_42fa] = 172,
+	[BNXT_ULP_ACT_HID_4afa] = 173,
+	[BNXT_ULP_ACT_HID_43fa] = 174,
+	[BNXT_ULP_ACT_HID_770a] = 175,
+	[BNXT_ULP_ACT_HID_550a] = 176,
+	[BNXT_ULP_ACT_HID_3f6e] = 177,
+	[BNXT_ULP_ACT_HID_727e] = 178,
+	[BNXT_ULP_ACT_HID_661a] = 179,
+	[BNXT_ULP_ACT_HID_07d2] = 180,
+	[BNXT_ULP_ACT_HID_4bfa] = 181,
+	[BNXT_ULP_ACT_HID_034e] = 182,
+	[BNXT_ULP_ACT_HID_5d0a] = 183,
+	[BNXT_ULP_ACT_HID_476e] = 184,
+	[BNXT_ULP_ACT_HID_7a7e] = 185,
+	[BNXT_ULP_ACT_HID_6e1a] = 186,
+	[BNXT_ULP_ACT_HID_0fd2] = 187,
+	[BNXT_ULP_ACT_HID_53fa] = 188,
+	[BNXT_ULP_ACT_HID_0b4e] = 189,
+	[BNXT_ULP_ACT_HID_650a] = 190,
+	[BNXT_ULP_ACT_HID_4f6e] = 191,
+	[BNXT_ULP_ACT_HID_06c2] = 192,
+	[BNXT_ULP_ACT_HID_761a] = 193,
+	[BNXT_ULP_ACT_HID_17d2] = 194,
+	[BNXT_ULP_ACT_HID_5bfa] = 195,
+	[BNXT_ULP_ACT_HID_134e] = 196,
+	[BNXT_ULP_ACT_HID_6d0a] = 197,
+	[BNXT_ULP_ACT_HID_576e] = 198,
+	[BNXT_ULP_ACT_HID_0ec2] = 199,
+	[BNXT_ULP_ACT_HID_025e] = 200,
+	[BNXT_ULP_ACT_HID_1fd2] = 201,
+	[BNXT_ULP_ACT_HID_440a] = 202,
+	[BNXT_ULP_ACT_HID_771a] = 203,
+	[BNXT_ULP_ACT_HID_551a] = 204,
+	[BNXT_ULP_ACT_HID_3f7e] = 205,
+	[BNXT_ULP_ACT_HID_728e] = 206,
+	[BNXT_ULP_ACT_HID_662a] = 207,
+	[BNXT_ULP_ACT_HID_07e2] = 208,
+	[BNXT_ULP_ACT_HID_4c0a] = 209,
+	[BNXT_ULP_ACT_HID_035e] = 210,
+	[BNXT_ULP_ACT_HID_5d1a] = 211,
+	[BNXT_ULP_ACT_HID_477e] = 212,
+	[BNXT_ULP_ACT_HID_7a8e] = 213,
+	[BNXT_ULP_ACT_HID_6e2a] = 214,
+	[BNXT_ULP_ACT_HID_0fe2] = 215,
+	[BNXT_ULP_ACT_HID_540a] = 216,
+	[BNXT_ULP_ACT_HID_0b5e] = 217,
+	[BNXT_ULP_ACT_HID_651a] = 218,
+	[BNXT_ULP_ACT_HID_4f7e] = 219,
+	[BNXT_ULP_ACT_HID_06d2] = 220,
+	[BNXT_ULP_ACT_HID_762a] = 221,
+	[BNXT_ULP_ACT_HID_17e2] = 222,
+	[BNXT_ULP_ACT_HID_5c0a] = 223,
+	[BNXT_ULP_ACT_HID_135e] = 224,
+	[BNXT_ULP_ACT_HID_6d1a] = 225,
+	[BNXT_ULP_ACT_HID_577e] = 226,
+	[BNXT_ULP_ACT_HID_0ed2] = 227,
+	[BNXT_ULP_ACT_HID_026e] = 228,
+	[BNXT_ULP_ACT_HID_1fe2] = 229,
+	[BNXT_ULP_ACT_HID_5d82] = 230,
+	[BNXT_ULP_ACT_HID_14d6] = 231,
+	[BNXT_ULP_ACT_HID_6e92] = 232,
+	[BNXT_ULP_ACT_HID_58f6] = 233,
+	[BNXT_ULP_ACT_HID_104a] = 234,
+	[BNXT_ULP_ACT_HID_215a] = 235,
+	[BNXT_ULP_ACT_HID_5d92] = 236,
+	[BNXT_ULP_ACT_HID_14e6] = 237,
+	[BNXT_ULP_ACT_HID_6ea2] = 238,
+	[BNXT_ULP_ACT_HID_5906] = 239,
+	[BNXT_ULP_ACT_HID_105a] = 240,
+	[BNXT_ULP_ACT_HID_216a] = 241,
+	[BNXT_ULP_ACT_HID_6582] = 242,
+	[BNXT_ULP_ACT_HID_1cd6] = 243,
+	[BNXT_ULP_ACT_HID_7692] = 244,
+	[BNXT_ULP_ACT_HID_60f6] = 245,
+	[BNXT_ULP_ACT_HID_184a] = 246,
+	[BNXT_ULP_ACT_HID_295a] = 247,
+	[BNXT_ULP_ACT_HID_6592] = 248,
+	[BNXT_ULP_ACT_HID_1ce6] = 249,
+	[BNXT_ULP_ACT_HID_76a2] = 250,
+	[BNXT_ULP_ACT_HID_6106] = 251,
+	[BNXT_ULP_ACT_HID_185a] = 252,
+	[BNXT_ULP_ACT_HID_296a] = 253,
+	[BNXT_ULP_ACT_HID_6d82] = 254,
+	[BNXT_ULP_ACT_HID_24d6] = 255,
+	[BNXT_ULP_ACT_HID_02d6] = 256,
+	[BNXT_ULP_ACT_HID_68f6] = 257,
+	[BNXT_ULP_ACT_HID_204a] = 258,
+	[BNXT_ULP_ACT_HID_315a] = 259,
+	[BNXT_ULP_ACT_HID_6d92] = 260,
+	[BNXT_ULP_ACT_HID_24e6] = 261,
+	[BNXT_ULP_ACT_HID_02e6] = 262,
+	[BNXT_ULP_ACT_HID_6906] = 263,
+	[BNXT_ULP_ACT_HID_205a] = 264,
+	[BNXT_ULP_ACT_HID_316a] = 265,
+	[BNXT_ULP_ACT_HID_7582] = 266,
+	[BNXT_ULP_ACT_HID_2cd6] = 267,
+	[BNXT_ULP_ACT_HID_0ad6] = 268,
+	[BNXT_ULP_ACT_HID_70f6] = 269,
+	[BNXT_ULP_ACT_HID_284a] = 270,
+	[BNXT_ULP_ACT_HID_395a] = 271,
+	[BNXT_ULP_ACT_HID_7592] = 272,
+	[BNXT_ULP_ACT_HID_2ce6] = 273,
+	[BNXT_ULP_ACT_HID_0ae6] = 274,
+	[BNXT_ULP_ACT_HID_7106] = 275,
+	[BNXT_ULP_ACT_HID_285a] = 276,
+	[BNXT_ULP_ACT_HID_396a] = 277,
+	[BNXT_ULP_ACT_HID_0020] = 278,
+	[BNXT_ULP_ACT_HID_0030] = 279,
+	[BNXT_ULP_ACT_HID_65d4] = 280,
+	[BNXT_ULP_ACT_HID_65e4] = 281,
+	[BNXT_ULP_ACT_HID_330a] = 282,
+	[BNXT_ULP_ACT_HID_331a] = 283,
+	[BNXT_ULP_ACT_HID_1cfe] = 284,
+	[BNXT_ULP_ACT_HID_1d0e] = 285,
+	[BNXT_ULP_ACT_HID_1474] = 286,
+	[BNXT_ULP_ACT_HID_4838] = 287,
+	[BNXT_ULP_ACT_HID_6458] = 288,
+	[BNXT_ULP_ACT_HID_1c68] = 289,
+	[BNXT_ULP_ACT_HID_6c34] = 290,
+	[BNXT_ULP_ACT_HID_5d08] = 291,
+	[BNXT_ULP_ACT_HID_5d10] = 292,
+	[BNXT_ULP_ACT_HID_5d20] = 293,
+	[BNXT_ULP_ACT_HID_2e18] = 294,
+	[BNXT_ULP_ACT_HID_29d4] = 295,
+	[BNXT_ULP_ACT_HID_7690] = 296,
+	[BNXT_ULP_ACT_HID_47a0] = 297,
+	[BNXT_ULP_ACT_HID_435c] = 298,
+	[BNXT_ULP_ACT_HID_5d18] = 299,
+	[BNXT_ULP_ACT_HID_2e28] = 300,
+	[BNXT_ULP_ACT_HID_29e4] = 301,
+	[BNXT_ULP_ACT_HID_76a0] = 302,
+	[BNXT_ULP_ACT_HID_47b0] = 303,
+	[BNXT_ULP_ACT_HID_436c] = 304,
+	[BNXT_ULP_ACT_HID_1436] = 305,
+	[BNXT_ULP_ACT_HID_143e] = 306,
+	[BNXT_ULP_ACT_HID_144e] = 307,
+	[BNXT_ULP_ACT_HID_6102] = 308,
+	[BNXT_ULP_ACT_HID_5cbe] = 309,
+	[BNXT_ULP_ACT_HID_2dbe] = 310,
+	[BNXT_ULP_ACT_HID_7a8a] = 311,
+	[BNXT_ULP_ACT_HID_7646] = 312,
+	[BNXT_ULP_ACT_HID_1446] = 313,
+	[BNXT_ULP_ACT_HID_6112] = 314,
+	[BNXT_ULP_ACT_HID_5cce] = 315,
+	[BNXT_ULP_ACT_HID_2dce] = 316,
+	[BNXT_ULP_ACT_HID_7a9a] = 317,
+	[BNXT_ULP_ACT_HID_7656] = 318,
+	[BNXT_ULP_ACT_HID_6508] = 319,
+	[BNXT_ULP_ACT_HID_6d08] = 320,
+	[BNXT_ULP_ACT_HID_7508] = 321,
+	[BNXT_ULP_ACT_HID_6518] = 322,
+	[BNXT_ULP_ACT_HID_6d18] = 323,
+	[BNXT_ULP_ACT_HID_7518] = 324,
+	[BNXT_ULP_ACT_HID_6e18] = 325,
+	[BNXT_ULP_ACT_HID_256c] = 326,
+	[BNXT_ULP_ACT_HID_036c] = 327,
+	[BNXT_ULP_ACT_HID_698c] = 328,
+	[BNXT_ULP_ACT_HID_20e0] = 329,
+	[BNXT_ULP_ACT_HID_31f0] = 330,
+	[BNXT_ULP_ACT_HID_7618] = 331,
+	[BNXT_ULP_ACT_HID_2d6c] = 332,
+	[BNXT_ULP_ACT_HID_0b6c] = 333,
+	[BNXT_ULP_ACT_HID_718c] = 334,
+	[BNXT_ULP_ACT_HID_28e0] = 335,
+	[BNXT_ULP_ACT_HID_39f0] = 336,
+	[BNXT_ULP_ACT_HID_025c] = 337,
+	[BNXT_ULP_ACT_HID_356c] = 338,
+	[BNXT_ULP_ACT_HID_136c] = 339,
+	[BNXT_ULP_ACT_HID_798c] = 340,
+	[BNXT_ULP_ACT_HID_30e0] = 341,
+	[BNXT_ULP_ACT_HID_41f0] = 342,
+	[BNXT_ULP_ACT_HID_0a5c] = 343,
+	[BNXT_ULP_ACT_HID_3d6c] = 344,
+	[BNXT_ULP_ACT_HID_1b6c] = 345,
+	[BNXT_ULP_ACT_HID_05d0] = 346,
+	[BNXT_ULP_ACT_HID_38e0] = 347,
+	[BNXT_ULP_ACT_HID_49f0] = 348,
+	[BNXT_ULP_ACT_HID_6e28] = 349,
+	[BNXT_ULP_ACT_HID_257c] = 350,
+	[BNXT_ULP_ACT_HID_037c] = 351,
+	[BNXT_ULP_ACT_HID_699c] = 352,
+	[BNXT_ULP_ACT_HID_20f0] = 353,
+	[BNXT_ULP_ACT_HID_3200] = 354,
+	[BNXT_ULP_ACT_HID_7628] = 355,
+	[BNXT_ULP_ACT_HID_2d7c] = 356,
+	[BNXT_ULP_ACT_HID_0b7c] = 357,
+	[BNXT_ULP_ACT_HID_719c] = 358,
+	[BNXT_ULP_ACT_HID_28f0] = 359,
+	[BNXT_ULP_ACT_HID_3a00] = 360,
+	[BNXT_ULP_ACT_HID_026c] = 361,
+	[BNXT_ULP_ACT_HID_357c] = 362,
+	[BNXT_ULP_ACT_HID_137c] = 363,
+	[BNXT_ULP_ACT_HID_799c] = 364,
+	[BNXT_ULP_ACT_HID_30f0] = 365,
+	[BNXT_ULP_ACT_HID_4200] = 366,
+	[BNXT_ULP_ACT_HID_0a6c] = 367,
+	[BNXT_ULP_ACT_HID_3d7c] = 368,
+	[BNXT_ULP_ACT_HID_1b7c] = 369,
+	[BNXT_ULP_ACT_HID_05e0] = 370,
+	[BNXT_ULP_ACT_HID_38f0] = 371,
+	[BNXT_ULP_ACT_HID_4a00] = 372,
+	[BNXT_ULP_ACT_HID_0be4] = 373,
+	[BNXT_ULP_ACT_HID_3ef4] = 374,
+	[BNXT_ULP_ACT_HID_1cf4] = 375,
+	[BNXT_ULP_ACT_HID_0758] = 376,
+	[BNXT_ULP_ACT_HID_3a68] = 377,
+	[BNXT_ULP_ACT_HID_4b78] = 378,
+	[BNXT_ULP_ACT_HID_0bf4] = 379,
+	[BNXT_ULP_ACT_HID_3f04] = 380,
+	[BNXT_ULP_ACT_HID_1d04] = 381,
+	[BNXT_ULP_ACT_HID_0768] = 382,
+	[BNXT_ULP_ACT_HID_3a78] = 383,
+	[BNXT_ULP_ACT_HID_4b88] = 384,
+	[BNXT_ULP_ACT_HID_46f4] = 385,
+	[BNXT_ULP_ACT_HID_24f4] = 386,
+	[BNXT_ULP_ACT_HID_0f58] = 387,
+	[BNXT_ULP_ACT_HID_13e4] = 388,
+	[BNXT_ULP_ACT_HID_4268] = 389,
+	[BNXT_ULP_ACT_HID_5378] = 390,
+	[BNXT_ULP_ACT_HID_13f4] = 391,
+	[BNXT_ULP_ACT_HID_4704] = 392,
+	[BNXT_ULP_ACT_HID_2504] = 393,
+	[BNXT_ULP_ACT_HID_0f68] = 394,
+	[BNXT_ULP_ACT_HID_4278] = 395,
+	[BNXT_ULP_ACT_HID_5388] = 396,
+	[BNXT_ULP_ACT_HID_1be4] = 397,
+	[BNXT_ULP_ACT_HID_4ef4] = 398,
+	[BNXT_ULP_ACT_HID_2cf4] = 399,
+	[BNXT_ULP_ACT_HID_1758] = 400,
+	[BNXT_ULP_ACT_HID_4a68] = 401,
+	[BNXT_ULP_ACT_HID_5b78] = 402,
+	[BNXT_ULP_ACT_HID_1bf4] = 403,
+	[BNXT_ULP_ACT_HID_4f04] = 404,
+	[BNXT_ULP_ACT_HID_2d04] = 405,
+	[BNXT_ULP_ACT_HID_1768] = 406,
+	[BNXT_ULP_ACT_HID_4a78] = 407,
+	[BNXT_ULP_ACT_HID_5b88] = 408,
+	[BNXT_ULP_ACT_HID_23e4] = 409,
+	[BNXT_ULP_ACT_HID_56f4] = 410,
+	[BNXT_ULP_ACT_HID_34f4] = 411,
+	[BNXT_ULP_ACT_HID_1f58] = 412,
+	[BNXT_ULP_ACT_HID_5268] = 413,
+	[BNXT_ULP_ACT_HID_6378] = 414,
+	[BNXT_ULP_ACT_HID_23f4] = 415,
+	[BNXT_ULP_ACT_HID_5704] = 416,
+	[BNXT_ULP_ACT_HID_3504] = 417,
+	[BNXT_ULP_ACT_HID_1f68] = 418,
+	[BNXT_ULP_ACT_HID_5278] = 419,
+	[BNXT_ULP_ACT_HID_6388] = 420,
+	[BNXT_ULP_ACT_HID_1c36] = 421,
+	[BNXT_ULP_ACT_HID_2436] = 422,
+	[BNXT_ULP_ACT_HID_2c36] = 423,
+	[BNXT_ULP_ACT_HID_1c46] = 424,
+	[BNXT_ULP_ACT_HID_2446] = 425,
+	[BNXT_ULP_ACT_HID_2c46] = 426,
+	[BNXT_ULP_ACT_HID_2546] = 427,
+	[BNXT_ULP_ACT_HID_5856] = 428,
+	[BNXT_ULP_ACT_HID_3656] = 429,
+	[BNXT_ULP_ACT_HID_20ba] = 430,
+	[BNXT_ULP_ACT_HID_53ca] = 431,
+	[BNXT_ULP_ACT_HID_64da] = 432,
+	[BNXT_ULP_ACT_HID_2d46] = 433,
+	[BNXT_ULP_ACT_HID_6056] = 434,
+	[BNXT_ULP_ACT_HID_3e56] = 435,
+	[BNXT_ULP_ACT_HID_28ba] = 436,
+	[BNXT_ULP_ACT_HID_5bca] = 437,
+	[BNXT_ULP_ACT_HID_6cda] = 438,
+	[BNXT_ULP_ACT_HID_3546] = 439,
+	[BNXT_ULP_ACT_HID_6856] = 440,
+	[BNXT_ULP_ACT_HID_4656] = 441,
+	[BNXT_ULP_ACT_HID_30ba] = 442,
+	[BNXT_ULP_ACT_HID_63ca] = 443,
+	[BNXT_ULP_ACT_HID_74da] = 444,
+	[BNXT_ULP_ACT_HID_3d46] = 445,
+	[BNXT_ULP_ACT_HID_7056] = 446,
+	[BNXT_ULP_ACT_HID_4e56] = 447,
+	[BNXT_ULP_ACT_HID_38ba] = 448,
+	[BNXT_ULP_ACT_HID_6bca] = 449,
+	[BNXT_ULP_ACT_HID_011e] = 450,
+	[BNXT_ULP_ACT_HID_2556] = 451,
+	[BNXT_ULP_ACT_HID_5866] = 452,
+	[BNXT_ULP_ACT_HID_3666] = 453,
+	[BNXT_ULP_ACT_HID_20ca] = 454,
+	[BNXT_ULP_ACT_HID_53da] = 455,
+	[BNXT_ULP_ACT_HID_64ea] = 456,
+	[BNXT_ULP_ACT_HID_2d56] = 457,
+	[BNXT_ULP_ACT_HID_6066] = 458,
+	[BNXT_ULP_ACT_HID_3e66] = 459,
+	[BNXT_ULP_ACT_HID_28ca] = 460,
+	[BNXT_ULP_ACT_HID_5bda] = 461,
+	[BNXT_ULP_ACT_HID_6cea] = 462,
+	[BNXT_ULP_ACT_HID_3556] = 463,
+	[BNXT_ULP_ACT_HID_6866] = 464,
+	[BNXT_ULP_ACT_HID_4666] = 465,
+	[BNXT_ULP_ACT_HID_30ca] = 466,
+	[BNXT_ULP_ACT_HID_63da] = 467,
+	[BNXT_ULP_ACT_HID_74ea] = 468,
+	[BNXT_ULP_ACT_HID_3d56] = 469,
+	[BNXT_ULP_ACT_HID_7066] = 470,
+	[BNXT_ULP_ACT_HID_4e66] = 471,
+	[BNXT_ULP_ACT_HID_38ca] = 472,
+	[BNXT_ULP_ACT_HID_6bda] = 473,
+	[BNXT_ULP_ACT_HID_012e] = 474,
+	[BNXT_ULP_ACT_HID_3ece] = 475,
+	[BNXT_ULP_ACT_HID_71de] = 476,
+	[BNXT_ULP_ACT_HID_4fde] = 477,
+	[BNXT_ULP_ACT_HID_3a42] = 478,
+	[BNXT_ULP_ACT_HID_6d52] = 479,
+	[BNXT_ULP_ACT_HID_02a6] = 480,
+	[BNXT_ULP_ACT_HID_3ede] = 481,
+	[BNXT_ULP_ACT_HID_71ee] = 482,
+	[BNXT_ULP_ACT_HID_4fee] = 483,
+	[BNXT_ULP_ACT_HID_3a52] = 484,
+	[BNXT_ULP_ACT_HID_6d62] = 485,
+	[BNXT_ULP_ACT_HID_02b6] = 486,
+	[BNXT_ULP_ACT_HID_79de] = 487,
+	[BNXT_ULP_ACT_HID_57de] = 488,
+	[BNXT_ULP_ACT_HID_4242] = 489,
+	[BNXT_ULP_ACT_HID_46ce] = 490,
+	[BNXT_ULP_ACT_HID_7552] = 491,
+	[BNXT_ULP_ACT_HID_0aa6] = 492,
+	[BNXT_ULP_ACT_HID_46de] = 493,
+	[BNXT_ULP_ACT_HID_79ee] = 494,
+	[BNXT_ULP_ACT_HID_57ee] = 495,
+	[BNXT_ULP_ACT_HID_4252] = 496,
+	[BNXT_ULP_ACT_HID_7562] = 497,
+	[BNXT_ULP_ACT_HID_0ab6] = 498,
+	[BNXT_ULP_ACT_HID_4ece] = 499,
+	[BNXT_ULP_ACT_HID_0622] = 500,
+	[BNXT_ULP_ACT_HID_5fde] = 501,
+	[BNXT_ULP_ACT_HID_4a42] = 502,
+	[BNXT_ULP_ACT_HID_0196] = 503,
+	[BNXT_ULP_ACT_HID_12a6] = 504,
+	[BNXT_ULP_ACT_HID_4ede] = 505,
+	[BNXT_ULP_ACT_HID_0632] = 506,
+	[BNXT_ULP_ACT_HID_5fee] = 507,
+	[BNXT_ULP_ACT_HID_4a52] = 508,
+	[BNXT_ULP_ACT_HID_01a6] = 509,
+	[BNXT_ULP_ACT_HID_12b6] = 510,
+	[BNXT_ULP_ACT_HID_56ce] = 511,
+	[BNXT_ULP_ACT_HID_0e22] = 512,
+	[BNXT_ULP_ACT_HID_67de] = 513,
+	[BNXT_ULP_ACT_HID_5242] = 514,
+	[BNXT_ULP_ACT_HID_0996] = 515,
+	[BNXT_ULP_ACT_HID_1aa6] = 516,
+	[BNXT_ULP_ACT_HID_56de] = 517,
+	[BNXT_ULP_ACT_HID_0e32] = 518,
+	[BNXT_ULP_ACT_HID_67ee] = 519,
+	[BNXT_ULP_ACT_HID_5252] = 520,
+	[BNXT_ULP_ACT_HID_09a6] = 521,
+	[BNXT_ULP_ACT_HID_1ab6] = 522,
+	[BNXT_ULP_ACT_HID_31d0] = 523,
+	[BNXT_ULP_ACT_HID_31e0] = 524,
+	[BNXT_ULP_ACT_HID_39d0] = 525,
+	[BNXT_ULP_ACT_HID_39e0] = 526,
+	[BNXT_ULP_ACT_HID_41d0] = 527,
+	[BNXT_ULP_ACT_HID_41e0] = 528,
+	[BNXT_ULP_ACT_HID_49d0] = 529,
+	[BNXT_ULP_ACT_HID_49e0] = 530,
+	[BNXT_ULP_ACT_HID_64ba] = 531,
+	[BNXT_ULP_ACT_HID_64ca] = 532,
+	[BNXT_ULP_ACT_HID_6cba] = 533,
+	[BNXT_ULP_ACT_HID_6cca] = 534,
+	[BNXT_ULP_ACT_HID_74ba] = 535,
+	[BNXT_ULP_ACT_HID_74ca] = 536,
+	[BNXT_ULP_ACT_HID_00fe] = 537,
+	[BNXT_ULP_ACT_HID_010e] = 538,
+	[BNXT_ULP_ACT_HID_331c] = 539,
+	[BNXT_ULP_ACT_HID_332c] = 540,
+	[BNXT_ULP_ACT_HID_6706] = 541,
+	[BNXT_ULP_ACT_HID_6716] = 542,
+	[BNXT_ULP_ACT_HID_1b6d] = 543,
+	[BNXT_ULP_ACT_HID_1b7d] = 544,
+	[BNXT_ULP_ACT_HID_641a] = 545
 };
 
 /* Array for the act matcher list */
@@ -121,7 +571,7 @@  struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[2] = {
-	.act_hid = BNXT_ULP_ACT_HID_0001,
+	.act_hid = BNXT_ULP_ACT_HID_0008,
 	.act_pattern_id = 1,
 	.app_sig = 0,
 	.act_sig = { .bits =
@@ -130,7 +580,7 @@  struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[3] = {
-	.act_hid = BNXT_ULP_ACT_HID_0400,
+	.act_hid = BNXT_ULP_ACT_HID_2000,
 	.act_pattern_id = 2,
 	.app_sig = 0,
 	.act_sig = { .bits =
@@ -139,7 +589,7 @@  struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[4] = {
-	.act_hid = BNXT_ULP_ACT_HID_01ab,
+	.act_hid = BNXT_ULP_ACT_HID_1988,
 	.act_pattern_id = 3,
 	.app_sig = 0,
 	.act_sig = { .bits =
@@ -148,7 +598,7 @@  struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[5] = {
-	.act_hid = BNXT_ULP_ACT_HID_0010,
+	.act_hid = BNXT_ULP_ACT_HID_0080,
 	.act_pattern_id = 4,
 	.app_sig = 0,
 	.act_sig = { .bits =
@@ -157,7 +607,7 @@  struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[6] = {
-	.act_hid = BNXT_ULP_ACT_HID_05ab,
+	.act_hid = BNXT_ULP_ACT_HID_3988,
 	.act_pattern_id = 5,
 	.app_sig = 0,
 	.act_sig = { .bits =
@@ -167,7 +617,7 @@  struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[7] = {
-	.act_hid = BNXT_ULP_ACT_HID_01bb,
+	.act_hid = BNXT_ULP_ACT_HID_1a08,
 	.act_pattern_id = 6,
 	.app_sig = 0,
 	.act_sig = { .bits =
@@ -177,7 +627,7 @@  struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[8] = {
-	.act_hid = BNXT_ULP_ACT_HID_0002,
+	.act_hid = BNXT_ULP_ACT_HID_0010,
 	.act_pattern_id = 7,
 	.app_sig = 0,
 	.act_sig = { .bits =
@@ -186,902 +636,6269 @@  struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[9] = {
-	.act_hid = BNXT_ULP_ACT_HID_0003,
+	.act_hid = BNXT_ULP_ACT_HID_0040,
 	.act_pattern_id = 8,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_DROP |
+		BNXT_ULP_ACT_BIT_METER |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[10] = {
-	.act_hid = BNXT_ULP_ACT_HID_0402,
+	.act_hid = BNXT_ULP_ACT_HID_0050,
 	.act_pattern_id = 9,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_POP_VLAN |
+		BNXT_ULP_ACT_BIT_METER |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[11] = {
-	.act_hid = BNXT_ULP_ACT_HID_01ad,
+	.act_hid = BNXT_ULP_ACT_HID_0018,
 	.act_pattern_id = 10,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[12] = {
-	.act_hid = BNXT_ULP_ACT_HID_0012,
+	.act_hid = BNXT_ULP_ACT_HID_2010,
 	.act_pattern_id = 11,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+		BNXT_ULP_ACT_BIT_POP_VLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[13] = {
-	.act_hid = BNXT_ULP_ACT_HID_05ad,
+	.act_hid = BNXT_ULP_ACT_HID_1998,
 	.act_pattern_id = 12,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_POP_VLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[14] = {
-	.act_hid = BNXT_ULP_ACT_HID_01bd,
+	.act_hid = BNXT_ULP_ACT_HID_0090,
 	.act_pattern_id = 13,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
-		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[15] = {
-	.act_hid = BNXT_ULP_ACT_HID_0613,
+	.act_hid = BNXT_ULP_ACT_HID_3998,
 	.act_pattern_id = 14,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
-		BNXT_ULP_ACT_BIT_DROP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_POP_VLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[16] = {
-	.act_hid = BNXT_ULP_ACT_HID_02a9,
+	.act_hid = BNXT_ULP_ACT_HID_1a18,
 	.act_pattern_id = 15,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
-		BNXT_ULP_ACT_BIT_POP_VLAN |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[17] = {
-	.act_hid = BNXT_ULP_ACT_HID_0054,
+	.act_hid = BNXT_ULP_ACT_HID_32ea,
 	.act_pattern_id = 16,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
-		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[18] = {
-	.act_hid = BNXT_ULP_ACT_HID_0622,
+	.act_hid = BNXT_ULP_ACT_HID_32f2,
 	.act_pattern_id = 17,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
-		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[19] = {
-	.act_hid = BNXT_ULP_ACT_HID_0454,
+	.act_hid = BNXT_ULP_ACT_HID_52ea,
 	.act_pattern_id = 18,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
-		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_POP_VLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[20] = {
-	.act_hid = BNXT_ULP_ACT_HID_0064,
+	.act_hid = BNXT_ULP_ACT_HID_4c72,
 	.act_pattern_id = 19,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
-		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[21] = {
-	.act_hid = BNXT_ULP_ACT_HID_0614,
+	.act_hid = BNXT_ULP_ACT_HID_336a,
 	.act_pattern_id = 20,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
-		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[22] = {
-	.act_hid = BNXT_ULP_ACT_HID_0615,
+	.act_hid = BNXT_ULP_ACT_HID_6c72,
 	.act_pattern_id = 21,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
-		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_DROP |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_POP_VLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[23] = {
-	.act_hid = BNXT_ULP_ACT_HID_02ab,
+	.act_hid = BNXT_ULP_ACT_HID_4cf2,
 	.act_pattern_id = 22,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
-		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_POP_VLAN |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[24] = {
-	.act_hid = BNXT_ULP_ACT_HID_0056,
+	.act_hid = BNXT_ULP_ACT_HID_32fa,
 	.act_pattern_id = 23,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[25] = {
-	.act_hid = BNXT_ULP_ACT_HID_0624,
+	.act_hid = BNXT_ULP_ACT_HID_3302,
 	.act_pattern_id = 24,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[26] = {
-	.act_hid = BNXT_ULP_ACT_HID_0456,
+	.act_hid = BNXT_ULP_ACT_HID_52fa,
 	.act_pattern_id = 25,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_POP_VLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[27] = {
-	.act_hid = BNXT_ULP_ACT_HID_0066,
+	.act_hid = BNXT_ULP_ACT_HID_4c82,
 	.act_pattern_id = 26,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 1
 	},
 	[28] = {
-	.act_hid = BNXT_ULP_ACT_HID_048d,
-	.act_pattern_id = 0,
+	.act_hid = BNXT_ULP_ACT_HID_337a,
+	.act_pattern_id = 27,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SHARED |
-		BNXT_ULP_ACT_BIT_SAMPLE |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 2
+	.act_tid = 1
 	},
 	[29] = {
-	.act_hid = BNXT_ULP_ACT_HID_048f,
-	.act_pattern_id = 1,
+	.act_hid = BNXT_ULP_ACT_HID_6c82,
+	.act_pattern_id = 28,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SHARED |
-		BNXT_ULP_ACT_BIT_SAMPLE |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_POP_VLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 2
+	.act_tid = 1
 	},
 	[30] = {
-	.act_hid = BNXT_ULP_ACT_HID_04bc,
-	.act_pattern_id = 0,
+	.act_hid = BNXT_ULP_ACT_HID_4d02,
+	.act_pattern_id = 29,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[31] = {
-	.act_hid = BNXT_ULP_ACT_HID_00a9,
-	.act_pattern_id = 1,
+	.act_hid = BNXT_ULP_ACT_HID_0808,
+	.act_pattern_id = 30,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[32] = {
-	.act_hid = BNXT_ULP_ACT_HID_020f,
-	.act_pattern_id = 2,
+	.act_hid = BNXT_ULP_ACT_HID_1008,
+	.act_pattern_id = 31,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[33] = {
-	.act_hid = BNXT_ULP_ACT_HID_0153,
-	.act_pattern_id = 3,
+	.act_hid = BNXT_ULP_ACT_HID_1808,
+	.act_pattern_id = 32,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[34] = {
-	.act_hid = BNXT_ULP_ACT_HID_04a9,
-	.act_pattern_id = 4,
+	.act_hid = BNXT_ULP_ACT_HID_0818,
+	.act_pattern_id = 33,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[35] = {
-	.act_hid = BNXT_ULP_ACT_HID_01fc,
-	.act_pattern_id = 5,
+	.act_hid = BNXT_ULP_ACT_HID_1018,
+	.act_pattern_id = 34,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[36] = {
-	.act_hid = BNXT_ULP_ACT_HID_04be,
-	.act_pattern_id = 6,
+	.act_hid = BNXT_ULP_ACT_HID_1818,
+	.act_pattern_id = 35,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[37] = {
-	.act_hid = BNXT_ULP_ACT_HID_00ab,
-	.act_pattern_id = 7,
+	.act_hid = BNXT_ULP_ACT_HID_0880,
+	.act_pattern_id = 36,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[38] = {
-	.act_hid = BNXT_ULP_ACT_HID_0211,
-	.act_pattern_id = 8,
+	.act_hid = BNXT_ULP_ACT_HID_1080,
+	.act_pattern_id = 37,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[39] = {
-	.act_hid = BNXT_ULP_ACT_HID_0155,
-	.act_pattern_id = 9,
+	.act_hid = BNXT_ULP_ACT_HID_1880,
+	.act_pattern_id = 38,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[40] = {
-	.act_hid = BNXT_ULP_ACT_HID_04ab,
-	.act_pattern_id = 10,
+	.act_hid = BNXT_ULP_ACT_HID_0890,
+	.act_pattern_id = 39,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[41] = {
-	.act_hid = BNXT_ULP_ACT_HID_01fe,
-	.act_pattern_id = 11,
+	.act_hid = BNXT_ULP_ACT_HID_1090,
+	.act_pattern_id = 40,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[42] = {
-	.act_hid = BNXT_ULP_ACT_HID_0667,
-	.act_pattern_id = 12,
+	.act_hid = BNXT_ULP_ACT_HID_1890,
+	.act_pattern_id = 41,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[43] = {
-	.act_hid = BNXT_ULP_ACT_HID_0254,
-	.act_pattern_id = 13,
+	.act_hid = BNXT_ULP_ACT_HID_3af2,
+	.act_pattern_id = 42,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[44] = {
-	.act_hid = BNXT_ULP_ACT_HID_03ba,
-	.act_pattern_id = 14,
+	.act_hid = BNXT_ULP_ACT_HID_42f2,
+	.act_pattern_id = 43,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[45] = {
-	.act_hid = BNXT_ULP_ACT_HID_02fe,
-	.act_pattern_id = 15,
+	.act_hid = BNXT_ULP_ACT_HID_4af2,
+	.act_pattern_id = 44,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[46] = {
-	.act_hid = BNXT_ULP_ACT_HID_0654,
-	.act_pattern_id = 16,
+	.act_hid = BNXT_ULP_ACT_HID_3b02,
+	.act_pattern_id = 45,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[47] = {
-	.act_hid = BNXT_ULP_ACT_HID_03a7,
-	.act_pattern_id = 17,
+	.act_hid = BNXT_ULP_ACT_HID_4302,
+	.act_pattern_id = 46,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[48] = {
-	.act_hid = BNXT_ULP_ACT_HID_0669,
-	.act_pattern_id = 18,
+	.act_hid = BNXT_ULP_ACT_HID_4b02,
+	.act_pattern_id = 47,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[49] = {
-	.act_hid = BNXT_ULP_ACT_HID_0256,
-	.act_pattern_id = 19,
+	.act_hid = BNXT_ULP_ACT_HID_3b6a,
+	.act_pattern_id = 48,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[50] = {
-	.act_hid = BNXT_ULP_ACT_HID_03bc,
-	.act_pattern_id = 20,
+	.act_hid = BNXT_ULP_ACT_HID_436a,
+	.act_pattern_id = 49,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[51] = {
-	.act_hid = BNXT_ULP_ACT_HID_0300,
-	.act_pattern_id = 21,
+	.act_hid = BNXT_ULP_ACT_HID_4b6a,
+	.act_pattern_id = 50,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[52] = {
-	.act_hid = BNXT_ULP_ACT_HID_0656,
-	.act_pattern_id = 22,
+	.act_hid = BNXT_ULP_ACT_HID_3b7a,
+	.act_pattern_id = 51,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[53] = {
-	.act_hid = BNXT_ULP_ACT_HID_03a9,
-	.act_pattern_id = 23,
+	.act_hid = BNXT_ULP_ACT_HID_437a,
+	.act_pattern_id = 52,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
-	.act_tid = 3
+	.act_tid = 1
 	},
 	[54] = {
-	.act_hid = BNXT_ULP_ACT_HID_021b,
-	.act_pattern_id = 0,
+	.act_hid = BNXT_ULP_ACT_HID_4b7a,
+	.act_pattern_id = 53,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 1
 	},
 	[55] = {
-	.act_hid = BNXT_ULP_ACT_HID_021c,
-	.act_pattern_id = 1,
+	.act_hid = BNXT_ULP_ACT_HID_640d,
+	.act_pattern_id = 0,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DROP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_ACT_BIT_SHARED |
+		BNXT_ULP_ACT_BIT_SAMPLE |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 2
+	},
+	[56] = {
+	.act_hid = BNXT_ULP_ACT_HID_641d,
+	.act_pattern_id = 1,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED |
+		BNXT_ULP_ACT_BIT_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 2
+	},
+	[57] = {
+	.act_hid = BNXT_ULP_ACT_HID_071a,
+	.act_pattern_id = 2,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DELETE |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 2
+	},
+	[58] = {
+	.act_hid = BNXT_ULP_ACT_HID_0800,
+	.act_pattern_id = 0,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[59] = {
+	.act_hid = BNXT_ULP_ACT_HID_1000,
+	.act_pattern_id = 1,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[60] = {
+	.act_hid = BNXT_ULP_ACT_HID_1800,
+	.act_pattern_id = 2,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[61] = {
+	.act_hid = BNXT_ULP_ACT_HID_0810,
+	.act_pattern_id = 3,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[62] = {
+	.act_hid = BNXT_ULP_ACT_HID_1010,
+	.act_pattern_id = 4,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[63] = {
+	.act_hid = BNXT_ULP_ACT_HID_1810,
+	.act_pattern_id = 5,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[64] = {
+	.act_hid = BNXT_ULP_ACT_HID_1110,
+	.act_pattern_id = 6,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[65] = {
+	.act_hid = BNXT_ULP_ACT_HID_4420,
+	.act_pattern_id = 7,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[66] = {
+	.act_hid = BNXT_ULP_ACT_HID_2220,
+	.act_pattern_id = 8,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[67] = {
+	.act_hid = BNXT_ULP_ACT_HID_0c84,
+	.act_pattern_id = 9,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[68] = {
+	.act_hid = BNXT_ULP_ACT_HID_3f94,
+	.act_pattern_id = 10,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[69] = {
+	.act_hid = BNXT_ULP_ACT_HID_3330,
+	.act_pattern_id = 11,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[70] = {
+	.act_hid = BNXT_ULP_ACT_HID_50a4,
+	.act_pattern_id = 12,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[71] = {
+	.act_hid = BNXT_ULP_ACT_HID_1910,
+	.act_pattern_id = 13,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[72] = {
+	.act_hid = BNXT_ULP_ACT_HID_4c20,
+	.act_pattern_id = 14,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[73] = {
+	.act_hid = BNXT_ULP_ACT_HID_2a20,
+	.act_pattern_id = 15,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[74] = {
+	.act_hid = BNXT_ULP_ACT_HID_1484,
+	.act_pattern_id = 16,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[75] = {
+	.act_hid = BNXT_ULP_ACT_HID_4794,
+	.act_pattern_id = 17,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[76] = {
+	.act_hid = BNXT_ULP_ACT_HID_3b30,
+	.act_pattern_id = 18,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[77] = {
+	.act_hid = BNXT_ULP_ACT_HID_58a4,
+	.act_pattern_id = 19,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[78] = {
+	.act_hid = BNXT_ULP_ACT_HID_2110,
+	.act_pattern_id = 20,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[79] = {
+	.act_hid = BNXT_ULP_ACT_HID_5420,
+	.act_pattern_id = 21,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[80] = {
+	.act_hid = BNXT_ULP_ACT_HID_3220,
+	.act_pattern_id = 22,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[81] = {
+	.act_hid = BNXT_ULP_ACT_HID_1c84,
+	.act_pattern_id = 23,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[82] = {
+	.act_hid = BNXT_ULP_ACT_HID_4f94,
+	.act_pattern_id = 24,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[83] = {
+	.act_hid = BNXT_ULP_ACT_HID_4330,
+	.act_pattern_id = 25,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[84] = {
+	.act_hid = BNXT_ULP_ACT_HID_60a4,
+	.act_pattern_id = 26,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[85] = {
+	.act_hid = BNXT_ULP_ACT_HID_2910,
+	.act_pattern_id = 27,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[86] = {
+	.act_hid = BNXT_ULP_ACT_HID_5c20,
+	.act_pattern_id = 28,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[87] = {
+	.act_hid = BNXT_ULP_ACT_HID_3a20,
+	.act_pattern_id = 29,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[88] = {
+	.act_hid = BNXT_ULP_ACT_HID_2484,
+	.act_pattern_id = 30,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[89] = {
+	.act_hid = BNXT_ULP_ACT_HID_5794,
+	.act_pattern_id = 31,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[90] = {
+	.act_hid = BNXT_ULP_ACT_HID_4b30,
+	.act_pattern_id = 32,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[91] = {
+	.act_hid = BNXT_ULP_ACT_HID_68a4,
+	.act_pattern_id = 33,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[92] = {
+	.act_hid = BNXT_ULP_ACT_HID_1120,
+	.act_pattern_id = 34,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[93] = {
+	.act_hid = BNXT_ULP_ACT_HID_4430,
+	.act_pattern_id = 35,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[94] = {
+	.act_hid = BNXT_ULP_ACT_HID_2230,
+	.act_pattern_id = 36,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[95] = {
+	.act_hid = BNXT_ULP_ACT_HID_0c94,
+	.act_pattern_id = 37,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[96] = {
+	.act_hid = BNXT_ULP_ACT_HID_3fa4,
+	.act_pattern_id = 38,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[97] = {
+	.act_hid = BNXT_ULP_ACT_HID_3340,
+	.act_pattern_id = 39,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[98] = {
+	.act_hid = BNXT_ULP_ACT_HID_50b4,
+	.act_pattern_id = 40,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[99] = {
+	.act_hid = BNXT_ULP_ACT_HID_1920,
+	.act_pattern_id = 41,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[100] = {
+	.act_hid = BNXT_ULP_ACT_HID_4c30,
+	.act_pattern_id = 42,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[101] = {
+	.act_hid = BNXT_ULP_ACT_HID_2a30,
+	.act_pattern_id = 43,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[102] = {
+	.act_hid = BNXT_ULP_ACT_HID_1494,
+	.act_pattern_id = 44,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[103] = {
+	.act_hid = BNXT_ULP_ACT_HID_47a4,
+	.act_pattern_id = 45,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[104] = {
+	.act_hid = BNXT_ULP_ACT_HID_3b40,
+	.act_pattern_id = 46,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[105] = {
+	.act_hid = BNXT_ULP_ACT_HID_58b4,
+	.act_pattern_id = 47,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[106] = {
+	.act_hid = BNXT_ULP_ACT_HID_2120,
+	.act_pattern_id = 48,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[107] = {
+	.act_hid = BNXT_ULP_ACT_HID_5430,
+	.act_pattern_id = 49,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[108] = {
+	.act_hid = BNXT_ULP_ACT_HID_3230,
+	.act_pattern_id = 50,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[109] = {
+	.act_hid = BNXT_ULP_ACT_HID_1c94,
+	.act_pattern_id = 51,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[110] = {
+	.act_hid = BNXT_ULP_ACT_HID_4fa4,
+	.act_pattern_id = 52,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[111] = {
+	.act_hid = BNXT_ULP_ACT_HID_4340,
+	.act_pattern_id = 53,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[112] = {
+	.act_hid = BNXT_ULP_ACT_HID_60b4,
+	.act_pattern_id = 54,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[113] = {
+	.act_hid = BNXT_ULP_ACT_HID_2920,
+	.act_pattern_id = 55,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[114] = {
+	.act_hid = BNXT_ULP_ACT_HID_5c30,
+	.act_pattern_id = 56,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[115] = {
+	.act_hid = BNXT_ULP_ACT_HID_3a30,
+	.act_pattern_id = 57,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[116] = {
+	.act_hid = BNXT_ULP_ACT_HID_2494,
+	.act_pattern_id = 58,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[117] = {
+	.act_hid = BNXT_ULP_ACT_HID_57a4,
+	.act_pattern_id = 59,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[118] = {
+	.act_hid = BNXT_ULP_ACT_HID_4b40,
+	.act_pattern_id = 60,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[119] = {
+	.act_hid = BNXT_ULP_ACT_HID_68b4,
+	.act_pattern_id = 61,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[120] = {
+	.act_hid = BNXT_ULP_ACT_HID_2a98,
+	.act_pattern_id = 62,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[121] = {
+	.act_hid = BNXT_ULP_ACT_HID_5da8,
+	.act_pattern_id = 63,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[122] = {
+	.act_hid = BNXT_ULP_ACT_HID_3ba8,
+	.act_pattern_id = 64,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[123] = {
+	.act_hid = BNXT_ULP_ACT_HID_260c,
+	.act_pattern_id = 65,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[124] = {
+	.act_hid = BNXT_ULP_ACT_HID_591c,
+	.act_pattern_id = 66,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[125] = {
+	.act_hid = BNXT_ULP_ACT_HID_6a2c,
+	.act_pattern_id = 67,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[126] = {
+	.act_hid = BNXT_ULP_ACT_HID_2aa8,
+	.act_pattern_id = 68,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[127] = {
+	.act_hid = BNXT_ULP_ACT_HID_5db8,
+	.act_pattern_id = 69,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[128] = {
+	.act_hid = BNXT_ULP_ACT_HID_3bb8,
+	.act_pattern_id = 70,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[129] = {
+	.act_hid = BNXT_ULP_ACT_HID_261c,
+	.act_pattern_id = 71,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[130] = {
+	.act_hid = BNXT_ULP_ACT_HID_592c,
+	.act_pattern_id = 72,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[131] = {
+	.act_hid = BNXT_ULP_ACT_HID_6a3c,
+	.act_pattern_id = 73,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[132] = {
+	.act_hid = BNXT_ULP_ACT_HID_3298,
+	.act_pattern_id = 74,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[133] = {
+	.act_hid = BNXT_ULP_ACT_HID_65a8,
+	.act_pattern_id = 75,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[134] = {
+	.act_hid = BNXT_ULP_ACT_HID_43a8,
+	.act_pattern_id = 76,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[135] = {
+	.act_hid = BNXT_ULP_ACT_HID_2e0c,
+	.act_pattern_id = 77,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[136] = {
+	.act_hid = BNXT_ULP_ACT_HID_611c,
+	.act_pattern_id = 78,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[137] = {
+	.act_hid = BNXT_ULP_ACT_HID_722c,
+	.act_pattern_id = 79,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[138] = {
+	.act_hid = BNXT_ULP_ACT_HID_32a8,
+	.act_pattern_id = 80,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[139] = {
+	.act_hid = BNXT_ULP_ACT_HID_65b8,
+	.act_pattern_id = 81,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[140] = {
+	.act_hid = BNXT_ULP_ACT_HID_43b8,
+	.act_pattern_id = 82,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[141] = {
+	.act_hid = BNXT_ULP_ACT_HID_2e1c,
+	.act_pattern_id = 83,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[142] = {
+	.act_hid = BNXT_ULP_ACT_HID_612c,
+	.act_pattern_id = 84,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[143] = {
+	.act_hid = BNXT_ULP_ACT_HID_723c,
+	.act_pattern_id = 85,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[144] = {
+	.act_hid = BNXT_ULP_ACT_HID_3a98,
+	.act_pattern_id = 86,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[145] = {
+	.act_hid = BNXT_ULP_ACT_HID_6da8,
+	.act_pattern_id = 87,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[146] = {
+	.act_hid = BNXT_ULP_ACT_HID_4ba8,
+	.act_pattern_id = 88,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[147] = {
+	.act_hid = BNXT_ULP_ACT_HID_360c,
+	.act_pattern_id = 89,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[148] = {
+	.act_hid = BNXT_ULP_ACT_HID_691c,
+	.act_pattern_id = 90,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[149] = {
+	.act_hid = BNXT_ULP_ACT_HID_7a2c,
+	.act_pattern_id = 91,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[150] = {
+	.act_hid = BNXT_ULP_ACT_HID_3aa8,
+	.act_pattern_id = 92,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[151] = {
+	.act_hid = BNXT_ULP_ACT_HID_6db8,
+	.act_pattern_id = 93,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[152] = {
+	.act_hid = BNXT_ULP_ACT_HID_4bb8,
+	.act_pattern_id = 94,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[153] = {
+	.act_hid = BNXT_ULP_ACT_HID_361c,
+	.act_pattern_id = 95,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[154] = {
+	.act_hid = BNXT_ULP_ACT_HID_692c,
+	.act_pattern_id = 96,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[155] = {
+	.act_hid = BNXT_ULP_ACT_HID_7a3c,
+	.act_pattern_id = 97,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[156] = {
+	.act_hid = BNXT_ULP_ACT_HID_4298,
+	.act_pattern_id = 98,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[157] = {
+	.act_hid = BNXT_ULP_ACT_HID_75a8,
+	.act_pattern_id = 99,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[158] = {
+	.act_hid = BNXT_ULP_ACT_HID_53a8,
+	.act_pattern_id = 100,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[159] = {
+	.act_hid = BNXT_ULP_ACT_HID_3e0c,
+	.act_pattern_id = 101,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[160] = {
+	.act_hid = BNXT_ULP_ACT_HID_711c,
+	.act_pattern_id = 102,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[161] = {
+	.act_hid = BNXT_ULP_ACT_HID_0670,
+	.act_pattern_id = 103,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[162] = {
+	.act_hid = BNXT_ULP_ACT_HID_42a8,
+	.act_pattern_id = 104,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[163] = {
+	.act_hid = BNXT_ULP_ACT_HID_75b8,
+	.act_pattern_id = 105,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[164] = {
+	.act_hid = BNXT_ULP_ACT_HID_53b8,
+	.act_pattern_id = 106,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[165] = {
+	.act_hid = BNXT_ULP_ACT_HID_3e1c,
+	.act_pattern_id = 107,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[166] = {
+	.act_hid = BNXT_ULP_ACT_HID_712c,
+	.act_pattern_id = 108,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[167] = {
+	.act_hid = BNXT_ULP_ACT_HID_0680,
+	.act_pattern_id = 109,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[168] = {
+	.act_hid = BNXT_ULP_ACT_HID_3aea,
+	.act_pattern_id = 110,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[169] = {
+	.act_hid = BNXT_ULP_ACT_HID_42ea,
+	.act_pattern_id = 111,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[170] = {
+	.act_hid = BNXT_ULP_ACT_HID_4aea,
+	.act_pattern_id = 112,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[171] = {
+	.act_hid = BNXT_ULP_ACT_HID_3afa,
+	.act_pattern_id = 113,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[172] = {
+	.act_hid = BNXT_ULP_ACT_HID_42fa,
+	.act_pattern_id = 114,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[173] = {
+	.act_hid = BNXT_ULP_ACT_HID_4afa,
+	.act_pattern_id = 115,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[174] = {
+	.act_hid = BNXT_ULP_ACT_HID_43fa,
+	.act_pattern_id = 116,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[175] = {
+	.act_hid = BNXT_ULP_ACT_HID_770a,
+	.act_pattern_id = 117,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[176] = {
+	.act_hid = BNXT_ULP_ACT_HID_550a,
+	.act_pattern_id = 118,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[177] = {
+	.act_hid = BNXT_ULP_ACT_HID_3f6e,
+	.act_pattern_id = 119,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[178] = {
+	.act_hid = BNXT_ULP_ACT_HID_727e,
+	.act_pattern_id = 120,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[179] = {
+	.act_hid = BNXT_ULP_ACT_HID_661a,
+	.act_pattern_id = 121,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[180] = {
+	.act_hid = BNXT_ULP_ACT_HID_07d2,
+	.act_pattern_id = 122,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[181] = {
+	.act_hid = BNXT_ULP_ACT_HID_4bfa,
+	.act_pattern_id = 123,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[182] = {
+	.act_hid = BNXT_ULP_ACT_HID_034e,
+	.act_pattern_id = 124,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[183] = {
+	.act_hid = BNXT_ULP_ACT_HID_5d0a,
+	.act_pattern_id = 125,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[184] = {
+	.act_hid = BNXT_ULP_ACT_HID_476e,
+	.act_pattern_id = 126,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[185] = {
+	.act_hid = BNXT_ULP_ACT_HID_7a7e,
+	.act_pattern_id = 127,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[186] = {
+	.act_hid = BNXT_ULP_ACT_HID_6e1a,
+	.act_pattern_id = 128,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[187] = {
+	.act_hid = BNXT_ULP_ACT_HID_0fd2,
+	.act_pattern_id = 129,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[188] = {
+	.act_hid = BNXT_ULP_ACT_HID_53fa,
+	.act_pattern_id = 130,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[189] = {
+	.act_hid = BNXT_ULP_ACT_HID_0b4e,
+	.act_pattern_id = 131,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[190] = {
+	.act_hid = BNXT_ULP_ACT_HID_650a,
+	.act_pattern_id = 132,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[191] = {
+	.act_hid = BNXT_ULP_ACT_HID_4f6e,
+	.act_pattern_id = 133,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[192] = {
+	.act_hid = BNXT_ULP_ACT_HID_06c2,
+	.act_pattern_id = 134,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[193] = {
+	.act_hid = BNXT_ULP_ACT_HID_761a,
+	.act_pattern_id = 135,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[194] = {
+	.act_hid = BNXT_ULP_ACT_HID_17d2,
+	.act_pattern_id = 136,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[195] = {
+	.act_hid = BNXT_ULP_ACT_HID_5bfa,
+	.act_pattern_id = 137,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[196] = {
+	.act_hid = BNXT_ULP_ACT_HID_134e,
+	.act_pattern_id = 138,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[197] = {
+	.act_hid = BNXT_ULP_ACT_HID_6d0a,
+	.act_pattern_id = 139,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[198] = {
+	.act_hid = BNXT_ULP_ACT_HID_576e,
+	.act_pattern_id = 140,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[199] = {
+	.act_hid = BNXT_ULP_ACT_HID_0ec2,
+	.act_pattern_id = 141,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[200] = {
+	.act_hid = BNXT_ULP_ACT_HID_025e,
+	.act_pattern_id = 142,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[201] = {
+	.act_hid = BNXT_ULP_ACT_HID_1fd2,
+	.act_pattern_id = 143,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[202] = {
+	.act_hid = BNXT_ULP_ACT_HID_440a,
+	.act_pattern_id = 144,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[203] = {
+	.act_hid = BNXT_ULP_ACT_HID_771a,
+	.act_pattern_id = 145,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[204] = {
+	.act_hid = BNXT_ULP_ACT_HID_551a,
+	.act_pattern_id = 146,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[205] = {
+	.act_hid = BNXT_ULP_ACT_HID_3f7e,
+	.act_pattern_id = 147,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[206] = {
+	.act_hid = BNXT_ULP_ACT_HID_728e,
+	.act_pattern_id = 148,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[207] = {
+	.act_hid = BNXT_ULP_ACT_HID_662a,
+	.act_pattern_id = 149,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[208] = {
+	.act_hid = BNXT_ULP_ACT_HID_07e2,
+	.act_pattern_id = 150,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[209] = {
+	.act_hid = BNXT_ULP_ACT_HID_4c0a,
+	.act_pattern_id = 151,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[210] = {
+	.act_hid = BNXT_ULP_ACT_HID_035e,
+	.act_pattern_id = 152,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[211] = {
+	.act_hid = BNXT_ULP_ACT_HID_5d1a,
+	.act_pattern_id = 153,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[212] = {
+	.act_hid = BNXT_ULP_ACT_HID_477e,
+	.act_pattern_id = 154,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[213] = {
+	.act_hid = BNXT_ULP_ACT_HID_7a8e,
+	.act_pattern_id = 155,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[214] = {
+	.act_hid = BNXT_ULP_ACT_HID_6e2a,
+	.act_pattern_id = 156,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[215] = {
+	.act_hid = BNXT_ULP_ACT_HID_0fe2,
+	.act_pattern_id = 157,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[216] = {
+	.act_hid = BNXT_ULP_ACT_HID_540a,
+	.act_pattern_id = 158,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[217] = {
+	.act_hid = BNXT_ULP_ACT_HID_0b5e,
+	.act_pattern_id = 159,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[218] = {
+	.act_hid = BNXT_ULP_ACT_HID_651a,
+	.act_pattern_id = 160,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[219] = {
+	.act_hid = BNXT_ULP_ACT_HID_4f7e,
+	.act_pattern_id = 161,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[220] = {
+	.act_hid = BNXT_ULP_ACT_HID_06d2,
+	.act_pattern_id = 162,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[221] = {
+	.act_hid = BNXT_ULP_ACT_HID_762a,
+	.act_pattern_id = 163,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[222] = {
+	.act_hid = BNXT_ULP_ACT_HID_17e2,
+	.act_pattern_id = 164,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[223] = {
+	.act_hid = BNXT_ULP_ACT_HID_5c0a,
+	.act_pattern_id = 165,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[224] = {
+	.act_hid = BNXT_ULP_ACT_HID_135e,
+	.act_pattern_id = 166,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[225] = {
+	.act_hid = BNXT_ULP_ACT_HID_6d1a,
+	.act_pattern_id = 167,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[226] = {
+	.act_hid = BNXT_ULP_ACT_HID_577e,
+	.act_pattern_id = 168,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[227] = {
+	.act_hid = BNXT_ULP_ACT_HID_0ed2,
+	.act_pattern_id = 169,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[228] = {
+	.act_hid = BNXT_ULP_ACT_HID_026e,
+	.act_pattern_id = 170,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[229] = {
+	.act_hid = BNXT_ULP_ACT_HID_1fe2,
+	.act_pattern_id = 171,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[230] = {
+	.act_hid = BNXT_ULP_ACT_HID_5d82,
+	.act_pattern_id = 172,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[231] = {
+	.act_hid = BNXT_ULP_ACT_HID_14d6,
+	.act_pattern_id = 173,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[232] = {
+	.act_hid = BNXT_ULP_ACT_HID_6e92,
+	.act_pattern_id = 174,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[233] = {
+	.act_hid = BNXT_ULP_ACT_HID_58f6,
+	.act_pattern_id = 175,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[234] = {
+	.act_hid = BNXT_ULP_ACT_HID_104a,
+	.act_pattern_id = 176,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[235] = {
+	.act_hid = BNXT_ULP_ACT_HID_215a,
+	.act_pattern_id = 177,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[236] = {
+	.act_hid = BNXT_ULP_ACT_HID_5d92,
+	.act_pattern_id = 178,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[237] = {
+	.act_hid = BNXT_ULP_ACT_HID_14e6,
+	.act_pattern_id = 179,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[238] = {
+	.act_hid = BNXT_ULP_ACT_HID_6ea2,
+	.act_pattern_id = 180,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[239] = {
+	.act_hid = BNXT_ULP_ACT_HID_5906,
+	.act_pattern_id = 181,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[240] = {
+	.act_hid = BNXT_ULP_ACT_HID_105a,
+	.act_pattern_id = 182,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[241] = {
+	.act_hid = BNXT_ULP_ACT_HID_216a,
+	.act_pattern_id = 183,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[242] = {
+	.act_hid = BNXT_ULP_ACT_HID_6582,
+	.act_pattern_id = 184,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[243] = {
+	.act_hid = BNXT_ULP_ACT_HID_1cd6,
+	.act_pattern_id = 185,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[244] = {
+	.act_hid = BNXT_ULP_ACT_HID_7692,
+	.act_pattern_id = 186,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[245] = {
+	.act_hid = BNXT_ULP_ACT_HID_60f6,
+	.act_pattern_id = 187,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[246] = {
+	.act_hid = BNXT_ULP_ACT_HID_184a,
+	.act_pattern_id = 188,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[247] = {
+	.act_hid = BNXT_ULP_ACT_HID_295a,
+	.act_pattern_id = 189,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[248] = {
+	.act_hid = BNXT_ULP_ACT_HID_6592,
+	.act_pattern_id = 190,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[249] = {
+	.act_hid = BNXT_ULP_ACT_HID_1ce6,
+	.act_pattern_id = 191,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[250] = {
+	.act_hid = BNXT_ULP_ACT_HID_76a2,
+	.act_pattern_id = 192,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[251] = {
+	.act_hid = BNXT_ULP_ACT_HID_6106,
+	.act_pattern_id = 193,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[252] = {
+	.act_hid = BNXT_ULP_ACT_HID_185a,
+	.act_pattern_id = 194,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[253] = {
+	.act_hid = BNXT_ULP_ACT_HID_296a,
+	.act_pattern_id = 195,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[254] = {
+	.act_hid = BNXT_ULP_ACT_HID_6d82,
+	.act_pattern_id = 196,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[255] = {
+	.act_hid = BNXT_ULP_ACT_HID_24d6,
+	.act_pattern_id = 197,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[256] = {
+	.act_hid = BNXT_ULP_ACT_HID_02d6,
+	.act_pattern_id = 198,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[257] = {
+	.act_hid = BNXT_ULP_ACT_HID_68f6,
+	.act_pattern_id = 199,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[258] = {
+	.act_hid = BNXT_ULP_ACT_HID_204a,
+	.act_pattern_id = 200,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[259] = {
+	.act_hid = BNXT_ULP_ACT_HID_315a,
+	.act_pattern_id = 201,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[260] = {
+	.act_hid = BNXT_ULP_ACT_HID_6d92,
+	.act_pattern_id = 202,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[261] = {
+	.act_hid = BNXT_ULP_ACT_HID_24e6,
+	.act_pattern_id = 203,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[262] = {
+	.act_hid = BNXT_ULP_ACT_HID_02e6,
+	.act_pattern_id = 204,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[263] = {
+	.act_hid = BNXT_ULP_ACT_HID_6906,
+	.act_pattern_id = 205,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[264] = {
+	.act_hid = BNXT_ULP_ACT_HID_205a,
+	.act_pattern_id = 206,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[265] = {
+	.act_hid = BNXT_ULP_ACT_HID_316a,
+	.act_pattern_id = 207,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[266] = {
+	.act_hid = BNXT_ULP_ACT_HID_7582,
+	.act_pattern_id = 208,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[267] = {
+	.act_hid = BNXT_ULP_ACT_HID_2cd6,
+	.act_pattern_id = 209,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[268] = {
+	.act_hid = BNXT_ULP_ACT_HID_0ad6,
+	.act_pattern_id = 210,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[269] = {
+	.act_hid = BNXT_ULP_ACT_HID_70f6,
+	.act_pattern_id = 211,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[270] = {
+	.act_hid = BNXT_ULP_ACT_HID_284a,
+	.act_pattern_id = 212,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[271] = {
+	.act_hid = BNXT_ULP_ACT_HID_395a,
+	.act_pattern_id = 213,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[272] = {
+	.act_hid = BNXT_ULP_ACT_HID_7592,
+	.act_pattern_id = 214,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[273] = {
+	.act_hid = BNXT_ULP_ACT_HID_2ce6,
+	.act_pattern_id = 215,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[274] = {
+	.act_hid = BNXT_ULP_ACT_HID_0ae6,
+	.act_pattern_id = 216,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[275] = {
+	.act_hid = BNXT_ULP_ACT_HID_7106,
+	.act_pattern_id = 217,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[276] = {
+	.act_hid = BNXT_ULP_ACT_HID_285a,
+	.act_pattern_id = 218,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[277] = {
+	.act_hid = BNXT_ULP_ACT_HID_396a,
+	.act_pattern_id = 219,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[278] = {
+	.act_hid = BNXT_ULP_ACT_HID_0020,
+	.act_pattern_id = 0,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_RSS |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 4
+	},
+	[279] = {
+	.act_hid = BNXT_ULP_ACT_HID_0030,
+	.act_pattern_id = 1,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_RSS |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 4
+	},
+	[280] = {
+	.act_hid = BNXT_ULP_ACT_HID_65d4,
+	.act_pattern_id = 2,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_QUEUE |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 4
+	},
+	[281] = {
+	.act_hid = BNXT_ULP_ACT_HID_65e4,
+	.act_pattern_id = 3,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_QUEUE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 4
+	},
+	[282] = {
+	.act_hid = BNXT_ULP_ACT_HID_330a,
+	.act_pattern_id = 4,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_RSS |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 4
+	},
+	[283] = {
+	.act_hid = BNXT_ULP_ACT_HID_331a,
+	.act_pattern_id = 5,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_RSS |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 4
+	},
+	[284] = {
+	.act_hid = BNXT_ULP_ACT_HID_1cfe,
+	.act_pattern_id = 6,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_QUEUE |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 4
+	},
+	[285] = {
+	.act_hid = BNXT_ULP_ACT_HID_1d0e,
+	.act_pattern_id = 7,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_QUEUE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 4
 	},
-	[56] = {
-	.act_hid = BNXT_ULP_ACT_HID_021e,
-	.act_pattern_id = 2,
+	[286] = {
+	.act_hid = BNXT_ULP_ACT_HID_1474,
+	.act_pattern_id = 0,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_METER_PROFILE |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 5
+	},
+	[287] = {
+	.act_hid = BNXT_ULP_ACT_HID_4838,
+	.act_pattern_id = 1,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_METER |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 5
+	},
+	[288] = {
+	.act_hid = BNXT_ULP_ACT_HID_6458,
+	.act_pattern_id = 2,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DELETE |
+		BNXT_ULP_ACT_BIT_METER_PROFILE |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 5
+	},
+	[289] = {
+	.act_hid = BNXT_ULP_ACT_HID_1c68,
+	.act_pattern_id = 3,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DELETE |
+		BNXT_ULP_ACT_BIT_SHARED_METER |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 5
+	},
+	[290] = {
+	.act_hid = BNXT_ULP_ACT_HID_6c34,
+	.act_pattern_id = 4,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_UPDATE |
+		BNXT_ULP_ACT_BIT_SHARED_METER |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 5
+	},
+	[291] = {
+	.act_hid = BNXT_ULP_ACT_HID_5d08,
+	.act_pattern_id = 0,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[292] = {
+	.act_hid = BNXT_ULP_ACT_HID_5d10,
+	.act_pattern_id = 1,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DROP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[293] = {
+	.act_hid = BNXT_ULP_ACT_HID_5d20,
+	.act_pattern_id = 2,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DROP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[294] = {
+	.act_hid = BNXT_ULP_ACT_HID_2e18,
+	.act_pattern_id = 3,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[295] = {
+	.act_hid = BNXT_ULP_ACT_HID_29d4,
+	.act_pattern_id = 4,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[296] = {
+	.act_hid = BNXT_ULP_ACT_HID_7690,
+	.act_pattern_id = 5,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[297] = {
+	.act_hid = BNXT_ULP_ACT_HID_47a0,
+	.act_pattern_id = 6,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[298] = {
+	.act_hid = BNXT_ULP_ACT_HID_435c,
+	.act_pattern_id = 7,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[299] = {
+	.act_hid = BNXT_ULP_ACT_HID_5d18,
+	.act_pattern_id = 8,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[300] = {
+	.act_hid = BNXT_ULP_ACT_HID_2e28,
+	.act_pattern_id = 9,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[301] = {
+	.act_hid = BNXT_ULP_ACT_HID_29e4,
+	.act_pattern_id = 10,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[302] = {
+	.act_hid = BNXT_ULP_ACT_HID_76a0,
+	.act_pattern_id = 11,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[303] = {
+	.act_hid = BNXT_ULP_ACT_HID_47b0,
+	.act_pattern_id = 12,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[304] = {
+	.act_hid = BNXT_ULP_ACT_HID_436c,
+	.act_pattern_id = 13,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[305] = {
+	.act_hid = BNXT_ULP_ACT_HID_1436,
+	.act_pattern_id = 14,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[306] = {
+	.act_hid = BNXT_ULP_ACT_HID_143e,
+	.act_pattern_id = 15,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DROP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[307] = {
+	.act_hid = BNXT_ULP_ACT_HID_144e,
+	.act_pattern_id = 16,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DROP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[308] = {
+	.act_hid = BNXT_ULP_ACT_HID_6102,
+	.act_pattern_id = 17,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[309] = {
+	.act_hid = BNXT_ULP_ACT_HID_5cbe,
+	.act_pattern_id = 18,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[310] = {
+	.act_hid = BNXT_ULP_ACT_HID_2dbe,
+	.act_pattern_id = 19,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[311] = {
+	.act_hid = BNXT_ULP_ACT_HID_7a8a,
+	.act_pattern_id = 20,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[312] = {
+	.act_hid = BNXT_ULP_ACT_HID_7646,
+	.act_pattern_id = 21,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[313] = {
+	.act_hid = BNXT_ULP_ACT_HID_1446,
+	.act_pattern_id = 22,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[314] = {
+	.act_hid = BNXT_ULP_ACT_HID_6112,
+	.act_pattern_id = 23,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[315] = {
+	.act_hid = BNXT_ULP_ACT_HID_5cce,
+	.act_pattern_id = 24,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[316] = {
+	.act_hid = BNXT_ULP_ACT_HID_2dce,
+	.act_pattern_id = 25,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[317] = {
+	.act_hid = BNXT_ULP_ACT_HID_7a9a,
+	.act_pattern_id = 26,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[318] = {
+	.act_hid = BNXT_ULP_ACT_HID_7656,
+	.act_pattern_id = 27,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[319] = {
+	.act_hid = BNXT_ULP_ACT_HID_6508,
+	.act_pattern_id = 0,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[320] = {
+	.act_hid = BNXT_ULP_ACT_HID_6d08,
+	.act_pattern_id = 1,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[321] = {
+	.act_hid = BNXT_ULP_ACT_HID_7508,
+	.act_pattern_id = 2,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[322] = {
+	.act_hid = BNXT_ULP_ACT_HID_6518,
+	.act_pattern_id = 3,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[323] = {
+	.act_hid = BNXT_ULP_ACT_HID_6d18,
+	.act_pattern_id = 4,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[324] = {
+	.act_hid = BNXT_ULP_ACT_HID_7518,
+	.act_pattern_id = 5,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[325] = {
+	.act_hid = BNXT_ULP_ACT_HID_6e18,
+	.act_pattern_id = 6,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[326] = {
+	.act_hid = BNXT_ULP_ACT_HID_256c,
+	.act_pattern_id = 7,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[327] = {
+	.act_hid = BNXT_ULP_ACT_HID_036c,
+	.act_pattern_id = 8,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[328] = {
+	.act_hid = BNXT_ULP_ACT_HID_698c,
+	.act_pattern_id = 9,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[329] = {
+	.act_hid = BNXT_ULP_ACT_HID_20e0,
+	.act_pattern_id = 10,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[330] = {
+	.act_hid = BNXT_ULP_ACT_HID_31f0,
+	.act_pattern_id = 11,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[331] = {
+	.act_hid = BNXT_ULP_ACT_HID_7618,
+	.act_pattern_id = 12,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[332] = {
+	.act_hid = BNXT_ULP_ACT_HID_2d6c,
+	.act_pattern_id = 13,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[333] = {
+	.act_hid = BNXT_ULP_ACT_HID_0b6c,
+	.act_pattern_id = 14,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[334] = {
+	.act_hid = BNXT_ULP_ACT_HID_718c,
+	.act_pattern_id = 15,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[335] = {
+	.act_hid = BNXT_ULP_ACT_HID_28e0,
+	.act_pattern_id = 16,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[336] = {
+	.act_hid = BNXT_ULP_ACT_HID_39f0,
+	.act_pattern_id = 17,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[337] = {
+	.act_hid = BNXT_ULP_ACT_HID_025c,
+	.act_pattern_id = 18,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[338] = {
+	.act_hid = BNXT_ULP_ACT_HID_356c,
+	.act_pattern_id = 19,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[339] = {
+	.act_hid = BNXT_ULP_ACT_HID_136c,
+	.act_pattern_id = 20,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[340] = {
+	.act_hid = BNXT_ULP_ACT_HID_798c,
+	.act_pattern_id = 21,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[341] = {
+	.act_hid = BNXT_ULP_ACT_HID_30e0,
+	.act_pattern_id = 22,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[342] = {
+	.act_hid = BNXT_ULP_ACT_HID_41f0,
+	.act_pattern_id = 23,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[343] = {
+	.act_hid = BNXT_ULP_ACT_HID_0a5c,
+	.act_pattern_id = 24,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[344] = {
+	.act_hid = BNXT_ULP_ACT_HID_3d6c,
+	.act_pattern_id = 25,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[345] = {
+	.act_hid = BNXT_ULP_ACT_HID_1b6c,
+	.act_pattern_id = 26,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[346] = {
+	.act_hid = BNXT_ULP_ACT_HID_05d0,
+	.act_pattern_id = 27,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[347] = {
+	.act_hid = BNXT_ULP_ACT_HID_38e0,
+	.act_pattern_id = 28,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[348] = {
+	.act_hid = BNXT_ULP_ACT_HID_49f0,
+	.act_pattern_id = 29,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[349] = {
+	.act_hid = BNXT_ULP_ACT_HID_6e28,
+	.act_pattern_id = 30,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[350] = {
+	.act_hid = BNXT_ULP_ACT_HID_257c,
+	.act_pattern_id = 31,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[351] = {
+	.act_hid = BNXT_ULP_ACT_HID_037c,
+	.act_pattern_id = 32,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[352] = {
+	.act_hid = BNXT_ULP_ACT_HID_699c,
+	.act_pattern_id = 33,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[353] = {
+	.act_hid = BNXT_ULP_ACT_HID_20f0,
+	.act_pattern_id = 34,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[354] = {
+	.act_hid = BNXT_ULP_ACT_HID_3200,
+	.act_pattern_id = 35,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[355] = {
+	.act_hid = BNXT_ULP_ACT_HID_7628,
+	.act_pattern_id = 36,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[356] = {
+	.act_hid = BNXT_ULP_ACT_HID_2d7c,
+	.act_pattern_id = 37,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[357] = {
+	.act_hid = BNXT_ULP_ACT_HID_0b7c,
+	.act_pattern_id = 38,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[358] = {
+	.act_hid = BNXT_ULP_ACT_HID_719c,
+	.act_pattern_id = 39,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[359] = {
+	.act_hid = BNXT_ULP_ACT_HID_28f0,
+	.act_pattern_id = 40,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[360] = {
+	.act_hid = BNXT_ULP_ACT_HID_3a00,
+	.act_pattern_id = 41,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[361] = {
+	.act_hid = BNXT_ULP_ACT_HID_026c,
+	.act_pattern_id = 42,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[362] = {
+	.act_hid = BNXT_ULP_ACT_HID_357c,
+	.act_pattern_id = 43,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[363] = {
+	.act_hid = BNXT_ULP_ACT_HID_137c,
+	.act_pattern_id = 44,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[364] = {
+	.act_hid = BNXT_ULP_ACT_HID_799c,
+	.act_pattern_id = 45,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[365] = {
+	.act_hid = BNXT_ULP_ACT_HID_30f0,
+	.act_pattern_id = 46,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[366] = {
+	.act_hid = BNXT_ULP_ACT_HID_4200,
+	.act_pattern_id = 47,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[367] = {
+	.act_hid = BNXT_ULP_ACT_HID_0a6c,
+	.act_pattern_id = 48,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[368] = {
+	.act_hid = BNXT_ULP_ACT_HID_3d7c,
+	.act_pattern_id = 49,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[369] = {
+	.act_hid = BNXT_ULP_ACT_HID_1b7c,
+	.act_pattern_id = 50,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[370] = {
+	.act_hid = BNXT_ULP_ACT_HID_05e0,
+	.act_pattern_id = 51,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[371] = {
+	.act_hid = BNXT_ULP_ACT_HID_38f0,
+	.act_pattern_id = 52,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[372] = {
+	.act_hid = BNXT_ULP_ACT_HID_4a00,
+	.act_pattern_id = 53,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[373] = {
+	.act_hid = BNXT_ULP_ACT_HID_0be4,
+	.act_pattern_id = 54,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[374] = {
+	.act_hid = BNXT_ULP_ACT_HID_3ef4,
+	.act_pattern_id = 55,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[375] = {
+	.act_hid = BNXT_ULP_ACT_HID_1cf4,
+	.act_pattern_id = 56,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[376] = {
+	.act_hid = BNXT_ULP_ACT_HID_0758,
+	.act_pattern_id = 57,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[377] = {
+	.act_hid = BNXT_ULP_ACT_HID_3a68,
+	.act_pattern_id = 58,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[378] = {
+	.act_hid = BNXT_ULP_ACT_HID_4b78,
+	.act_pattern_id = 59,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[379] = {
+	.act_hid = BNXT_ULP_ACT_HID_0bf4,
+	.act_pattern_id = 60,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[380] = {
+	.act_hid = BNXT_ULP_ACT_HID_3f04,
+	.act_pattern_id = 61,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[381] = {
+	.act_hid = BNXT_ULP_ACT_HID_1d04,
+	.act_pattern_id = 62,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[382] = {
+	.act_hid = BNXT_ULP_ACT_HID_0768,
+	.act_pattern_id = 63,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[383] = {
+	.act_hid = BNXT_ULP_ACT_HID_3a78,
+	.act_pattern_id = 64,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[384] = {
+	.act_hid = BNXT_ULP_ACT_HID_4b88,
+	.act_pattern_id = 65,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[385] = {
+	.act_hid = BNXT_ULP_ACT_HID_46f4,
+	.act_pattern_id = 66,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[386] = {
+	.act_hid = BNXT_ULP_ACT_HID_24f4,
+	.act_pattern_id = 67,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[387] = {
+	.act_hid = BNXT_ULP_ACT_HID_0f58,
+	.act_pattern_id = 68,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[388] = {
+	.act_hid = BNXT_ULP_ACT_HID_13e4,
+	.act_pattern_id = 69,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[389] = {
+	.act_hid = BNXT_ULP_ACT_HID_4268,
+	.act_pattern_id = 70,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[390] = {
+	.act_hid = BNXT_ULP_ACT_HID_5378,
+	.act_pattern_id = 71,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[391] = {
+	.act_hid = BNXT_ULP_ACT_HID_13f4,
+	.act_pattern_id = 72,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[392] = {
+	.act_hid = BNXT_ULP_ACT_HID_4704,
+	.act_pattern_id = 73,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[393] = {
+	.act_hid = BNXT_ULP_ACT_HID_2504,
+	.act_pattern_id = 74,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[394] = {
+	.act_hid = BNXT_ULP_ACT_HID_0f68,
+	.act_pattern_id = 75,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[395] = {
+	.act_hid = BNXT_ULP_ACT_HID_4278,
+	.act_pattern_id = 76,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[396] = {
+	.act_hid = BNXT_ULP_ACT_HID_5388,
+	.act_pattern_id = 77,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[397] = {
+	.act_hid = BNXT_ULP_ACT_HID_1be4,
+	.act_pattern_id = 78,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[398] = {
+	.act_hid = BNXT_ULP_ACT_HID_4ef4,
+	.act_pattern_id = 79,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[399] = {
+	.act_hid = BNXT_ULP_ACT_HID_2cf4,
+	.act_pattern_id = 80,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[400] = {
+	.act_hid = BNXT_ULP_ACT_HID_1758,
+	.act_pattern_id = 81,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[401] = {
+	.act_hid = BNXT_ULP_ACT_HID_4a68,
+	.act_pattern_id = 82,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[402] = {
+	.act_hid = BNXT_ULP_ACT_HID_5b78,
+	.act_pattern_id = 83,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[403] = {
+	.act_hid = BNXT_ULP_ACT_HID_1bf4,
+	.act_pattern_id = 84,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[404] = {
+	.act_hid = BNXT_ULP_ACT_HID_4f04,
+	.act_pattern_id = 85,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[405] = {
+	.act_hid = BNXT_ULP_ACT_HID_2d04,
+	.act_pattern_id = 86,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[406] = {
+	.act_hid = BNXT_ULP_ACT_HID_1768,
+	.act_pattern_id = 87,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[407] = {
+	.act_hid = BNXT_ULP_ACT_HID_4a78,
+	.act_pattern_id = 88,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[408] = {
+	.act_hid = BNXT_ULP_ACT_HID_5b88,
+	.act_pattern_id = 89,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[409] = {
+	.act_hid = BNXT_ULP_ACT_HID_23e4,
+	.act_pattern_id = 90,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[410] = {
+	.act_hid = BNXT_ULP_ACT_HID_56f4,
+	.act_pattern_id = 91,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[411] = {
+	.act_hid = BNXT_ULP_ACT_HID_34f4,
+	.act_pattern_id = 92,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[412] = {
+	.act_hid = BNXT_ULP_ACT_HID_1f58,
+	.act_pattern_id = 93,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[413] = {
+	.act_hid = BNXT_ULP_ACT_HID_5268,
+	.act_pattern_id = 94,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[414] = {
+	.act_hid = BNXT_ULP_ACT_HID_6378,
+	.act_pattern_id = 95,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[415] = {
+	.act_hid = BNXT_ULP_ACT_HID_23f4,
+	.act_pattern_id = 96,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[416] = {
+	.act_hid = BNXT_ULP_ACT_HID_5704,
+	.act_pattern_id = 97,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[417] = {
+	.act_hid = BNXT_ULP_ACT_HID_3504,
+	.act_pattern_id = 98,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[418] = {
+	.act_hid = BNXT_ULP_ACT_HID_1f68,
+	.act_pattern_id = 99,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[419] = {
+	.act_hid = BNXT_ULP_ACT_HID_5278,
+	.act_pattern_id = 100,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[420] = {
+	.act_hid = BNXT_ULP_ACT_HID_6388,
+	.act_pattern_id = 101,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[421] = {
+	.act_hid = BNXT_ULP_ACT_HID_1c36,
+	.act_pattern_id = 102,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[422] = {
+	.act_hid = BNXT_ULP_ACT_HID_2436,
+	.act_pattern_id = 103,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[423] = {
+	.act_hid = BNXT_ULP_ACT_HID_2c36,
+	.act_pattern_id = 104,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[424] = {
+	.act_hid = BNXT_ULP_ACT_HID_1c46,
+	.act_pattern_id = 105,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[425] = {
+	.act_hid = BNXT_ULP_ACT_HID_2446,
+	.act_pattern_id = 106,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[426] = {
+	.act_hid = BNXT_ULP_ACT_HID_2c46,
+	.act_pattern_id = 107,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[427] = {
+	.act_hid = BNXT_ULP_ACT_HID_2546,
+	.act_pattern_id = 108,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[428] = {
+	.act_hid = BNXT_ULP_ACT_HID_5856,
+	.act_pattern_id = 109,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[429] = {
+	.act_hid = BNXT_ULP_ACT_HID_3656,
+	.act_pattern_id = 110,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[430] = {
+	.act_hid = BNXT_ULP_ACT_HID_20ba,
+	.act_pattern_id = 111,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[431] = {
+	.act_hid = BNXT_ULP_ACT_HID_53ca,
+	.act_pattern_id = 112,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[432] = {
+	.act_hid = BNXT_ULP_ACT_HID_64da,
+	.act_pattern_id = 113,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[433] = {
+	.act_hid = BNXT_ULP_ACT_HID_2d46,
+	.act_pattern_id = 114,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[434] = {
+	.act_hid = BNXT_ULP_ACT_HID_6056,
+	.act_pattern_id = 115,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[435] = {
+	.act_hid = BNXT_ULP_ACT_HID_3e56,
+	.act_pattern_id = 116,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[436] = {
+	.act_hid = BNXT_ULP_ACT_HID_28ba,
+	.act_pattern_id = 117,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[437] = {
+	.act_hid = BNXT_ULP_ACT_HID_5bca,
+	.act_pattern_id = 118,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[438] = {
+	.act_hid = BNXT_ULP_ACT_HID_6cda,
+	.act_pattern_id = 119,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[439] = {
+	.act_hid = BNXT_ULP_ACT_HID_3546,
+	.act_pattern_id = 120,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[440] = {
+	.act_hid = BNXT_ULP_ACT_HID_6856,
+	.act_pattern_id = 121,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[441] = {
+	.act_hid = BNXT_ULP_ACT_HID_4656,
+	.act_pattern_id = 122,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[442] = {
+	.act_hid = BNXT_ULP_ACT_HID_30ba,
+	.act_pattern_id = 123,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[443] = {
+	.act_hid = BNXT_ULP_ACT_HID_63ca,
+	.act_pattern_id = 124,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[444] = {
+	.act_hid = BNXT_ULP_ACT_HID_74da,
+	.act_pattern_id = 125,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[445] = {
+	.act_hid = BNXT_ULP_ACT_HID_3d46,
+	.act_pattern_id = 126,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[446] = {
+	.act_hid = BNXT_ULP_ACT_HID_7056,
+	.act_pattern_id = 127,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[447] = {
+	.act_hid = BNXT_ULP_ACT_HID_4e56,
+	.act_pattern_id = 128,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[448] = {
+	.act_hid = BNXT_ULP_ACT_HID_38ba,
+	.act_pattern_id = 129,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[449] = {
+	.act_hid = BNXT_ULP_ACT_HID_6bca,
+	.act_pattern_id = 130,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[450] = {
+	.act_hid = BNXT_ULP_ACT_HID_011e,
+	.act_pattern_id = 131,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[451] = {
+	.act_hid = BNXT_ULP_ACT_HID_2556,
+	.act_pattern_id = 132,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[452] = {
+	.act_hid = BNXT_ULP_ACT_HID_5866,
+	.act_pattern_id = 133,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[453] = {
+	.act_hid = BNXT_ULP_ACT_HID_3666,
+	.act_pattern_id = 134,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[454] = {
+	.act_hid = BNXT_ULP_ACT_HID_20ca,
+	.act_pattern_id = 135,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[455] = {
+	.act_hid = BNXT_ULP_ACT_HID_53da,
+	.act_pattern_id = 136,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[456] = {
+	.act_hid = BNXT_ULP_ACT_HID_64ea,
+	.act_pattern_id = 137,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[457] = {
+	.act_hid = BNXT_ULP_ACT_HID_2d56,
+	.act_pattern_id = 138,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[458] = {
+	.act_hid = BNXT_ULP_ACT_HID_6066,
+	.act_pattern_id = 139,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[459] = {
+	.act_hid = BNXT_ULP_ACT_HID_3e66,
+	.act_pattern_id = 140,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[460] = {
+	.act_hid = BNXT_ULP_ACT_HID_28ca,
+	.act_pattern_id = 141,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[461] = {
+	.act_hid = BNXT_ULP_ACT_HID_5bda,
+	.act_pattern_id = 142,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[462] = {
+	.act_hid = BNXT_ULP_ACT_HID_6cea,
+	.act_pattern_id = 143,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[463] = {
+	.act_hid = BNXT_ULP_ACT_HID_3556,
+	.act_pattern_id = 144,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[464] = {
+	.act_hid = BNXT_ULP_ACT_HID_6866,
+	.act_pattern_id = 145,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[465] = {
+	.act_hid = BNXT_ULP_ACT_HID_4666,
+	.act_pattern_id = 146,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[466] = {
+	.act_hid = BNXT_ULP_ACT_HID_30ca,
+	.act_pattern_id = 147,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[467] = {
+	.act_hid = BNXT_ULP_ACT_HID_63da,
+	.act_pattern_id = 148,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[468] = {
+	.act_hid = BNXT_ULP_ACT_HID_74ea,
+	.act_pattern_id = 149,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[469] = {
+	.act_hid = BNXT_ULP_ACT_HID_3d56,
+	.act_pattern_id = 150,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_DROP |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[57] = {
-	.act_hid = BNXT_ULP_ACT_HID_063f,
-	.act_pattern_id = 3,
+	[470] = {
+	.act_hid = BNXT_ULP_ACT_HID_7066,
+	.act_pattern_id = 151,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
-		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
-		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[58] = {
-	.act_hid = BNXT_ULP_ACT_HID_0510,
-	.act_pattern_id = 4,
+	[471] = {
+	.act_hid = BNXT_ULP_ACT_HID_4e66,
+	.act_pattern_id = 152,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
-		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[59] = {
-	.act_hid = BNXT_ULP_ACT_HID_03c6,
-	.act_pattern_id = 5,
+	[472] = {
+	.act_hid = BNXT_ULP_ACT_HID_38ca,
+	.act_pattern_id = 153,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[473] = {
+	.act_hid = BNXT_ULP_ACT_HID_6bda,
+	.act_pattern_id = 154,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[474] = {
+	.act_hid = BNXT_ULP_ACT_HID_012e,
+	.act_pattern_id = 155,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[475] = {
+	.act_hid = BNXT_ULP_ACT_HID_3ece,
+	.act_pattern_id = 156,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[60] = {
-	.act_hid = BNXT_ULP_ACT_HID_0082,
-	.act_pattern_id = 6,
+	[476] = {
+	.act_hid = BNXT_ULP_ACT_HID_71de,
+	.act_pattern_id = 157,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
-		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
-		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[61] = {
-	.act_hid = BNXT_ULP_ACT_HID_06bb,
-	.act_pattern_id = 7,
+	[477] = {
+	.act_hid = BNXT_ULP_ACT_HID_4fde,
+	.act_pattern_id = 158,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
-		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[62] = {
-	.act_hid = BNXT_ULP_ACT_HID_021d,
-	.act_pattern_id = 8,
+	[478] = {
+	.act_hid = BNXT_ULP_ACT_HID_3a42,
+	.act_pattern_id = 159,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[479] = {
+	.act_hid = BNXT_ULP_ACT_HID_6d52,
+	.act_pattern_id = 160,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[480] = {
+	.act_hid = BNXT_ULP_ACT_HID_02a6,
+	.act_pattern_id = 161,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[481] = {
+	.act_hid = BNXT_ULP_ACT_HID_3ede,
+	.act_pattern_id = 162,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[63] = {
-	.act_hid = BNXT_ULP_ACT_HID_0641,
-	.act_pattern_id = 9,
+	[482] = {
+	.act_hid = BNXT_ULP_ACT_HID_71ee,
+	.act_pattern_id = 163,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
-		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
-		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[64] = {
-	.act_hid = BNXT_ULP_ACT_HID_0512,
-	.act_pattern_id = 10,
+	[483] = {
+	.act_hid = BNXT_ULP_ACT_HID_4fee,
+	.act_pattern_id = 164,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
-		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[65] = {
-	.act_hid = BNXT_ULP_ACT_HID_03c8,
-	.act_pattern_id = 11,
+	[484] = {
+	.act_hid = BNXT_ULP_ACT_HID_3a52,
+	.act_pattern_id = 165,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[485] = {
+	.act_hid = BNXT_ULP_ACT_HID_6d62,
+	.act_pattern_id = 166,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[486] = {
+	.act_hid = BNXT_ULP_ACT_HID_02b6,
+	.act_pattern_id = 167,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[66] = {
-	.act_hid = BNXT_ULP_ACT_HID_0084,
-	.act_pattern_id = 12,
+	[487] = {
+	.act_hid = BNXT_ULP_ACT_HID_79de,
+	.act_pattern_id = 168,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[488] = {
+	.act_hid = BNXT_ULP_ACT_HID_57de,
+	.act_pattern_id = 169,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[489] = {
+	.act_hid = BNXT_ULP_ACT_HID_4242,
+	.act_pattern_id = 170,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[490] = {
+	.act_hid = BNXT_ULP_ACT_HID_46ce,
+	.act_pattern_id = 171,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[491] = {
+	.act_hid = BNXT_ULP_ACT_HID_7552,
+	.act_pattern_id = 172,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[492] = {
+	.act_hid = BNXT_ULP_ACT_HID_0aa6,
+	.act_pattern_id = 173,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[493] = {
+	.act_hid = BNXT_ULP_ACT_HID_46de,
+	.act_pattern_id = 174,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[494] = {
+	.act_hid = BNXT_ULP_ACT_HID_79ee,
+	.act_pattern_id = 175,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
-		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
-		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[67] = {
-	.act_hid = BNXT_ULP_ACT_HID_06bd,
-	.act_pattern_id = 13,
+	[495] = {
+	.act_hid = BNXT_ULP_ACT_HID_57ee,
+	.act_pattern_id = 176,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[496] = {
+	.act_hid = BNXT_ULP_ACT_HID_4252,
+	.act_pattern_id = 177,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[497] = {
+	.act_hid = BNXT_ULP_ACT_HID_7562,
+	.act_pattern_id = 178,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
-		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
-		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 4
+	.act_tid = 7
 	},
-	[68] = {
-	.act_hid = BNXT_ULP_ACT_HID_06d7,
-	.act_pattern_id = 0,
+	[498] = {
+	.act_hid = BNXT_ULP_ACT_HID_0ab6,
+	.act_pattern_id = 179,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 7
+	},
+	[499] = {
+	.act_hid = BNXT_ULP_ACT_HID_4ece,
+	.act_pattern_id = 180,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[69] = {
-	.act_hid = BNXT_ULP_ACT_HID_02c4,
-	.act_pattern_id = 1,
+	[500] = {
+	.act_hid = BNXT_ULP_ACT_HID_0622,
+	.act_pattern_id = 181,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[70] = {
-	.act_hid = BNXT_ULP_ACT_HID_042a,
-	.act_pattern_id = 2,
+	[501] = {
+	.act_hid = BNXT_ULP_ACT_HID_5fde,
+	.act_pattern_id = 182,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[71] = {
-	.act_hid = BNXT_ULP_ACT_HID_036e,
-	.act_pattern_id = 3,
+	[502] = {
+	.act_hid = BNXT_ULP_ACT_HID_4a42,
+	.act_pattern_id = 183,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[72] = {
-	.act_hid = BNXT_ULP_ACT_HID_06c4,
-	.act_pattern_id = 4,
+	[503] = {
+	.act_hid = BNXT_ULP_ACT_HID_0196,
+	.act_pattern_id = 184,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[73] = {
-	.act_hid = BNXT_ULP_ACT_HID_0417,
-	.act_pattern_id = 5,
+	[504] = {
+	.act_hid = BNXT_ULP_ACT_HID_12a6,
+	.act_pattern_id = 185,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[74] = {
-	.act_hid = BNXT_ULP_ACT_HID_06d9,
-	.act_pattern_id = 6,
+	[505] = {
+	.act_hid = BNXT_ULP_ACT_HID_4ede,
+	.act_pattern_id = 186,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[75] = {
-	.act_hid = BNXT_ULP_ACT_HID_02c6,
-	.act_pattern_id = 7,
+	[506] = {
+	.act_hid = BNXT_ULP_ACT_HID_0632,
+	.act_pattern_id = 187,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[76] = {
-	.act_hid = BNXT_ULP_ACT_HID_042c,
-	.act_pattern_id = 8,
+	[507] = {
+	.act_hid = BNXT_ULP_ACT_HID_5fee,
+	.act_pattern_id = 188,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[77] = {
-	.act_hid = BNXT_ULP_ACT_HID_0370,
-	.act_pattern_id = 9,
+	[508] = {
+	.act_hid = BNXT_ULP_ACT_HID_4a52,
+	.act_pattern_id = 189,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[78] = {
-	.act_hid = BNXT_ULP_ACT_HID_06c6,
-	.act_pattern_id = 10,
+	[509] = {
+	.act_hid = BNXT_ULP_ACT_HID_01a6,
+	.act_pattern_id = 190,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[79] = {
-	.act_hid = BNXT_ULP_ACT_HID_0419,
-	.act_pattern_id = 11,
+	[510] = {
+	.act_hid = BNXT_ULP_ACT_HID_12b6,
+	.act_pattern_id = 191,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[80] = {
-	.act_hid = BNXT_ULP_ACT_HID_0119,
-	.act_pattern_id = 12,
+	[511] = {
+	.act_hid = BNXT_ULP_ACT_HID_56ce,
+	.act_pattern_id = 192,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[81] = {
-	.act_hid = BNXT_ULP_ACT_HID_046f,
-	.act_pattern_id = 13,
+	[512] = {
+	.act_hid = BNXT_ULP_ACT_HID_0e22,
+	.act_pattern_id = 193,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[82] = {
-	.act_hid = BNXT_ULP_ACT_HID_05d5,
-	.act_pattern_id = 14,
+	[513] = {
+	.act_hid = BNXT_ULP_ACT_HID_67de,
+	.act_pattern_id = 194,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[83] = {
-	.act_hid = BNXT_ULP_ACT_HID_0519,
-	.act_pattern_id = 15,
+	[514] = {
+	.act_hid = BNXT_ULP_ACT_HID_5242,
+	.act_pattern_id = 195,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[84] = {
-	.act_hid = BNXT_ULP_ACT_HID_0106,
-	.act_pattern_id = 16,
+	[515] = {
+	.act_hid = BNXT_ULP_ACT_HID_0996,
+	.act_pattern_id = 196,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[85] = {
-	.act_hid = BNXT_ULP_ACT_HID_05c2,
-	.act_pattern_id = 17,
+	[516] = {
+	.act_hid = BNXT_ULP_ACT_HID_1aa6,
+	.act_pattern_id = 197,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[86] = {
-	.act_hid = BNXT_ULP_ACT_HID_011b,
-	.act_pattern_id = 18,
+	[517] = {
+	.act_hid = BNXT_ULP_ACT_HID_56de,
+	.act_pattern_id = 198,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[87] = {
-	.act_hid = BNXT_ULP_ACT_HID_0471,
-	.act_pattern_id = 19,
+	[518] = {
+	.act_hid = BNXT_ULP_ACT_HID_0e32,
+	.act_pattern_id = 199,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[88] = {
-	.act_hid = BNXT_ULP_ACT_HID_05d7,
-	.act_pattern_id = 20,
+	[519] = {
+	.act_hid = BNXT_ULP_ACT_HID_67ee,
+	.act_pattern_id = 200,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[89] = {
-	.act_hid = BNXT_ULP_ACT_HID_051b,
-	.act_pattern_id = 21,
+	[520] = {
+	.act_hid = BNXT_ULP_ACT_HID_5252,
+	.act_pattern_id = 201,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[90] = {
-	.act_hid = BNXT_ULP_ACT_HID_0108,
-	.act_pattern_id = 22,
+	[521] = {
+	.act_hid = BNXT_ULP_ACT_HID_09a6,
+	.act_pattern_id = 202,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[91] = {
-	.act_hid = BNXT_ULP_ACT_HID_05c4,
-	.act_pattern_id = 23,
+	[522] = {
+	.act_hid = BNXT_ULP_ACT_HID_1ab6,
+	.act_pattern_id = 203,
 	.app_sig = 0,
 	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
@@ -1089,25 +6906,256 @@  struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 5
+	.act_tid = 7
 	},
-	[92] = {
-	.act_hid = BNXT_ULP_ACT_HID_00a2,
+	[523] = {
+	.act_hid = BNXT_ULP_ACT_HID_31d0,
 	.act_pattern_id = 0,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 6
+	.act_tid = 8
 	},
-	[93] = {
-	.act_hid = BNXT_ULP_ACT_HID_00a4,
+	[524] = {
+	.act_hid = BNXT_ULP_ACT_HID_31e0,
 	.act_pattern_id = 1,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 6
+	.act_tid = 8
+	},
+	[525] = {
+	.act_hid = BNXT_ULP_ACT_HID_39d0,
+	.act_pattern_id = 2,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[526] = {
+	.act_hid = BNXT_ULP_ACT_HID_39e0,
+	.act_pattern_id = 3,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[527] = {
+	.act_hid = BNXT_ULP_ACT_HID_41d0,
+	.act_pattern_id = 4,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[528] = {
+	.act_hid = BNXT_ULP_ACT_HID_41e0,
+	.act_pattern_id = 5,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[529] = {
+	.act_hid = BNXT_ULP_ACT_HID_49d0,
+	.act_pattern_id = 6,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[530] = {
+	.act_hid = BNXT_ULP_ACT_HID_49e0,
+	.act_pattern_id = 7,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[531] = {
+	.act_hid = BNXT_ULP_ACT_HID_64ba,
+	.act_pattern_id = 8,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[532] = {
+	.act_hid = BNXT_ULP_ACT_HID_64ca,
+	.act_pattern_id = 9,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[533] = {
+	.act_hid = BNXT_ULP_ACT_HID_6cba,
+	.act_pattern_id = 10,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[534] = {
+	.act_hid = BNXT_ULP_ACT_HID_6cca,
+	.act_pattern_id = 11,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[535] = {
+	.act_hid = BNXT_ULP_ACT_HID_74ba,
+	.act_pattern_id = 12,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[536] = {
+	.act_hid = BNXT_ULP_ACT_HID_74ca,
+	.act_pattern_id = 13,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[537] = {
+	.act_hid = BNXT_ULP_ACT_HID_00fe,
+	.act_pattern_id = 14,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[538] = {
+	.act_hid = BNXT_ULP_ACT_HID_010e,
+	.act_pattern_id = 15,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+		BNXT_ULP_ACT_BIT_SET_MAC_DST |
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 8
+	},
+	[539] = {
+	.act_hid = BNXT_ULP_ACT_HID_331c,
+	.act_pattern_id = 0,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_VF_TO_VF |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 9
+	},
+	[540] = {
+	.act_hid = BNXT_ULP_ACT_HID_332c,
+	.act_pattern_id = 1,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_VF_TO_VF |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 9
+	},
+	[541] = {
+	.act_hid = BNXT_ULP_ACT_HID_6706,
+	.act_pattern_id = 2,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_VF_TO_VF |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 9
+	},
+	[542] = {
+	.act_hid = BNXT_ULP_ACT_HID_6716,
+	.act_pattern_id = 3,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_ACT_BIT_VF_TO_VF |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 9
+	},
+	[543] = {
+	.act_hid = BNXT_ULP_ACT_HID_1b6d,
+	.act_pattern_id = 0,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED |
+		BNXT_ULP_ACT_BIT_SAMPLE |
+		BNXT_ULP_ACT_BIT_VF_TO_VF |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 10
+	},
+	[544] = {
+	.act_hid = BNXT_ULP_ACT_HID_1b7d,
+	.act_pattern_id = 1,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SHARED |
+		BNXT_ULP_ACT_BIT_SAMPLE |
+		BNXT_ULP_ACT_BIT_VF_TO_VF |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 10
+	},
+	[545] = {
+	.act_hid = BNXT_ULP_ACT_HID_641a,
+	.act_pattern_id = 2,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DELETE |
+		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 10
 	}
 };
+
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
index c127a53b32..70409edb68 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
@@ -1,10 +1,8 @@ 
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
  * All rights reserved.
  */
 
-/* date: Wed Nov 24 17:15:38 2021 */
-
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
 #include "ulp_template_struct.h"
@@ -16,1308 +14,1918 @@ 
  * maps hash id to ulp_class_match_list[] index
  */
 uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
-	[BNXT_ULP_CLASS_HID_55dd] = 1,
-	[BNXT_ULP_CLASS_HID_1df1] = 2,
-	[BNXT_ULP_CLASS_HID_3e55] = 3,
-	[BNXT_ULP_CLASS_HID_0649] = 4,
-	[BNXT_ULP_CLASS_HID_1011] = 5,
-	[BNXT_ULP_CLASS_HID_40e9] = 6,
-	[BNXT_ULP_CLASS_HID_3e99] = 7,
-	[BNXT_ULP_CLASS_HID_06ad] = 8,
-	[BNXT_ULP_CLASS_HID_38c7] = 9,
-	[BNXT_ULP_CLASS_HID_00fb] = 10,
-	[BNXT_ULP_CLASS_HID_24d3] = 11,
-	[BNXT_ULP_CLASS_HID_559b] = 12,
-	[BNXT_ULP_CLASS_HID_5003] = 13,
-	[BNXT_ULP_CLASS_HID_1837] = 14,
-	[BNXT_ULP_CLASS_HID_3bef] = 15,
-	[BNXT_ULP_CLASS_HID_0403] = 16,
-	[BNXT_ULP_CLASS_HID_3d3f] = 17,
-	[BNXT_ULP_CLASS_HID_0543] = 18,
-	[BNXT_ULP_CLASS_HID_292b] = 19,
-	[BNXT_ULP_CLASS_HID_59e3] = 20,
-	[BNXT_ULP_CLASS_HID_5d3b] = 21,
-	[BNXT_ULP_CLASS_HID_254f] = 22,
-	[BNXT_ULP_CLASS_HID_4917] = 23,
-	[BNXT_ULP_CLASS_HID_113b] = 24,
-	[BNXT_ULP_CLASS_HID_55fd] = 25,
-	[BNXT_ULP_CLASS_HID_1dd1] = 26,
-	[BNXT_ULP_CLASS_HID_3e75] = 27,
-	[BNXT_ULP_CLASS_HID_0669] = 28,
-	[BNXT_ULP_CLASS_HID_1ba1] = 29,
-	[BNXT_ULP_CLASS_HID_4c69] = 30,
-	[BNXT_ULP_CLASS_HID_0439] = 31,
-	[BNXT_ULP_CLASS_HID_34e1] = 32,
-	[BNXT_ULP_CLASS_HID_0465] = 33,
-	[BNXT_ULP_CLASS_HID_352d] = 34,
-	[BNXT_ULP_CLASS_HID_55b1] = 35,
-	[BNXT_ULP_CLASS_HID_1da5] = 36,
-	[BNXT_ULP_CLASS_HID_32fd] = 37,
-	[BNXT_ULP_CLASS_HID_63a5] = 38,
-	[BNXT_ULP_CLASS_HID_1b75] = 39,
-	[BNXT_ULP_CLASS_HID_4c3d] = 40,
-	[BNXT_ULP_CLASS_HID_1031] = 41,
-	[BNXT_ULP_CLASS_HID_40c9] = 42,
-	[BNXT_ULP_CLASS_HID_3eb9] = 43,
-	[BNXT_ULP_CLASS_HID_068d] = 44,
-	[BNXT_ULP_CLASS_HID_5039] = 45,
-	[BNXT_ULP_CLASS_HID_180d] = 46,
-	[BNXT_ULP_CLASS_HID_15fd] = 47,
-	[BNXT_ULP_CLASS_HID_46b5] = 48,
-	[BNXT_ULP_CLASS_HID_303d] = 49,
-	[BNXT_ULP_CLASS_HID_60f5] = 50,
-	[BNXT_ULP_CLASS_HID_5ea5] = 51,
-	[BNXT_ULP_CLASS_HID_2689] = 52,
-	[BNXT_ULP_CLASS_HID_0771] = 53,
-	[BNXT_ULP_CLASS_HID_3809] = 54,
-	[BNXT_ULP_CLASS_HID_35f9] = 55,
-	[BNXT_ULP_CLASS_HID_66b1] = 56,
-	[BNXT_ULP_CLASS_HID_559d] = 57,
-	[BNXT_ULP_CLASS_HID_1db1] = 58,
-	[BNXT_ULP_CLASS_HID_3e15] = 59,
-	[BNXT_ULP_CLASS_HID_0609] = 60,
-	[BNXT_ULP_CLASS_HID_1bc1] = 61,
-	[BNXT_ULP_CLASS_HID_4c09] = 62,
-	[BNXT_ULP_CLASS_HID_0459] = 63,
-	[BNXT_ULP_CLASS_HID_3481] = 64,
-	[BNXT_ULP_CLASS_HID_0405] = 65,
-	[BNXT_ULP_CLASS_HID_354d] = 66,
-	[BNXT_ULP_CLASS_HID_55d1] = 67,
-	[BNXT_ULP_CLASS_HID_1dc5] = 68,
-	[BNXT_ULP_CLASS_HID_329d] = 69,
-	[BNXT_ULP_CLASS_HID_63c5] = 70,
-	[BNXT_ULP_CLASS_HID_1b15] = 71,
-	[BNXT_ULP_CLASS_HID_4c5d] = 72,
-	[BNXT_ULP_CLASS_HID_1051] = 73,
-	[BNXT_ULP_CLASS_HID_40a9] = 74,
-	[BNXT_ULP_CLASS_HID_3ed9] = 75,
-	[BNXT_ULP_CLASS_HID_06ed] = 76,
-	[BNXT_ULP_CLASS_HID_5059] = 77,
-	[BNXT_ULP_CLASS_HID_186d] = 78,
-	[BNXT_ULP_CLASS_HID_159d] = 79,
-	[BNXT_ULP_CLASS_HID_46d5] = 80,
-	[BNXT_ULP_CLASS_HID_305d] = 81,
-	[BNXT_ULP_CLASS_HID_6095] = 82,
-	[BNXT_ULP_CLASS_HID_5ec5] = 83,
-	[BNXT_ULP_CLASS_HID_26e9] = 84,
-	[BNXT_ULP_CLASS_HID_0711] = 85,
-	[BNXT_ULP_CLASS_HID_3869] = 86,
-	[BNXT_ULP_CLASS_HID_3599] = 87,
-	[BNXT_ULP_CLASS_HID_66d1] = 88,
-	[BNXT_ULP_CLASS_HID_38e7] = 89,
-	[BNXT_ULP_CLASS_HID_00db] = 90,
-	[BNXT_ULP_CLASS_HID_24f3] = 91,
-	[BNXT_ULP_CLASS_HID_55bb] = 92,
-	[BNXT_ULP_CLASS_HID_5023] = 93,
-	[BNXT_ULP_CLASS_HID_1817] = 94,
-	[BNXT_ULP_CLASS_HID_3bcf] = 95,
-	[BNXT_ULP_CLASS_HID_0423] = 96,
-	[BNXT_ULP_CLASS_HID_58e3] = 97,
-	[BNXT_ULP_CLASS_HID_20d7] = 98,
-	[BNXT_ULP_CLASS_HID_448f] = 99,
-	[BNXT_ULP_CLASS_HID_0ce3] = 100,
-	[BNXT_ULP_CLASS_HID_076b] = 101,
-	[BNXT_ULP_CLASS_HID_3813] = 102,
-	[BNXT_ULP_CLASS_HID_5bcb] = 103,
-	[BNXT_ULP_CLASS_HID_243f] = 104,
-	[BNXT_ULP_CLASS_HID_144b] = 105,
-	[BNXT_ULP_CLASS_HID_4573] = 106,
-	[BNXT_ULP_CLASS_HID_0057] = 107,
-	[BNXT_ULP_CLASS_HID_311f] = 108,
-	[BNXT_ULP_CLASS_HID_2b87] = 109,
-	[BNXT_ULP_CLASS_HID_5c4f] = 110,
-	[BNXT_ULP_CLASS_HID_1793] = 111,
-	[BNXT_ULP_CLASS_HID_485b] = 112,
-	[BNXT_ULP_CLASS_HID_3447] = 113,
-	[BNXT_ULP_CLASS_HID_650f] = 114,
-	[BNXT_ULP_CLASS_HID_2053] = 115,
-	[BNXT_ULP_CLASS_HID_511b] = 116,
-	[BNXT_ULP_CLASS_HID_4b83] = 117,
-	[BNXT_ULP_CLASS_HID_13f7] = 118,
-	[BNXT_ULP_CLASS_HID_37af] = 119,
-	[BNXT_ULP_CLASS_HID_6857] = 120,
-	[BNXT_ULP_CLASS_HID_3d1f] = 121,
-	[BNXT_ULP_CLASS_HID_0563] = 122,
-	[BNXT_ULP_CLASS_HID_290b] = 123,
-	[BNXT_ULP_CLASS_HID_59c3] = 124,
-	[BNXT_ULP_CLASS_HID_5d1b] = 125,
-	[BNXT_ULP_CLASS_HID_256f] = 126,
-	[BNXT_ULP_CLASS_HID_4937] = 127,
-	[BNXT_ULP_CLASS_HID_111b] = 128,
-	[BNXT_ULP_CLASS_HID_25f4b] = 129,
-	[BNXT_ULP_CLASS_HID_2275f] = 130,
-	[BNXT_ULP_CLASS_HID_24b67] = 131,
-	[BNXT_ULP_CLASS_HID_2134b] = 132,
-	[BNXT_ULP_CLASS_HID_21683] = 133,
-	[BNXT_ULP_CLASS_HID_2475b] = 134,
-	[BNXT_ULP_CLASS_HID_202bf] = 135,
-	[BNXT_ULP_CLASS_HID_23377] = 136,
-	[BNXT_ULP_CLASS_HID_119db] = 137,
-	[BNXT_ULP_CLASS_HID_14a93] = 138,
-	[BNXT_ULP_CLASS_HID_105f7] = 139,
-	[BNXT_ULP_CLASS_HID_1368f] = 140,
-	[BNXT_ULP_CLASS_HID_139c7] = 141,
-	[BNXT_ULP_CLASS_HID_1022b] = 142,
-	[BNXT_ULP_CLASS_HID_125f3] = 143,
-	[BNXT_ULP_CLASS_HID_1568b] = 144,
-	[BNXT_ULP_CLASS_HID_33c37] = 145,
-	[BNXT_ULP_CLASS_HID_3041b] = 146,
-	[BNXT_ULP_CLASS_HID_32823] = 147,
-	[BNXT_ULP_CLASS_HID_358fb] = 148,
-	[BNXT_ULP_CLASS_HID_35c33] = 149,
-	[BNXT_ULP_CLASS_HID_32407] = 150,
-	[BNXT_ULP_CLASS_HID_3482f] = 151,
-	[BNXT_ULP_CLASS_HID_31033] = 152,
-	[BNXT_ULP_CLASS_HID_3887] = 153,
-	[BNXT_ULP_CLASS_HID_00bb] = 154,
-	[BNXT_ULP_CLASS_HID_2493] = 155,
-	[BNXT_ULP_CLASS_HID_55db] = 156,
-	[BNXT_ULP_CLASS_HID_5043] = 157,
-	[BNXT_ULP_CLASS_HID_1877] = 158,
-	[BNXT_ULP_CLASS_HID_3baf] = 159,
-	[BNXT_ULP_CLASS_HID_0443] = 160,
-	[BNXT_ULP_CLASS_HID_5883] = 161,
-	[BNXT_ULP_CLASS_HID_20b7] = 162,
-	[BNXT_ULP_CLASS_HID_44ef] = 163,
-	[BNXT_ULP_CLASS_HID_0c83] = 164,
-	[BNXT_ULP_CLASS_HID_070b] = 165,
-	[BNXT_ULP_CLASS_HID_3873] = 166,
-	[BNXT_ULP_CLASS_HID_5bab] = 167,
-	[BNXT_ULP_CLASS_HID_245f] = 168,
-	[BNXT_ULP_CLASS_HID_142b] = 169,
-	[BNXT_ULP_CLASS_HID_4513] = 170,
-	[BNXT_ULP_CLASS_HID_0037] = 171,
-	[BNXT_ULP_CLASS_HID_317f] = 172,
-	[BNXT_ULP_CLASS_HID_2be7] = 173,
-	[BNXT_ULP_CLASS_HID_5c2f] = 174,
-	[BNXT_ULP_CLASS_HID_17f3] = 175,
-	[BNXT_ULP_CLASS_HID_483b] = 176,
-	[BNXT_ULP_CLASS_HID_3427] = 177,
-	[BNXT_ULP_CLASS_HID_656f] = 178,
-	[BNXT_ULP_CLASS_HID_2033] = 179,
-	[BNXT_ULP_CLASS_HID_517b] = 180,
-	[BNXT_ULP_CLASS_HID_4be3] = 181,
-	[BNXT_ULP_CLASS_HID_1397] = 182,
-	[BNXT_ULP_CLASS_HID_37cf] = 183,
-	[BNXT_ULP_CLASS_HID_6837] = 184,
-	[BNXT_ULP_CLASS_HID_3d7f] = 185,
-	[BNXT_ULP_CLASS_HID_0503] = 186,
-	[BNXT_ULP_CLASS_HID_296b] = 187,
-	[BNXT_ULP_CLASS_HID_59a3] = 188,
-	[BNXT_ULP_CLASS_HID_5d7b] = 189,
-	[BNXT_ULP_CLASS_HID_250f] = 190,
-	[BNXT_ULP_CLASS_HID_4957] = 191,
-	[BNXT_ULP_CLASS_HID_117b] = 192,
-	[BNXT_ULP_CLASS_HID_25f2b] = 193,
-	[BNXT_ULP_CLASS_HID_2273f] = 194,
-	[BNXT_ULP_CLASS_HID_24b07] = 195,
-	[BNXT_ULP_CLASS_HID_2132b] = 196,
-	[BNXT_ULP_CLASS_HID_216e3] = 197,
-	[BNXT_ULP_CLASS_HID_2473b] = 198,
-	[BNXT_ULP_CLASS_HID_202df] = 199,
-	[BNXT_ULP_CLASS_HID_23317] = 200,
-	[BNXT_ULP_CLASS_HID_119bb] = 201,
-	[BNXT_ULP_CLASS_HID_14af3] = 202,
-	[BNXT_ULP_CLASS_HID_10597] = 203,
-	[BNXT_ULP_CLASS_HID_136ef] = 204,
-	[BNXT_ULP_CLASS_HID_139a7] = 205,
-	[BNXT_ULP_CLASS_HID_1024b] = 206,
-	[BNXT_ULP_CLASS_HID_12593] = 207,
-	[BNXT_ULP_CLASS_HID_156eb] = 208,
-	[BNXT_ULP_CLASS_HID_33c57] = 209,
-	[BNXT_ULP_CLASS_HID_3047b] = 210,
-	[BNXT_ULP_CLASS_HID_32843] = 211,
-	[BNXT_ULP_CLASS_HID_3589b] = 212,
-	[BNXT_ULP_CLASS_HID_35c53] = 213,
-	[BNXT_ULP_CLASS_HID_32467] = 214,
-	[BNXT_ULP_CLASS_HID_3484f] = 215,
-	[BNXT_ULP_CLASS_HID_31053] = 216,
-	[BNXT_ULP_CLASS_HID_5ce1] = 217,
-	[BNXT_ULP_CLASS_HID_4579] = 218,
-	[BNXT_ULP_CLASS_HID_1735] = 219,
-	[BNXT_ULP_CLASS_HID_45bd] = 220,
-	[BNXT_ULP_CLASS_HID_3feb] = 221,
-	[BNXT_ULP_CLASS_HID_2bf7] = 222,
-	[BNXT_ULP_CLASS_HID_5727] = 223,
-	[BNXT_ULP_CLASS_HID_4333] = 224,
-	[BNXT_ULP_CLASS_HID_4453] = 225,
-	[BNXT_ULP_CLASS_HID_304f] = 226,
-	[BNXT_ULP_CLASS_HID_645f] = 227,
-	[BNXT_ULP_CLASS_HID_504b] = 228,
-	[BNXT_ULP_CLASS_HID_5cc1] = 229,
-	[BNXT_ULP_CLASS_HID_4559] = 230,
-	[BNXT_ULP_CLASS_HID_2285] = 231,
-	[BNXT_ULP_CLASS_HID_0b1d] = 232,
-	[BNXT_ULP_CLASS_HID_0b49] = 233,
-	[BNXT_ULP_CLASS_HID_5c95] = 234,
-	[BNXT_ULP_CLASS_HID_39c1] = 235,
-	[BNXT_ULP_CLASS_HID_2259] = 236,
-	[BNXT_ULP_CLASS_HID_1715] = 237,
-	[BNXT_ULP_CLASS_HID_459d] = 238,
-	[BNXT_ULP_CLASS_HID_571d] = 239,
-	[BNXT_ULP_CLASS_HID_1cd1] = 240,
-	[BNXT_ULP_CLASS_HID_3711] = 241,
-	[BNXT_ULP_CLASS_HID_6599] = 242,
-	[BNXT_ULP_CLASS_HID_0e55] = 243,
-	[BNXT_ULP_CLASS_HID_3cdd] = 244,
-	[BNXT_ULP_CLASS_HID_5ca1] = 245,
-	[BNXT_ULP_CLASS_HID_4539] = 246,
-	[BNXT_ULP_CLASS_HID_22e5] = 247,
-	[BNXT_ULP_CLASS_HID_0b7d] = 248,
-	[BNXT_ULP_CLASS_HID_0b29] = 249,
-	[BNXT_ULP_CLASS_HID_5cf5] = 250,
-	[BNXT_ULP_CLASS_HID_39a1] = 251,
-	[BNXT_ULP_CLASS_HID_2239] = 252,
-	[BNXT_ULP_CLASS_HID_1775] = 253,
-	[BNXT_ULP_CLASS_HID_45fd] = 254,
-	[BNXT_ULP_CLASS_HID_577d] = 255,
-	[BNXT_ULP_CLASS_HID_1cb1] = 256,
-	[BNXT_ULP_CLASS_HID_3771] = 257,
-	[BNXT_ULP_CLASS_HID_65f9] = 258,
-	[BNXT_ULP_CLASS_HID_0e35] = 259,
-	[BNXT_ULP_CLASS_HID_3cbd] = 260,
-	[BNXT_ULP_CLASS_HID_3fcb] = 261,
-	[BNXT_ULP_CLASS_HID_2bd7] = 262,
-	[BNXT_ULP_CLASS_HID_5707] = 263,
-	[BNXT_ULP_CLASS_HID_4313] = 264,
-	[BNXT_ULP_CLASS_HID_5fc7] = 265,
-	[BNXT_ULP_CLASS_HID_4bd3] = 266,
-	[BNXT_ULP_CLASS_HID_0e4f] = 267,
-	[BNXT_ULP_CLASS_HID_632f] = 268,
-	[BNXT_ULP_CLASS_HID_1baf] = 269,
-	[BNXT_ULP_CLASS_HID_07bb] = 270,
-	[BNXT_ULP_CLASS_HID_32eb] = 271,
-	[BNXT_ULP_CLASS_HID_1ef7] = 272,
-	[BNXT_ULP_CLASS_HID_3bab] = 273,
-	[BNXT_ULP_CLASS_HID_27b7] = 274,
-	[BNXT_ULP_CLASS_HID_52e7] = 275,
-	[BNXT_ULP_CLASS_HID_3ef3] = 276,
-	[BNXT_ULP_CLASS_HID_4473] = 277,
-	[BNXT_ULP_CLASS_HID_306f] = 278,
-	[BNXT_ULP_CLASS_HID_647f] = 279,
-	[BNXT_ULP_CLASS_HID_506b] = 280,
-	[BNXT_ULP_CLASS_HID_266af] = 281,
-	[BNXT_ULP_CLASS_HID_2525b] = 282,
-	[BNXT_ULP_CLASS_HID_21de7] = 283,
-	[BNXT_ULP_CLASS_HID_20993] = 284,
-	[BNXT_ULP_CLASS_HID_1213f] = 285,
-	[BNXT_ULP_CLASS_HID_10d2b] = 286,
-	[BNXT_ULP_CLASS_HID_1413b] = 287,
-	[BNXT_ULP_CLASS_HID_12cd7] = 288,
-	[BNXT_ULP_CLASS_HID_3436b] = 289,
-	[BNXT_ULP_CLASS_HID_32f07] = 290,
-	[BNXT_ULP_CLASS_HID_36317] = 291,
-	[BNXT_ULP_CLASS_HID_34f03] = 292,
-	[BNXT_ULP_CLASS_HID_3fab] = 293,
-	[BNXT_ULP_CLASS_HID_2bb7] = 294,
-	[BNXT_ULP_CLASS_HID_5767] = 295,
-	[BNXT_ULP_CLASS_HID_4373] = 296,
-	[BNXT_ULP_CLASS_HID_5fa7] = 297,
-	[BNXT_ULP_CLASS_HID_4bb3] = 298,
-	[BNXT_ULP_CLASS_HID_0e2f] = 299,
-	[BNXT_ULP_CLASS_HID_634f] = 300,
-	[BNXT_ULP_CLASS_HID_1bcf] = 301,
-	[BNXT_ULP_CLASS_HID_07db] = 302,
-	[BNXT_ULP_CLASS_HID_328b] = 303,
-	[BNXT_ULP_CLASS_HID_1e97] = 304,
-	[BNXT_ULP_CLASS_HID_3bcb] = 305,
-	[BNXT_ULP_CLASS_HID_27d7] = 306,
-	[BNXT_ULP_CLASS_HID_5287] = 307,
-	[BNXT_ULP_CLASS_HID_3e93] = 308,
-	[BNXT_ULP_CLASS_HID_4413] = 309,
-	[BNXT_ULP_CLASS_HID_300f] = 310,
-	[BNXT_ULP_CLASS_HID_641f] = 311,
-	[BNXT_ULP_CLASS_HID_500b] = 312,
-	[BNXT_ULP_CLASS_HID_266cf] = 313,
-	[BNXT_ULP_CLASS_HID_2523b] = 314,
-	[BNXT_ULP_CLASS_HID_21d87] = 315,
-	[BNXT_ULP_CLASS_HID_209f3] = 316,
-	[BNXT_ULP_CLASS_HID_1215f] = 317,
-	[BNXT_ULP_CLASS_HID_10d4b] = 318,
-	[BNXT_ULP_CLASS_HID_1415b] = 319,
-	[BNXT_ULP_CLASS_HID_12cb7] = 320,
-	[BNXT_ULP_CLASS_HID_3430b] = 321,
-	[BNXT_ULP_CLASS_HID_32f67] = 322,
-	[BNXT_ULP_CLASS_HID_36377] = 323,
-	[BNXT_ULP_CLASS_HID_34f63] = 324,
-	[BNXT_ULP_CLASS_HID_29b5] = 325,
-	[BNXT_ULP_CLASS_HID_29ad] = 326,
-	[BNXT_ULP_CLASS_HID_29b7] = 327,
-	[BNXT_ULP_CLASS_HID_1583] = 328,
-	[BNXT_ULP_CLASS_HID_29af] = 329,
-	[BNXT_ULP_CLASS_HID_159b] = 330,
-	[BNXT_ULP_CLASS_HID_2995] = 331,
-	[BNXT_ULP_CLASS_HID_298d] = 332,
-	[BNXT_ULP_CLASS_HID_29f5] = 333,
-	[BNXT_ULP_CLASS_HID_29ed] = 334,
-	[BNXT_ULP_CLASS_HID_2997] = 335,
-	[BNXT_ULP_CLASS_HID_15a3] = 336,
-	[BNXT_ULP_CLASS_HID_298f] = 337,
-	[BNXT_ULP_CLASS_HID_15bb] = 338,
-	[BNXT_ULP_CLASS_HID_29f7] = 339,
-	[BNXT_ULP_CLASS_HID_15c3] = 340,
-	[BNXT_ULP_CLASS_HID_29ef] = 341,
-	[BNXT_ULP_CLASS_HID_15db] = 342,
-	[BNXT_ULP_CLASS_HID_1151] = 343,
-	[BNXT_ULP_CLASS_HID_315d] = 344,
-	[BNXT_ULP_CLASS_HID_3612] = 345,
-	[BNXT_ULP_CLASS_HID_66da] = 346,
-	[BNXT_ULP_CLASS_HID_243ca] = 347,
-	[BNXT_ULP_CLASS_HID_20d8e] = 348,
-	[BNXT_ULP_CLASS_HID_2e082] = 349,
-	[BNXT_ULP_CLASS_HID_2ab46] = 350,
-	[BNXT_ULP_CLASS_HID_25226] = 351,
-	[BNXT_ULP_CLASS_HID_25cea] = 352,
-	[BNXT_ULP_CLASS_HID_2c82a] = 353,
-	[BNXT_ULP_CLASS_HID_2f9a2] = 354,
-	[BNXT_ULP_CLASS_HID_23b56] = 355,
-	[BNXT_ULP_CLASS_HID_205da] = 356,
-	[BNXT_ULP_CLASS_HID_2d8ce] = 357,
-	[BNXT_ULP_CLASS_HID_2a2d2] = 358,
-	[BNXT_ULP_CLASS_HID_24a72] = 359,
-	[BNXT_ULP_CLASS_HID_25476] = 360,
-	[BNXT_ULP_CLASS_HID_2c076] = 361,
-	[BNXT_ULP_CLASS_HID_2f1ee] = 362,
-	[BNXT_ULP_CLASS_HID_20bb6] = 363,
-	[BNXT_ULP_CLASS_HID_23d2e] = 364,
-	[BNXT_ULP_CLASS_HID_2a96e] = 365,
-	[BNXT_ULP_CLASS_HID_2dae6] = 366,
-	[BNXT_ULP_CLASS_HID_25af2] = 367,
-	[BNXT_ULP_CLASS_HID_24c6a] = 368,
-	[BNXT_ULP_CLASS_HID_2c7aa] = 369,
-	[BNXT_ULP_CLASS_HID_2c26e] = 370,
-	[BNXT_ULP_CLASS_HID_203e2] = 371,
-	[BNXT_ULP_CLASS_HID_2357a] = 372,
-	[BNXT_ULP_CLASS_HID_2a0fa] = 373,
-	[BNXT_ULP_CLASS_HID_2d272] = 374,
-	[BNXT_ULP_CLASS_HID_2527e] = 375,
-	[BNXT_ULP_CLASS_HID_243f6] = 376,
-	[BNXT_ULP_CLASS_HID_2fff6] = 377,
-	[BNXT_ULP_CLASS_HID_2e16e] = 378,
-	[BNXT_ULP_CLASS_HID_2422d] = 379,
-	[BNXT_ULP_CLASS_HID_20c69] = 380,
-	[BNXT_ULP_CLASS_HID_2e165] = 381,
-	[BNXT_ULP_CLASS_HID_2aaa1] = 382,
-	[BNXT_ULP_CLASS_HID_253c1] = 383,
-	[BNXT_ULP_CLASS_HID_25d0d] = 384,
-	[BNXT_ULP_CLASS_HID_2c9cd] = 385,
-	[BNXT_ULP_CLASS_HID_2f845] = 386,
-	[BNXT_ULP_CLASS_HID_25afd] = 387,
-	[BNXT_ULP_CLASS_HID_22439] = 388,
-	[BNXT_ULP_CLASS_HID_290f9] = 389,
-	[BNXT_ULP_CLASS_HID_2c371] = 390,
-	[BNXT_ULP_CLASS_HID_24355] = 391,
-	[BNXT_ULP_CLASS_HID_275dd] = 392,
-	[BNXT_ULP_CLASS_HID_2e19d] = 393,
-	[BNXT_ULP_CLASS_HID_2d015] = 394,
-	[BNXT_ULP_CLASS_HID_2560d] = 395,
-	[BNXT_ULP_CLASS_HID_21049] = 396,
-	[BNXT_ULP_CLASS_HID_28c09] = 397,
-	[BNXT_ULP_CLASS_HID_2be89] = 398,
-	[BNXT_ULP_CLASS_HID_267a9] = 399,
-	[BNXT_ULP_CLASS_HID_261ed] = 400,
-	[BNXT_ULP_CLASS_HID_2ddad] = 401,
-	[BNXT_ULP_CLASS_HID_2cc2d] = 402,
-	[BNXT_ULP_CLASS_HID_26edd] = 403,
-	[BNXT_ULP_CLASS_HID_22819] = 404,
-	[BNXT_ULP_CLASS_HID_2a4d9] = 405,
-	[BNXT_ULP_CLASS_HID_2d759] = 406,
-	[BNXT_ULP_CLASS_HID_2573d] = 407,
-	[BNXT_ULP_CLASS_HID_279bd] = 408,
-	[BNXT_ULP_CLASS_HID_2f27d] = 409,
-	[BNXT_ULP_CLASS_HID_2e4fd] = 410,
-	[BNXT_ULP_CLASS_HID_24fbe] = 411,
-	[BNXT_ULP_CLASS_HID_201fa] = 412,
-	[BNXT_ULP_CLASS_HID_2ecf6] = 413,
-	[BNXT_ULP_CLASS_HID_2a732] = 414,
-	[BNXT_ULP_CLASS_HID_25e52] = 415,
-	[BNXT_ULP_CLASS_HID_2509e] = 416,
-	[BNXT_ULP_CLASS_HID_2c45e] = 417,
-	[BNXT_ULP_CLASS_HID_2f5d6] = 418,
-	[BNXT_ULP_CLASS_HID_23722] = 419,
-	[BNXT_ULP_CLASS_HID_209ae] = 420,
-	[BNXT_ULP_CLASS_HID_2d4ba] = 421,
-	[BNXT_ULP_CLASS_HID_2aea6] = 422,
-	[BNXT_ULP_CLASS_HID_24606] = 423,
-	[BNXT_ULP_CLASS_HID_25802] = 424,
-	[BNXT_ULP_CLASS_HID_2cc02] = 425,
-	[BNXT_ULP_CLASS_HID_2fd9a] = 426,
-	[BNXT_ULP_CLASS_HID_207c2] = 427,
-	[BNXT_ULP_CLASS_HID_2315a] = 428,
-	[BNXT_ULP_CLASS_HID_2a51a] = 429,
-	[BNXT_ULP_CLASS_HID_2d692] = 430,
-	[BNXT_ULP_CLASS_HID_25686] = 431,
-	[BNXT_ULP_CLASS_HID_2401e] = 432,
-	[BNXT_ULP_CLASS_HID_2cbde] = 433,
-	[BNXT_ULP_CLASS_HID_2ce1a] = 434,
-	[BNXT_ULP_CLASS_HID_20f96] = 435,
-	[BNXT_ULP_CLASS_HID_2390e] = 436,
-	[BNXT_ULP_CLASS_HID_2ac8e] = 437,
-	[BNXT_ULP_CLASS_HID_2de06] = 438,
-	[BNXT_ULP_CLASS_HID_25e0a] = 439,
-	[BNXT_ULP_CLASS_HID_24f82] = 440,
-	[BNXT_ULP_CLASS_HID_2f382] = 441,
-	[BNXT_ULP_CLASS_HID_2ed1a] = 442,
-	[BNXT_ULP_CLASS_HID_2576e] = 443,
-	[BNXT_ULP_CLASS_HID_229aa] = 444,
-	[BNXT_ULP_CLASS_HID_29d6a] = 445,
-	[BNXT_ULP_CLASS_HID_2cee2] = 446,
-	[BNXT_ULP_CLASS_HID_24ec6] = 447,
-	[BNXT_ULP_CLASS_HID_2784e] = 448,
-	[BNXT_ULP_CLASS_HID_2ec0e] = 449,
-	[BNXT_ULP_CLASS_HID_2dd86] = 450,
-	[BNXT_ULP_CLASS_HID_25f22] = 451,
-	[BNXT_ULP_CLASS_HID_2112e] = 452,
-	[BNXT_ULP_CLASS_HID_2852e] = 453,
-	[BNXT_ULP_CLASS_HID_2b6a6] = 454,
-	[BNXT_ULP_CLASS_HID_26d86] = 455,
-	[BNXT_ULP_CLASS_HID_26002] = 456,
-	[BNXT_ULP_CLASS_HID_2eb82] = 457,
-	[BNXT_ULP_CLASS_HID_2c50a] = 458,
-	[BNXT_ULP_CLASS_HID_22f82] = 459,
-	[BNXT_ULP_CLASS_HID_2590a] = 460,
-	[BNXT_ULP_CLASS_HID_2ccca] = 461,
-	[BNXT_ULP_CLASS_HID_28706] = 462,
-	[BNXT_ULP_CLASS_HID_27e46] = 463,
-	[BNXT_ULP_CLASS_HID_26fce] = 464,
-	[BNXT_ULP_CLASS_HID_2d38e] = 465,
-	[BNXT_ULP_CLASS_HID_2d5ca] = 466,
-	[BNXT_ULP_CLASS_HID_21706] = 467,
-	[BNXT_ULP_CLASS_HID_2408e] = 468,
-	[BNXT_ULP_CLASS_HID_2b48e] = 469,
-	[BNXT_ULP_CLASS_HID_28e8a] = 470,
-	[BNXT_ULP_CLASS_HID_2660a] = 471,
-	[BNXT_ULP_CLASS_HID_25782] = 472,
-	[BNXT_ULP_CLASS_HID_2db02] = 473,
-	[BNXT_ULP_CLASS_HID_2dd8e] = 474,
-	[BNXT_ULP_CLASS_HID_25b9e] = 475,
-	[BNXT_ULP_CLASS_HID_21dda] = 476,
-	[BNXT_ULP_CLASS_HID_2819a] = 477,
-	[BNXT_ULP_CLASS_HID_2b31a] = 478,
-	[BNXT_ULP_CLASS_HID_26a3a] = 479,
-	[BNXT_ULP_CLASS_HID_26c7e] = 480,
-	[BNXT_ULP_CLASS_HID_2d03e] = 481,
-	[BNXT_ULP_CLASS_HID_2c1be] = 482,
-	[BNXT_ULP_CLASS_HID_2430a] = 483,
-	[BNXT_ULP_CLASS_HID_2058e] = 484,
-	[BNXT_ULP_CLASS_HID_2890e] = 485,
-	[BNXT_ULP_CLASS_HID_2ba8e] = 486,
-	[BNXT_ULP_CLASS_HID_251ae] = 487,
-	[BNXT_ULP_CLASS_HID_2542a] = 488,
-	[BNXT_ULP_CLASS_HID_2dfaa] = 489,
-	[BNXT_ULP_CLASS_HID_2c93a] = 490,
-	[BNXT_ULP_CLASS_HID_213ca] = 491,
-	[BNXT_ULP_CLASS_HID_24d5a] = 492,
-	[BNXT_ULP_CLASS_HID_2b11a] = 493,
-	[BNXT_ULP_CLASS_HID_28b4e] = 494,
-	[BNXT_ULP_CLASS_HID_2624e] = 495,
-	[BNXT_ULP_CLASS_HID_253de] = 496,
-	[BNXT_ULP_CLASS_HID_2c79e] = 497,
-	[BNXT_ULP_CLASS_HID_2d9da] = 498,
-	[BNXT_ULP_CLASS_HID_21b1e] = 499,
-	[BNXT_ULP_CLASS_HID_2350e] = 500,
-	[BNXT_ULP_CLASS_HID_2b88e] = 501,
-	[BNXT_ULP_CLASS_HID_2ea0e] = 502,
-	[BNXT_ULP_CLASS_HID_26a0a] = 503,
-	[BNXT_ULP_CLASS_HID_25b8a] = 504,
-	[BNXT_ULP_CLASS_HID_2cf0a] = 505,
-	[BNXT_ULP_CLASS_HID_2c18e] = 506,
-	[BNXT_ULP_CLASS_HID_2634e] = 507,
-	[BNXT_ULP_CLASS_HID_2258a] = 508,
-	[BNXT_ULP_CLASS_HID_2a94a] = 509,
-	[BNXT_ULP_CLASS_HID_2daca] = 510,
-	[BNXT_ULP_CLASS_HID_25aae] = 511,
-	[BNXT_ULP_CLASS_HID_2742e] = 512,
-	[BNXT_ULP_CLASS_HID_2ffee] = 513,
-	[BNXT_ULP_CLASS_HID_2e96e] = 514,
-	[BNXT_ULP_CLASS_HID_26b0a] = 515,
-	[BNXT_ULP_CLASS_HID_22d0e] = 516,
-	[BNXT_ULP_CLASS_HID_2910e] = 517,
-	[BNXT_ULP_CLASS_HID_2c28e] = 518,
-	[BNXT_ULP_CLASS_HID_2422a] = 519,
-	[BNXT_ULP_CLASS_HID_273aa] = 520,
-	[BNXT_ULP_CLASS_HID_2e7aa] = 521,
-	[BNXT_ULP_CLASS_HID_2d12a] = 522,
-	[BNXT_ULP_CLASS_HID_23b8a] = 523,
-	[BNXT_ULP_CLASS_HID_2550a] = 524,
-	[BNXT_ULP_CLASS_HID_2d8ca] = 525,
-	[BNXT_ULP_CLASS_HID_2930e] = 526,
-	[BNXT_ULP_CLASS_HID_24a0e] = 527,
-	[BNXT_ULP_CLASS_HID_24c4a] = 528,
-	[BNXT_ULP_CLASS_HID_2ef4e] = 529,
-	[BNXT_ULP_CLASS_HID_2e18a] = 530,
-	[BNXT_ULP_CLASS_HID_2230e] = 531,
-	[BNXT_ULP_CLASS_HID_25c8e] = 532,
-	[BNXT_ULP_CLASS_HID_2c08e] = 533,
-	[BNXT_ULP_CLASS_HID_29a8a] = 534,
-	[BNXT_ULP_CLASS_HID_2718a] = 535,
-	[BNXT_ULP_CLASS_HID_2630a] = 536,
-	[BNXT_ULP_CLASS_HID_2d70a] = 537,
-	[BNXT_ULP_CLASS_HID_2e90e] = 538,
-	[BNXT_ULP_CLASS_HID_24e91] = 539,
-	[BNXT_ULP_CLASS_HID_200d5] = 540,
-	[BNXT_ULP_CLASS_HID_2edd9] = 541,
-	[BNXT_ULP_CLASS_HID_2a61d] = 542,
-	[BNXT_ULP_CLASS_HID_25f7d] = 543,
-	[BNXT_ULP_CLASS_HID_251b1] = 544,
-	[BNXT_ULP_CLASS_HID_2c571] = 545,
-	[BNXT_ULP_CLASS_HID_2f4f9] = 546,
-	[BNXT_ULP_CLASS_HID_25641] = 547,
-	[BNXT_ULP_CLASS_HID_22885] = 548,
-	[BNXT_ULP_CLASS_HID_29c45] = 549,
-	[BNXT_ULP_CLASS_HID_2cfcd] = 550,
-	[BNXT_ULP_CLASS_HID_24fe9] = 551,
-	[BNXT_ULP_CLASS_HID_27961] = 552,
-	[BNXT_ULP_CLASS_HID_2ed21] = 553,
-	[BNXT_ULP_CLASS_HID_2dca9] = 554,
-	[BNXT_ULP_CLASS_HID_25ab1] = 555,
-	[BNXT_ULP_CLASS_HID_21cf5] = 556,
-	[BNXT_ULP_CLASS_HID_280b5] = 557,
-	[BNXT_ULP_CLASS_HID_2b235] = 558,
-	[BNXT_ULP_CLASS_HID_26b15] = 559,
-	[BNXT_ULP_CLASS_HID_26d51] = 560,
-	[BNXT_ULP_CLASS_HID_2d111] = 561,
-	[BNXT_ULP_CLASS_HID_2c091] = 562,
-	[BNXT_ULP_CLASS_HID_26261] = 563,
-	[BNXT_ULP_CLASS_HID_224a5] = 564,
-	[BNXT_ULP_CLASS_HID_2a865] = 565,
-	[BNXT_ULP_CLASS_HID_2dbe5] = 566,
-	[BNXT_ULP_CLASS_HID_25b81] = 567,
-	[BNXT_ULP_CLASS_HID_27501] = 568,
-	[BNXT_ULP_CLASS_HID_2fec1] = 569,
-	[BNXT_ULP_CLASS_HID_2e841] = 570,
-	[BNXT_ULP_CLASS_HID_24085] = 571,
-	[BNXT_ULP_CLASS_HID_21ac5] = 572,
-	[BNXT_ULP_CLASS_HID_28e85] = 573,
-	[BNXT_ULP_CLASS_HID_2b80d] = 574,
-	[BNXT_ULP_CLASS_HID_2516d] = 575,
-	[BNXT_ULP_CLASS_HID_26ba5] = 576,
-	[BNXT_ULP_CLASS_HID_2df65] = 577,
-	[BNXT_ULP_CLASS_HID_2ceed] = 578,
-	[BNXT_ULP_CLASS_HID_26845] = 579,
-	[BNXT_ULP_CLASS_HID_22285] = 580,
-	[BNXT_ULP_CLASS_HID_29645] = 581,
-	[BNXT_ULP_CLASS_HID_2c1cd] = 582,
-	[BNXT_ULP_CLASS_HID_2418d] = 583,
-	[BNXT_ULP_CLASS_HID_27365] = 584,
-	[BNXT_ULP_CLASS_HID_2e725] = 585,
-	[BNXT_ULP_CLASS_HID_2d6ad] = 586,
-	[BNXT_ULP_CLASS_HID_25ca5] = 587,
-	[BNXT_ULP_CLASS_HID_216e5] = 588,
-	[BNXT_ULP_CLASS_HID_29aa5] = 589,
-	[BNXT_ULP_CLASS_HID_2b425] = 590,
-	[BNXT_ULP_CLASS_HID_26d05] = 591,
-	[BNXT_ULP_CLASS_HID_26745] = 592,
-	[BNXT_ULP_CLASS_HID_2eb05] = 593,
-	[BNXT_ULP_CLASS_HID_2da85] = 594,
-	[BNXT_ULP_CLASS_HID_20cc5] = 595,
-	[BNXT_ULP_CLASS_HID_23ea5] = 596,
-	[BNXT_ULP_CLASS_HID_2a265] = 597,
-	[BNXT_ULP_CLASS_HID_2dde5] = 598,
-	[BNXT_ULP_CLASS_HID_25da5] = 599,
-	[BNXT_ULP_CLASS_HID_24f05] = 600,
-	[BNXT_ULP_CLASS_HID_2f0c5] = 601,
-	[BNXT_ULP_CLASS_HID_2e245] = 602,
-	[BNXT_ULP_CLASS_HID_24d8b] = 603,
-	[BNXT_ULP_CLASS_HID_207cf] = 604,
-	[BNXT_ULP_CLASS_HID_28b8f] = 605,
-	[BNXT_ULP_CLASS_HID_2a517] = 606,
-	[BNXT_ULP_CLASS_HID_25277] = 607,
-	[BNXT_ULP_CLASS_HID_254ab] = 608,
-	[BNXT_ULP_CLASS_HID_2d86b] = 609,
-	[BNXT_ULP_CLASS_HID_2cbf3] = 610,
-	[BNXT_ULP_CLASS_HID_2554b] = 611,
-	[BNXT_ULP_CLASS_HID_22f8f] = 612,
-	[BNXT_ULP_CLASS_HID_2934f] = 613,
-	[BNXT_ULP_CLASS_HID_2c2c7] = 614,
-	[BNXT_ULP_CLASS_HID_242e3] = 615,
-	[BNXT_ULP_CLASS_HID_27c6b] = 616,
-	[BNXT_ULP_CLASS_HID_2e02b] = 617,
-	[BNXT_ULP_CLASS_HID_2d3a3] = 618,
-	[BNXT_ULP_CLASS_HID_259a3] = 619,
-	[BNXT_ULP_CLASS_HID_213e7] = 620,
-	[BNXT_ULP_CLASS_HID_287a7] = 621,
-	[BNXT_ULP_CLASS_HID_2b137] = 622,
-	[BNXT_ULP_CLASS_HID_26e17] = 623,
-	[BNXT_ULP_CLASS_HID_26043] = 624,
-	[BNXT_ULP_CLASS_HID_2d403] = 625,
-	[BNXT_ULP_CLASS_HID_2c793] = 626,
-	[BNXT_ULP_CLASS_HID_20827] = 627,
-	[BNXT_ULP_CLASS_HID_23ba7] = 628,
-	[BNXT_ULP_CLASS_HID_2af67] = 629,
-	[BNXT_ULP_CLASS_HID_2dee7] = 630,
-	[BNXT_ULP_CLASS_HID_25e83] = 631,
-	[BNXT_ULP_CLASS_HID_24803] = 632,
-	[BNXT_ULP_CLASS_HID_2fdc3] = 633,
-	[BNXT_ULP_CLASS_HID_2ef43] = 634,
-	[BNXT_ULP_CLASS_HID_247bf] = 635,
-	[BNXT_ULP_CLASS_HID_219ff] = 636,
-	[BNXT_ULP_CLASS_HID_28dbf] = 637,
-	[BNXT_ULP_CLASS_HID_2bf07] = 638,
-	[BNXT_ULP_CLASS_HID_25467] = 639,
-	[BNXT_ULP_CLASS_HID_26e5f] = 640,
-	[BNXT_ULP_CLASS_HID_2d21f] = 641,
-	[BNXT_ULP_CLASS_HID_2cde7] = 642,
-	[BNXT_ULP_CLASS_HID_26f6f] = 643,
-	[BNXT_ULP_CLASS_HID_221af] = 644,
-	[BNXT_ULP_CLASS_HID_2956f] = 645,
-	[BNXT_ULP_CLASS_HID_2c4c7] = 646,
-	[BNXT_ULP_CLASS_HID_24487] = 647,
-	[BNXT_ULP_CLASS_HID_2760f] = 648,
-	[BNXT_ULP_CLASS_HID_2fbcf] = 649,
-	[BNXT_ULP_CLASS_HID_2d5a7] = 650,
-	[BNXT_ULP_CLASS_HID_25357] = 651,
-	[BNXT_ULP_CLASS_HID_21597] = 652,
-	[BNXT_ULP_CLASS_HID_29957] = 653,
-	[BNXT_ULP_CLASS_HID_2cb27] = 654,
-	[BNXT_ULP_CLASS_HID_248f7] = 655,
-	[BNXT_ULP_CLASS_HID_27a77] = 656,
-	[BNXT_ULP_CLASS_HID_2ee37] = 657,
-	[BNXT_ULP_CLASS_HID_2d987] = 658,
-	[BNXT_ULP_CLASS_HID_203c7] = 659,
-	[BNXT_ULP_CLASS_HID_23d47] = 660,
-	[BNXT_ULP_CLASS_HID_2a107] = 661,
-	[BNXT_ULP_CLASS_HID_2d0e7] = 662,
-	[BNXT_ULP_CLASS_HID_250a7] = 663,
-	[BNXT_ULP_CLASS_HID_24227] = 664,
-	[BNXT_ULP_CLASS_HID_2f7e7] = 665,
-	[BNXT_ULP_CLASS_HID_2c827] = 666,
-	[BNXT_ULP_CLASS_HID_25422] = 667,
-	[BNXT_ULP_CLASS_HID_21a66] = 668,
-	[BNXT_ULP_CLASS_HID_2f76a] = 669,
-	[BNXT_ULP_CLASS_HID_2bcae] = 670,
-	[BNXT_ULP_CLASS_HID_245ce] = 671,
-	[BNXT_ULP_CLASS_HID_24b02] = 672,
-	[BNXT_ULP_CLASS_HID_2dfc2] = 673,
-	[BNXT_ULP_CLASS_HID_2ee4a] = 674,
-	[BNXT_ULP_CLASS_HID_22cbe] = 675,
-	[BNXT_ULP_CLASS_HID_21232] = 676,
-	[BNXT_ULP_CLASS_HID_2cf26] = 677,
-	[BNXT_ULP_CLASS_HID_2b53a] = 678,
-	[BNXT_ULP_CLASS_HID_25d9a] = 679,
-	[BNXT_ULP_CLASS_HID_2439e] = 680,
-	[BNXT_ULP_CLASS_HID_2d79e] = 681,
-	[BNXT_ULP_CLASS_HID_2e606] = 682,
-	[BNXT_ULP_CLASS_HID_21c5e] = 683,
-	[BNXT_ULP_CLASS_HID_22ac6] = 684,
-	[BNXT_ULP_CLASS_HID_2be86] = 685,
-	[BNXT_ULP_CLASS_HID_2cd0e] = 686,
-	[BNXT_ULP_CLASS_HID_24d1a] = 687,
-	[BNXT_ULP_CLASS_HID_25b82] = 688,
-	[BNXT_ULP_CLASS_HID_2d042] = 689,
-	[BNXT_ULP_CLASS_HID_2d586] = 690,
-	[BNXT_ULP_CLASS_HID_2140a] = 691,
-	[BNXT_ULP_CLASS_HID_22292] = 692,
-	[BNXT_ULP_CLASS_HID_2b712] = 693,
-	[BNXT_ULP_CLASS_HID_2c59a] = 694,
-	[BNXT_ULP_CLASS_HID_24596] = 695,
-	[BNXT_ULP_CLASS_HID_2541e] = 696,
-	[BNXT_ULP_CLASS_HID_2e81e] = 697,
-	[BNXT_ULP_CLASS_HID_2f686] = 698,
-	[BNXT_ULP_CLASS_HID_24cf2] = 699,
-	[BNXT_ULP_CLASS_HID_23236] = 700,
-	[BNXT_ULP_CLASS_HID_286f6] = 701,
-	[BNXT_ULP_CLASS_HID_2d57e] = 702,
-	[BNXT_ULP_CLASS_HID_2555a] = 703,
-	[BNXT_ULP_CLASS_HID_263d2] = 704,
-	[BNXT_ULP_CLASS_HID_2f792] = 705,
-	[BNXT_ULP_CLASS_HID_2c61a] = 706,
-	[BNXT_ULP_CLASS_HID_244be] = 707,
-	[BNXT_ULP_CLASS_HID_20ab2] = 708,
-	[BNXT_ULP_CLASS_HID_29eb2] = 709,
-	[BNXT_ULP_CLASS_HID_2ad3a] = 710,
-	[BNXT_ULP_CLASS_HID_2761a] = 711,
-	[BNXT_ULP_CLASS_HID_27b9e] = 712,
-	[BNXT_ULP_CLASS_HID_2f01e] = 713,
-	[BNXT_ULP_CLASS_HID_2de96] = 714,
-	[BNXT_ULP_CLASS_HID_2341e] = 715,
-	[BNXT_ULP_CLASS_HID_24296] = 716,
-	[BNXT_ULP_CLASS_HID_2d756] = 717,
-	[BNXT_ULP_CLASS_HID_29c9a] = 718,
-	[BNXT_ULP_CLASS_HID_265da] = 719,
-	[BNXT_ULP_CLASS_HID_27452] = 720,
-	[BNXT_ULP_CLASS_HID_2c812] = 721,
-	[BNXT_ULP_CLASS_HID_2ce56] = 722,
-	[BNXT_ULP_CLASS_HID_20c9a] = 723,
-	[BNXT_ULP_CLASS_HID_25b12] = 724,
-	[BNXT_ULP_CLASS_HID_2af12] = 725,
-	[BNXT_ULP_CLASS_HID_29516] = 726,
-	[BNXT_ULP_CLASS_HID_27d96] = 727,
-	[BNXT_ULP_CLASS_HID_24c1e] = 728,
-	[BNXT_ULP_CLASS_HID_2c09e] = 729,
-	[BNXT_ULP_CLASS_HID_2c612] = 730,
-	[BNXT_ULP_CLASS_HID_24002] = 731,
-	[BNXT_ULP_CLASS_HID_20646] = 732,
-	[BNXT_ULP_CLASS_HID_29a06] = 733,
-	[BNXT_ULP_CLASS_HID_2a886] = 734,
-	[BNXT_ULP_CLASS_HID_271a6] = 735,
-	[BNXT_ULP_CLASS_HID_277e2] = 736,
-	[BNXT_ULP_CLASS_HID_2cba2] = 737,
-	[BNXT_ULP_CLASS_HID_2da22] = 738,
-	[BNXT_ULP_CLASS_HID_25896] = 739,
-	[BNXT_ULP_CLASS_HID_21e12] = 740,
-	[BNXT_ULP_CLASS_HID_29292] = 741,
-	[BNXT_ULP_CLASS_HID_2a112] = 742,
-	[BNXT_ULP_CLASS_HID_24a32] = 743,
-	[BNXT_ULP_CLASS_HID_24fb6] = 744,
-	[BNXT_ULP_CLASS_HID_2c436] = 745,
-	[BNXT_ULP_CLASS_HID_2d2a6] = 746,
-	[BNXT_ULP_CLASS_HID_20856] = 747,
-	[BNXT_ULP_CLASS_HID_256c6] = 748,
-	[BNXT_ULP_CLASS_HID_2aa86] = 749,
-	[BNXT_ULP_CLASS_HID_290d2] = 750,
-	[BNXT_ULP_CLASS_HID_279d2] = 751,
-	[BNXT_ULP_CLASS_HID_24842] = 752,
-	[BNXT_ULP_CLASS_HID_2dc02] = 753,
-	[BNXT_ULP_CLASS_HID_2c246] = 754,
-	[BNXT_ULP_CLASS_HID_20082] = 755,
-	[BNXT_ULP_CLASS_HID_22e92] = 756,
-	[BNXT_ULP_CLASS_HID_2a312] = 757,
-	[BNXT_ULP_CLASS_HID_2f192] = 758,
-	[BNXT_ULP_CLASS_HID_27196] = 759,
-	[BNXT_ULP_CLASS_HID_24016] = 760,
-	[BNXT_ULP_CLASS_HID_2d496] = 761,
-	[BNXT_ULP_CLASS_HID_2da12] = 762,
-	[BNXT_ULP_CLASS_HID_278d2] = 763,
-	[BNXT_ULP_CLASS_HID_23e16] = 764,
-	[BNXT_ULP_CLASS_HID_2b2d6] = 765,
-	[BNXT_ULP_CLASS_HID_2c156] = 766,
-	[BNXT_ULP_CLASS_HID_24132] = 767,
-	[BNXT_ULP_CLASS_HID_26fb2] = 768,
-	[BNXT_ULP_CLASS_HID_2e472] = 769,
-	[BNXT_ULP_CLASS_HID_2f2f2] = 770,
-	[BNXT_ULP_CLASS_HID_27096] = 771,
-	[BNXT_ULP_CLASS_HID_23692] = 772,
-	[BNXT_ULP_CLASS_HID_28a92] = 773,
-	[BNXT_ULP_CLASS_HID_2d912] = 774,
-	[BNXT_ULP_CLASS_HID_259b6] = 775,
-	[BNXT_ULP_CLASS_HID_26836] = 776,
-	[BNXT_ULP_CLASS_HID_2fc36] = 777,
-	[BNXT_ULP_CLASS_HID_2cab6] = 778,
-	[BNXT_ULP_CLASS_HID_22016] = 779,
-	[BNXT_ULP_CLASS_HID_24e96] = 780,
-	[BNXT_ULP_CLASS_HID_2c356] = 781,
-	[BNXT_ULP_CLASS_HID_28892] = 782,
-	[BNXT_ULP_CLASS_HID_25192] = 783,
-	[BNXT_ULP_CLASS_HID_257d6] = 784,
-	[BNXT_ULP_CLASS_HID_2f4d2] = 785,
-	[BNXT_ULP_CLASS_HID_2fa16] = 786,
-	[BNXT_ULP_CLASS_HID_23892] = 787,
-	[BNXT_ULP_CLASS_HID_24712] = 788,
-	[BNXT_ULP_CLASS_HID_2db12] = 789,
-	[BNXT_ULP_CLASS_HID_28116] = 790,
-	[BNXT_ULP_CLASS_HID_26a16] = 791,
-	[BNXT_ULP_CLASS_HID_27896] = 792,
-	[BNXT_ULP_CLASS_HID_2cc96] = 793,
-	[BNXT_ULP_CLASS_HID_2f292] = 794,
-	[BNXT_ULP_CLASS_HID_24b05] = 795,
-	[BNXT_ULP_CLASS_HID_20541] = 796,
-	[BNXT_ULP_CLASS_HID_2e84d] = 797,
-	[BNXT_ULP_CLASS_HID_2a389] = 798,
-	[BNXT_ULP_CLASS_HID_25ae9] = 799,
-	[BNXT_ULP_CLASS_HID_25425] = 800,
-	[BNXT_ULP_CLASS_HID_2c0e5] = 801,
-	[BNXT_ULP_CLASS_HID_2f16d] = 802,
-	[BNXT_ULP_CLASS_HID_253d5] = 803,
-	[BNXT_ULP_CLASS_HID_22d11] = 804,
-	[BNXT_ULP_CLASS_HID_299d1] = 805,
-	[BNXT_ULP_CLASS_HID_2ca59] = 806,
-	[BNXT_ULP_CLASS_HID_24a7d] = 807,
-	[BNXT_ULP_CLASS_HID_27cf5] = 808,
-	[BNXT_ULP_CLASS_HID_2e8b5] = 809,
-	[BNXT_ULP_CLASS_HID_2d93d] = 810,
-	[BNXT_ULP_CLASS_HID_25f25] = 811,
-	[BNXT_ULP_CLASS_HID_21961] = 812,
-	[BNXT_ULP_CLASS_HID_28521] = 813,
-	[BNXT_ULP_CLASS_HID_2b7a1] = 814,
-	[BNXT_ULP_CLASS_HID_26e81] = 815,
-	[BNXT_ULP_CLASS_HID_268c5] = 816,
-	[BNXT_ULP_CLASS_HID_2d485] = 817,
-	[BNXT_ULP_CLASS_HID_2c505] = 818,
-	[BNXT_ULP_CLASS_HID_267f5] = 819,
-	[BNXT_ULP_CLASS_HID_22131] = 820,
-	[BNXT_ULP_CLASS_HID_2adf1] = 821,
-	[BNXT_ULP_CLASS_HID_2de71] = 822,
-	[BNXT_ULP_CLASS_HID_25e15] = 823,
-	[BNXT_ULP_CLASS_HID_27095] = 824,
-	[BNXT_ULP_CLASS_HID_2fb55] = 825,
-	[BNXT_ULP_CLASS_HID_2edd5] = 826,
-	[BNXT_ULP_CLASS_HID_24511] = 827,
-	[BNXT_ULP_CLASS_HID_21f51] = 828,
-	[BNXT_ULP_CLASS_HID_28b11] = 829,
-	[BNXT_ULP_CLASS_HID_2bd99] = 830,
-	[BNXT_ULP_CLASS_HID_254f9] = 831,
-	[BNXT_ULP_CLASS_HID_26e31] = 832,
-	[BNXT_ULP_CLASS_HID_2daf1] = 833,
-	[BNXT_ULP_CLASS_HID_2cb79] = 834,
-	[BNXT_ULP_CLASS_HID_26dd1] = 835,
-	[BNXT_ULP_CLASS_HID_22711] = 836,
-	[BNXT_ULP_CLASS_HID_293d1] = 837,
-	[BNXT_ULP_CLASS_HID_2c459] = 838,
-	[BNXT_ULP_CLASS_HID_24419] = 839,
-	[BNXT_ULP_CLASS_HID_276f1] = 840,
-	[BNXT_ULP_CLASS_HID_2e2b1] = 841,
-	[BNXT_ULP_CLASS_HID_2d339] = 842,
-	[BNXT_ULP_CLASS_HID_25931] = 843,
-	[BNXT_ULP_CLASS_HID_21371] = 844,
-	[BNXT_ULP_CLASS_HID_29f31] = 845,
-	[BNXT_ULP_CLASS_HID_2b1b1] = 846,
-	[BNXT_ULP_CLASS_HID_26891] = 847,
-	[BNXT_ULP_CLASS_HID_262d1] = 848,
-	[BNXT_ULP_CLASS_HID_2ee91] = 849,
-	[BNXT_ULP_CLASS_HID_2df11] = 850,
-	[BNXT_ULP_CLASS_HID_20951] = 851,
-	[BNXT_ULP_CLASS_HID_23b31] = 852,
-	[BNXT_ULP_CLASS_HID_2a7f1] = 853,
-	[BNXT_ULP_CLASS_HID_2d871] = 854,
-	[BNXT_ULP_CLASS_HID_25831] = 855,
-	[BNXT_ULP_CLASS_HID_24a91] = 856,
-	[BNXT_ULP_CLASS_HID_2f551] = 857,
-	[BNXT_ULP_CLASS_HID_2e7d1] = 858,
-	[BNXT_ULP_CLASS_HID_2481f] = 859,
-	[BNXT_ULP_CLASS_HID_2025b] = 860,
-	[BNXT_ULP_CLASS_HID_28e1b] = 861,
-	[BNXT_ULP_CLASS_HID_2a083] = 862,
-	[BNXT_ULP_CLASS_HID_257e3] = 863,
-	[BNXT_ULP_CLASS_HID_2513f] = 864,
-	[BNXT_ULP_CLASS_HID_2ddff] = 865,
-	[BNXT_ULP_CLASS_HID_2ce67] = 866,
-	[BNXT_ULP_CLASS_HID_250df] = 867,
-	[BNXT_ULP_CLASS_HID_22a1b] = 868,
-	[BNXT_ULP_CLASS_HID_296db] = 869,
-	[BNXT_ULP_CLASS_HID_2c753] = 870,
-	[BNXT_ULP_CLASS_HID_24777] = 871,
-	[BNXT_ULP_CLASS_HID_279ff] = 872,
-	[BNXT_ULP_CLASS_HID_2e5bf] = 873,
-	[BNXT_ULP_CLASS_HID_2d637] = 874,
-	[BNXT_ULP_CLASS_HID_25c37] = 875,
-	[BNXT_ULP_CLASS_HID_21673] = 876,
-	[BNXT_ULP_CLASS_HID_28233] = 877,
-	[BNXT_ULP_CLASS_HID_2b4a3] = 878,
-	[BNXT_ULP_CLASS_HID_26b83] = 879,
-	[BNXT_ULP_CLASS_HID_265d7] = 880,
-	[BNXT_ULP_CLASS_HID_2d197] = 881,
-	[BNXT_ULP_CLASS_HID_2c207] = 882,
-	[BNXT_ULP_CLASS_HID_20db3] = 883,
-	[BNXT_ULP_CLASS_HID_23e33] = 884,
-	[BNXT_ULP_CLASS_HID_2aaf3] = 885,
-	[BNXT_ULP_CLASS_HID_2db73] = 886,
-	[BNXT_ULP_CLASS_HID_25b17] = 887,
-	[BNXT_ULP_CLASS_HID_24d97] = 888,
-	[BNXT_ULP_CLASS_HID_2f857] = 889,
-	[BNXT_ULP_CLASS_HID_2ead7] = 890,
-	[BNXT_ULP_CLASS_HID_2422b] = 891,
-	[BNXT_ULP_CLASS_HID_21c6b] = 892,
-	[BNXT_ULP_CLASS_HID_2882b] = 893,
-	[BNXT_ULP_CLASS_HID_2ba93] = 894,
-	[BNXT_ULP_CLASS_HID_251f3] = 895,
-	[BNXT_ULP_CLASS_HID_26bcb] = 896,
-	[BNXT_ULP_CLASS_HID_2d78b] = 897,
-	[BNXT_ULP_CLASS_HID_2c873] = 898,
-	[BNXT_ULP_CLASS_HID_26afb] = 899,
-	[BNXT_ULP_CLASS_HID_2243b] = 900,
-	[BNXT_ULP_CLASS_HID_290fb] = 901,
-	[BNXT_ULP_CLASS_HID_2c153] = 902,
-	[BNXT_ULP_CLASS_HID_24113] = 903,
-	[BNXT_ULP_CLASS_HID_2739b] = 904,
-	[BNXT_ULP_CLASS_HID_2fe5b] = 905,
-	[BNXT_ULP_CLASS_HID_2d033] = 906,
-	[BNXT_ULP_CLASS_HID_256c3] = 907,
-	[BNXT_ULP_CLASS_HID_21003] = 908,
-	[BNXT_ULP_CLASS_HID_29cc3] = 909,
-	[BNXT_ULP_CLASS_HID_2ceb3] = 910,
-	[BNXT_ULP_CLASS_HID_24d63] = 911,
-	[BNXT_ULP_CLASS_HID_27fe3] = 912,
-	[BNXT_ULP_CLASS_HID_2eba3] = 913,
-	[BNXT_ULP_CLASS_HID_2dc13] = 914,
-	[BNXT_ULP_CLASS_HID_20653] = 915,
-	[BNXT_ULP_CLASS_HID_238d3] = 916,
-	[BNXT_ULP_CLASS_HID_2a493] = 917,
-	[BNXT_ULP_CLASS_HID_2d573] = 918,
-	[BNXT_ULP_CLASS_HID_25533] = 919,
-	[BNXT_ULP_CLASS_HID_247b3] = 920,
-	[BNXT_ULP_CLASS_HID_2f273] = 921,
-	[BNXT_ULP_CLASS_HID_2cdb3] = 922,
-	[BNXT_ULP_CLASS_HID_25c7d] = 923,
-	[BNXT_ULP_CLASS_HID_21239] = 924,
-	[BNXT_ULP_CLASS_HID_2ff35] = 925,
-	[BNXT_ULP_CLASS_HID_2b4f1] = 926,
-	[BNXT_ULP_CLASS_HID_24d91] = 927,
-	[BNXT_ULP_CLASS_HID_2435d] = 928,
-	[BNXT_ULP_CLASS_HID_2d79d] = 929,
-	[BNXT_ULP_CLASS_HID_2e615] = 930,
-	[BNXT_ULP_CLASS_HID_244ad] = 931,
-	[BNXT_ULP_CLASS_HID_23a69] = 932,
-	[BNXT_ULP_CLASS_HID_28ea9] = 933,
-	[BNXT_ULP_CLASS_HID_2dd21] = 934,
-	[BNXT_ULP_CLASS_HID_25d05] = 935,
-	[BNXT_ULP_CLASS_HID_26b8d] = 936,
-	[BNXT_ULP_CLASS_HID_2ffcd] = 937,
-	[BNXT_ULP_CLASS_HID_2ce45] = 938,
-	[BNXT_ULP_CLASS_HID_2485d] = 939,
-	[BNXT_ULP_CLASS_HID_20e19] = 940,
-	[BNXT_ULP_CLASS_HID_29259] = 941,
-	[BNXT_ULP_CLASS_HID_2a0d9] = 942,
-	[BNXT_ULP_CLASS_HID_279f9] = 943,
-	[BNXT_ULP_CLASS_HID_27fbd] = 944,
-	[BNXT_ULP_CLASS_HID_2c3fd] = 945,
-	[BNXT_ULP_CLASS_HID_2d27d] = 946,
-	[BNXT_ULP_CLASS_HID_2708d] = 947,
-	[BNXT_ULP_CLASS_HID_23649] = 948,
-	[BNXT_ULP_CLASS_HID_2ba89] = 949,
-	[BNXT_ULP_CLASS_HID_2c909] = 950,
-	[BNXT_ULP_CLASS_HID_2496d] = 951,
-	[BNXT_ULP_CLASS_HID_267ed] = 952,
-	[BNXT_ULP_CLASS_HID_2ec2d] = 953,
-	[BNXT_ULP_CLASS_HID_2faad] = 954,
-	[BNXT_ULP_CLASS_HID_34c6] = 955,
-	[BNXT_ULP_CLASS_HID_0c22] = 956,
-	[BNXT_ULP_CLASS_HID_1cbe] = 957,
-	[BNXT_ULP_CLASS_HID_179a] = 958,
-	[BNXT_ULP_CLASS_HID_59be] = 959,
-	[BNXT_ULP_CLASS_HID_515a] = 960,
-	[BNXT_ULP_CLASS_HID_1c72] = 961,
-	[BNXT_ULP_CLASS_HID_171e] = 962,
-	[BNXT_ULP_CLASS_HID_19c8] = 963,
-	[BNXT_ULP_CLASS_HID_112c] = 964,
-	[BNXT_ULP_CLASS_HID_4d68] = 965,
-	[BNXT_ULP_CLASS_HID_444c] = 966,
-	[BNXT_ULP_CLASS_HID_0e8c] = 967,
-	[BNXT_ULP_CLASS_HID_09e0] = 968,
-	[BNXT_ULP_CLASS_HID_1af0] = 969,
-	[BNXT_ULP_CLASS_HID_15d4] = 970,
-	[BNXT_ULP_CLASS_HID_1dd0] = 971,
-	[BNXT_ULP_CLASS_HID_14f4] = 972,
-	[BNXT_ULP_CLASS_HID_70b0] = 973,
-	[BNXT_ULP_CLASS_HID_4854] = 974,
-	[BNXT_ULP_CLASS_HID_3dd4] = 975,
-	[BNXT_ULP_CLASS_HID_34f8] = 976,
-	[BNXT_ULP_CLASS_HID_09e8] = 977,
-	[BNXT_ULP_CLASS_HID_008c] = 978,
-	[BNXT_ULP_CLASS_HID_34e6] = 979,
-	[BNXT_ULP_CLASS_HID_0c02] = 980,
-	[BNXT_ULP_CLASS_HID_1c9e] = 981,
-	[BNXT_ULP_CLASS_HID_17ba] = 982,
-	[BNXT_ULP_CLASS_HID_429e] = 983,
-	[BNXT_ULP_CLASS_HID_5dba] = 984,
-	[BNXT_ULP_CLASS_HID_2a16] = 985,
-	[BNXT_ULP_CLASS_HID_2532] = 986,
-	[BNXT_ULP_CLASS_HID_2da2] = 987,
-	[BNXT_ULP_CLASS_HID_24fe] = 988,
-	[BNXT_ULP_CLASS_HID_355a] = 989,
-	[BNXT_ULP_CLASS_HID_0c76] = 990,
-	[BNXT_ULP_CLASS_HID_13e6] = 991,
-	[BNXT_ULP_CLASS_HID_7276] = 992,
-	[BNXT_ULP_CLASS_HID_42d2] = 993,
-	[BNXT_ULP_CLASS_HID_5dee] = 994,
-	[BNXT_ULP_CLASS_HID_59de] = 995,
-	[BNXT_ULP_CLASS_HID_513a] = 996,
-	[BNXT_ULP_CLASS_HID_1c12] = 997,
-	[BNXT_ULP_CLASS_HID_177e] = 998,
-	[BNXT_ULP_CLASS_HID_0e92] = 999,
-	[BNXT_ULP_CLASS_HID_09fe] = 1000,
-	[BNXT_ULP_CLASS_HID_5c1a] = 1001,
-	[BNXT_ULP_CLASS_HID_5746] = 1002,
-	[BNXT_ULP_CLASS_HID_79da] = 1003,
-	[BNXT_ULP_CLASS_HID_7106] = 1004,
-	[BNXT_ULP_CLASS_HID_3c1e] = 1005,
-	[BNXT_ULP_CLASS_HID_377a] = 1006,
-	[BNXT_ULP_CLASS_HID_2e9e] = 1007,
-	[BNXT_ULP_CLASS_HID_29fa] = 1008,
-	[BNXT_ULP_CLASS_HID_14d2] = 1009,
-	[BNXT_ULP_CLASS_HID_7742] = 1010,
-	[BNXT_ULP_CLASS_HID_3706] = 1011,
-	[BNXT_ULP_CLASS_HID_0fe2] = 1012,
-	[BNXT_ULP_CLASS_HID_1f7e] = 1013,
-	[BNXT_ULP_CLASS_HID_145a] = 1014,
-	[BNXT_ULP_CLASS_HID_417e] = 1015,
-	[BNXT_ULP_CLASS_HID_5e5a] = 1016,
-	[BNXT_ULP_CLASS_HID_29f6] = 1017,
-	[BNXT_ULP_CLASS_HID_26d2] = 1018,
-	[BNXT_ULP_CLASS_HID_2e42] = 1019,
-	[BNXT_ULP_CLASS_HID_271e] = 1020,
-	[BNXT_ULP_CLASS_HID_36ba] = 1021,
-	[BNXT_ULP_CLASS_HID_0f96] = 1022,
-	[BNXT_ULP_CLASS_HID_1006] = 1023,
-	[BNXT_ULP_CLASS_HID_7196] = 1024,
-	[BNXT_ULP_CLASS_HID_4132] = 1025,
-	[BNXT_ULP_CLASS_HID_5e0e] = 1026,
-	[BNXT_ULP_CLASS_HID_59fe] = 1027,
-	[BNXT_ULP_CLASS_HID_511a] = 1028,
-	[BNXT_ULP_CLASS_HID_1c32] = 1029,
-	[BNXT_ULP_CLASS_HID_175e] = 1030,
-	[BNXT_ULP_CLASS_HID_0eb2] = 1031,
-	[BNXT_ULP_CLASS_HID_09de] = 1032,
-	[BNXT_ULP_CLASS_HID_5c3a] = 1033,
-	[BNXT_ULP_CLASS_HID_5766] = 1034,
-	[BNXT_ULP_CLASS_HID_79fa] = 1035,
-	[BNXT_ULP_CLASS_HID_7126] = 1036,
-	[BNXT_ULP_CLASS_HID_3c3e] = 1037,
-	[BNXT_ULP_CLASS_HID_375a] = 1038,
-	[BNXT_ULP_CLASS_HID_2ebe] = 1039,
-	[BNXT_ULP_CLASS_HID_29da] = 1040,
-	[BNXT_ULP_CLASS_HID_14f2] = 1041,
-	[BNXT_ULP_CLASS_HID_7762] = 1042,
-	[BNXT_ULP_CLASS_HID_19e8] = 1043,
-	[BNXT_ULP_CLASS_HID_110c] = 1044,
-	[BNXT_ULP_CLASS_HID_4d48] = 1045,
-	[BNXT_ULP_CLASS_HID_446c] = 1046,
-	[BNXT_ULP_CLASS_HID_0eac] = 1047,
-	[BNXT_ULP_CLASS_HID_09c0] = 1048,
-	[BNXT_ULP_CLASS_HID_1ad0] = 1049,
-	[BNXT_ULP_CLASS_HID_15f4] = 1050,
-	[BNXT_ULP_CLASS_HID_39ec] = 1051,
-	[BNXT_ULP_CLASS_HID_3100] = 1052,
-	[BNXT_ULP_CLASS_HID_0210] = 1053,
-	[BNXT_ULP_CLASS_HID_1d34] = 1054,
-	[BNXT_ULP_CLASS_HID_2ea0] = 1055,
-	[BNXT_ULP_CLASS_HID_29c4] = 1056,
-	[BNXT_ULP_CLASS_HID_3ad4] = 1057,
-	[BNXT_ULP_CLASS_HID_35e8] = 1058,
-	[BNXT_ULP_CLASS_HID_5d80] = 1059,
-	[BNXT_ULP_CLASS_HID_54a4] = 1060,
-	[BNXT_ULP_CLASS_HID_29b4] = 1061,
-	[BNXT_ULP_CLASS_HID_20c8] = 1062,
-	[BNXT_ULP_CLASS_HID_7244] = 1063,
-	[BNXT_ULP_CLASS_HID_4d98] = 1064,
-	[BNXT_ULP_CLASS_HID_5e68] = 1065,
-	[BNXT_ULP_CLASS_HID_598c] = 1066,
-	[BNXT_ULP_CLASS_HID_1248] = 1067,
-	[BNXT_ULP_CLASS_HID_74d8] = 1068,
-	[BNXT_ULP_CLASS_HID_49a8] = 1069,
-	[BNXT_ULP_CLASS_HID_40cc] = 1070,
-	[BNXT_ULP_CLASS_HID_0b0c] = 1071,
-	[BNXT_ULP_CLASS_HID_0220] = 1072,
-	[BNXT_ULP_CLASS_HID_1730] = 1073,
-	[BNXT_ULP_CLASS_HID_7980] = 1074,
-	[BNXT_ULP_CLASS_HID_1db0] = 1075,
-	[BNXT_ULP_CLASS_HID_1494] = 1076,
-	[BNXT_ULP_CLASS_HID_70d0] = 1077,
-	[BNXT_ULP_CLASS_HID_4834] = 1078,
-	[BNXT_ULP_CLASS_HID_3db4] = 1079,
-	[BNXT_ULP_CLASS_HID_3498] = 1080,
-	[BNXT_ULP_CLASS_HID_0988] = 1081,
-	[BNXT_ULP_CLASS_HID_00ec] = 1082,
-	[BNXT_ULP_CLASS_HID_23f44] = 1083,
-	[BNXT_ULP_CLASS_HID_236a8] = 1084,
-	[BNXT_ULP_CLASS_HID_20b58] = 1085,
-	[BNXT_ULP_CLASS_HID_202bc] = 1086,
-	[BNXT_ULP_CLASS_HID_25f48] = 1087,
-	[BNXT_ULP_CLASS_HID_256ac] = 1088,
-	[BNXT_ULP_CLASS_HID_22b5c] = 1089,
-	[BNXT_ULP_CLASS_HID_22280] = 1090,
-	[BNXT_ULP_CLASS_HID_14000] = 1091,
-	[BNXT_ULP_CLASS_HID_15b64] = 1092,
-	[BNXT_ULP_CLASS_HID_12c14] = 1093,
-	[BNXT_ULP_CLASS_HID_12778] = 1094,
-	[BNXT_ULP_CLASS_HID_118f8] = 1095,
-	[BNXT_ULP_CLASS_HID_113dc] = 1096,
-	[BNXT_ULP_CLASS_HID_14c18] = 1097,
-	[BNXT_ULP_CLASS_HID_1477c] = 1098,
-	[BNXT_ULP_CLASS_HID_31a88] = 1099,
-	[BNXT_ULP_CLASS_HID_315ec] = 1100,
-	[BNXT_ULP_CLASS_HID_34e28] = 1101,
-	[BNXT_ULP_CLASS_HID_3490c] = 1102,
-	[BNXT_ULP_CLASS_HID_33a8c] = 1103,
-	[BNXT_ULP_CLASS_HID_335f0] = 1104,
-	[BNXT_ULP_CLASS_HID_306e0] = 1105,
-	[BNXT_ULP_CLASS_HID_301c4] = 1106,
-	[BNXT_ULP_CLASS_HID_1a08] = 1107,
-	[BNXT_ULP_CLASS_HID_12ec] = 1108,
-	[BNXT_ULP_CLASS_HID_4ea8] = 1109,
-	[BNXT_ULP_CLASS_HID_478c] = 1110,
-	[BNXT_ULP_CLASS_HID_0d4c] = 1111,
-	[BNXT_ULP_CLASS_HID_0a20] = 1112,
-	[BNXT_ULP_CLASS_HID_1930] = 1113,
-	[BNXT_ULP_CLASS_HID_1614] = 1114,
-	[BNXT_ULP_CLASS_HID_3a0c] = 1115,
-	[BNXT_ULP_CLASS_HID_32e0] = 1116,
-	[BNXT_ULP_CLASS_HID_01f0] = 1117,
-	[BNXT_ULP_CLASS_HID_1ed4] = 1118,
-	[BNXT_ULP_CLASS_HID_2d40] = 1119,
-	[BNXT_ULP_CLASS_HID_2a24] = 1120,
-	[BNXT_ULP_CLASS_HID_3934] = 1121,
-	[BNXT_ULP_CLASS_HID_3608] = 1122,
-	[BNXT_ULP_CLASS_HID_5e60] = 1123,
-	[BNXT_ULP_CLASS_HID_5744] = 1124,
-	[BNXT_ULP_CLASS_HID_2a54] = 1125,
-	[BNXT_ULP_CLASS_HID_2328] = 1126,
-	[BNXT_ULP_CLASS_HID_71a4] = 1127,
-	[BNXT_ULP_CLASS_HID_4e78] = 1128,
-	[BNXT_ULP_CLASS_HID_5d88] = 1129,
-	[BNXT_ULP_CLASS_HID_5a6c] = 1130,
-	[BNXT_ULP_CLASS_HID_11a8] = 1131,
-	[BNXT_ULP_CLASS_HID_7738] = 1132,
-	[BNXT_ULP_CLASS_HID_4a48] = 1133,
-	[BNXT_ULP_CLASS_HID_432c] = 1134,
-	[BNXT_ULP_CLASS_HID_08ec] = 1135,
-	[BNXT_ULP_CLASS_HID_01c0] = 1136,
-	[BNXT_ULP_CLASS_HID_14d0] = 1137,
-	[BNXT_ULP_CLASS_HID_7a60] = 1138,
-	[BNXT_ULP_CLASS_HID_1d90] = 1139,
-	[BNXT_ULP_CLASS_HID_14b4] = 1140,
-	[BNXT_ULP_CLASS_HID_70f0] = 1141,
-	[BNXT_ULP_CLASS_HID_4814] = 1142,
-	[BNXT_ULP_CLASS_HID_3d94] = 1143,
-	[BNXT_ULP_CLASS_HID_34b8] = 1144,
-	[BNXT_ULP_CLASS_HID_09a8] = 1145,
-	[BNXT_ULP_CLASS_HID_00cc] = 1146,
-	[BNXT_ULP_CLASS_HID_23f64] = 1147,
-	[BNXT_ULP_CLASS_HID_23688] = 1148,
-	[BNXT_ULP_CLASS_HID_20b78] = 1149,
-	[BNXT_ULP_CLASS_HID_2029c] = 1150,
-	[BNXT_ULP_CLASS_HID_25f68] = 1151,
-	[BNXT_ULP_CLASS_HID_2568c] = 1152,
-	[BNXT_ULP_CLASS_HID_22b7c] = 1153,
-	[BNXT_ULP_CLASS_HID_222a0] = 1154,
-	[BNXT_ULP_CLASS_HID_14020] = 1155,
-	[BNXT_ULP_CLASS_HID_15b44] = 1156,
-	[BNXT_ULP_CLASS_HID_12c34] = 1157,
-	[BNXT_ULP_CLASS_HID_12758] = 1158,
-	[BNXT_ULP_CLASS_HID_118d8] = 1159,
-	[BNXT_ULP_CLASS_HID_113fc] = 1160,
-	[BNXT_ULP_CLASS_HID_14c38] = 1161,
-	[BNXT_ULP_CLASS_HID_1475c] = 1162,
-	[BNXT_ULP_CLASS_HID_31aa8] = 1163,
-	[BNXT_ULP_CLASS_HID_315cc] = 1164,
-	[BNXT_ULP_CLASS_HID_34e08] = 1165,
-	[BNXT_ULP_CLASS_HID_3492c] = 1166,
-	[BNXT_ULP_CLASS_HID_33aac] = 1167,
-	[BNXT_ULP_CLASS_HID_335d0] = 1168,
-	[BNXT_ULP_CLASS_HID_306c0] = 1169,
-	[BNXT_ULP_CLASS_HID_301e4] = 1170,
-	[BNXT_ULP_CLASS_HID_4d32] = 1171,
-	[BNXT_ULP_CLASS_HID_54aa] = 1172,
-	[BNXT_ULP_CLASS_HID_0686] = 1173,
-	[BNXT_ULP_CLASS_HID_540e] = 1174,
-	[BNXT_ULP_CLASS_HID_2e3c] = 1175,
-	[BNXT_ULP_CLASS_HID_3a20] = 1176,
-	[BNXT_ULP_CLASS_HID_46f0] = 1177,
-	[BNXT_ULP_CLASS_HID_52e4] = 1178,
-	[BNXT_ULP_CLASS_HID_55e4] = 1179,
-	[BNXT_ULP_CLASS_HID_21f8] = 1180,
-	[BNXT_ULP_CLASS_HID_75e8] = 1181,
-	[BNXT_ULP_CLASS_HID_41fc] = 1182,
-	[BNXT_ULP_CLASS_HID_4d12] = 1183,
-	[BNXT_ULP_CLASS_HID_548a] = 1184,
-	[BNXT_ULP_CLASS_HID_3356] = 1185,
-	[BNXT_ULP_CLASS_HID_1ace] = 1186,
-	[BNXT_ULP_CLASS_HID_1a9a] = 1187,
-	[BNXT_ULP_CLASS_HID_4d46] = 1188,
-	[BNXT_ULP_CLASS_HID_2812] = 1189,
-	[BNXT_ULP_CLASS_HID_338a] = 1190,
-	[BNXT_ULP_CLASS_HID_06e6] = 1191,
-	[BNXT_ULP_CLASS_HID_546e] = 1192,
-	[BNXT_ULP_CLASS_HID_46ee] = 1193,
-	[BNXT_ULP_CLASS_HID_0d22] = 1194,
-	[BNXT_ULP_CLASS_HID_26e2] = 1195,
-	[BNXT_ULP_CLASS_HID_746a] = 1196,
-	[BNXT_ULP_CLASS_HID_1fa6] = 1197,
-	[BNXT_ULP_CLASS_HID_2d2e] = 1198,
-	[BNXT_ULP_CLASS_HID_4ef2] = 1199,
-	[BNXT_ULP_CLASS_HID_576a] = 1200,
-	[BNXT_ULP_CLASS_HID_30b6] = 1201,
-	[BNXT_ULP_CLASS_HID_192e] = 1202,
-	[BNXT_ULP_CLASS_HID_197a] = 1203,
-	[BNXT_ULP_CLASS_HID_4ea6] = 1204,
-	[BNXT_ULP_CLASS_HID_2bf2] = 1205,
-	[BNXT_ULP_CLASS_HID_306a] = 1206,
-	[BNXT_ULP_CLASS_HID_06c6] = 1207,
-	[BNXT_ULP_CLASS_HID_544e] = 1208,
-	[BNXT_ULP_CLASS_HID_46ce] = 1209,
-	[BNXT_ULP_CLASS_HID_0d02] = 1210,
-	[BNXT_ULP_CLASS_HID_26c2] = 1211,
-	[BNXT_ULP_CLASS_HID_744a] = 1212,
-	[BNXT_ULP_CLASS_HID_1f86] = 1213,
-	[BNXT_ULP_CLASS_HID_2d0e] = 1214,
-	[BNXT_ULP_CLASS_HID_2e1c] = 1215,
-	[BNXT_ULP_CLASS_HID_3a00] = 1216,
-	[BNXT_ULP_CLASS_HID_46d0] = 1217,
-	[BNXT_ULP_CLASS_HID_52c4] = 1218,
-	[BNXT_ULP_CLASS_HID_4e10] = 1219,
-	[BNXT_ULP_CLASS_HID_5a04] = 1220,
-	[BNXT_ULP_CLASS_HID_1f98] = 1221,
-	[BNXT_ULP_CLASS_HID_72f8] = 1222,
-	[BNXT_ULP_CLASS_HID_0a78] = 1223,
-	[BNXT_ULP_CLASS_HID_166c] = 1224,
-	[BNXT_ULP_CLASS_HID_233c] = 1225,
-	[BNXT_ULP_CLASS_HID_0f20] = 1226,
-	[BNXT_ULP_CLASS_HID_2a7c] = 1227,
-	[BNXT_ULP_CLASS_HID_3660] = 1228,
-	[BNXT_ULP_CLASS_HID_4330] = 1229,
-	[BNXT_ULP_CLASS_HID_2f24] = 1230,
-	[BNXT_ULP_CLASS_HID_5584] = 1231,
-	[BNXT_ULP_CLASS_HID_2198] = 1232,
-	[BNXT_ULP_CLASS_HID_7588] = 1233,
-	[BNXT_ULP_CLASS_HID_419c] = 1234,
-	[BNXT_ULP_CLASS_HID_27758] = 1235,
-	[BNXT_ULP_CLASS_HID_243ac] = 1236,
-	[BNXT_ULP_CLASS_HID_20c10] = 1237,
-	[BNXT_ULP_CLASS_HID_21864] = 1238,
-	[BNXT_ULP_CLASS_HID_130c8] = 1239,
-	[BNXT_ULP_CLASS_HID_11cdc] = 1240,
-	[BNXT_ULP_CLASS_HID_150cc] = 1241,
-	[BNXT_ULP_CLASS_HID_13d20] = 1242,
-	[BNXT_ULP_CLASS_HID_3529c] = 1243,
-	[BNXT_ULP_CLASS_HID_33ef0] = 1244,
-	[BNXT_ULP_CLASS_HID_372e0] = 1245,
-	[BNXT_ULP_CLASS_HID_35ef4] = 1246,
-	[BNXT_ULP_CLASS_HID_2dfc] = 1247,
-	[BNXT_ULP_CLASS_HID_39e0] = 1248,
-	[BNXT_ULP_CLASS_HID_4530] = 1249,
-	[BNXT_ULP_CLASS_HID_5124] = 1250,
-	[BNXT_ULP_CLASS_HID_4df0] = 1251,
-	[BNXT_ULP_CLASS_HID_59e4] = 1252,
-	[BNXT_ULP_CLASS_HID_1c78] = 1253,
-	[BNXT_ULP_CLASS_HID_7118] = 1254,
-	[BNXT_ULP_CLASS_HID_0998] = 1255,
-	[BNXT_ULP_CLASS_HID_158c] = 1256,
-	[BNXT_ULP_CLASS_HID_20dc] = 1257,
-	[BNXT_ULP_CLASS_HID_0cc0] = 1258,
-	[BNXT_ULP_CLASS_HID_299c] = 1259,
-	[BNXT_ULP_CLASS_HID_3580] = 1260,
-	[BNXT_ULP_CLASS_HID_40d0] = 1261,
-	[BNXT_ULP_CLASS_HID_2cc4] = 1262,
-	[BNXT_ULP_CLASS_HID_55a4] = 1263,
-	[BNXT_ULP_CLASS_HID_21b8] = 1264,
-	[BNXT_ULP_CLASS_HID_75a8] = 1265,
-	[BNXT_ULP_CLASS_HID_41bc] = 1266,
-	[BNXT_ULP_CLASS_HID_27778] = 1267,
-	[BNXT_ULP_CLASS_HID_2438c] = 1268,
-	[BNXT_ULP_CLASS_HID_20c30] = 1269,
-	[BNXT_ULP_CLASS_HID_21844] = 1270,
-	[BNXT_ULP_CLASS_HID_130e8] = 1271,
-	[BNXT_ULP_CLASS_HID_11cfc] = 1272,
-	[BNXT_ULP_CLASS_HID_150ec] = 1273,
-	[BNXT_ULP_CLASS_HID_13d00] = 1274,
-	[BNXT_ULP_CLASS_HID_352bc] = 1275,
-	[BNXT_ULP_CLASS_HID_33ed0] = 1276,
-	[BNXT_ULP_CLASS_HID_372c0] = 1277,
-	[BNXT_ULP_CLASS_HID_35ed4] = 1278,
-	[BNXT_ULP_CLASS_HID_3866] = 1279,
-	[BNXT_ULP_CLASS_HID_381e] = 1280,
-	[BNXT_ULP_CLASS_HID_3860] = 1281,
-	[BNXT_ULP_CLASS_HID_0454] = 1282,
-	[BNXT_ULP_CLASS_HID_3818] = 1283,
-	[BNXT_ULP_CLASS_HID_042c] = 1284,
-	[BNXT_ULP_CLASS_HID_3846] = 1285,
-	[BNXT_ULP_CLASS_HID_387e] = 1286,
-	[BNXT_ULP_CLASS_HID_3ba6] = 1287,
-	[BNXT_ULP_CLASS_HID_385e] = 1288,
-	[BNXT_ULP_CLASS_HID_3840] = 1289,
-	[BNXT_ULP_CLASS_HID_0474] = 1290,
-	[BNXT_ULP_CLASS_HID_3878] = 1291,
-	[BNXT_ULP_CLASS_HID_044c] = 1292,
-	[BNXT_ULP_CLASS_HID_3ba0] = 1293,
-	[BNXT_ULP_CLASS_HID_0794] = 1294,
-	[BNXT_ULP_CLASS_HID_3858] = 1295,
-	[BNXT_ULP_CLASS_HID_046c] = 1296
+	[BNXT_ULP_CLASS_HID_00b8] = 1,
+	[BNXT_ULP_CLASS_HID_0cc2] = 2,
+	[BNXT_ULP_CLASS_HID_10e4] = 3,
+	[BNXT_ULP_CLASS_HID_1d0e] = 4,
+	[BNXT_ULP_CLASS_HID_0286] = 5,
+	[BNXT_ULP_CLASS_HID_0e98] = 6,
+	[BNXT_ULP_CLASS_HID_1666] = 7,
+	[BNXT_ULP_CLASS_HID_02de] = 8,
+	[BNXT_ULP_CLASS_HID_81d25] = 9,
+	[BNXT_ULP_CLASS_HID_809ad] = 10,
+	[BNXT_ULP_CLASS_HID_80ae3] = 11,
+	[BNXT_ULP_CLASS_HID_8170d] = 12,
+	[BNXT_ULP_CLASS_HID_80773] = 13,
+	[BNXT_ULP_CLASS_HID_8139d] = 14,
+	[BNXT_ULP_CLASS_HID_814d3] = 15,
+	[BNXT_ULP_CLASS_HID_8015b] = 16,
+	[BNXT_ULP_CLASS_HID_21977] = 17,
+	[BNXT_ULP_CLASS_HID_205ef] = 18,
+	[BNXT_ULP_CLASS_HID_20735] = 19,
+	[BNXT_ULP_CLASS_HID_2134f] = 20,
+	[BNXT_ULP_CLASS_HID_61beb] = 21,
+	[BNXT_ULP_CLASS_HID_60863] = 22,
+	[BNXT_ULP_CLASS_HID_609a9] = 23,
+	[BNXT_ULP_CLASS_HID_615c3] = 24,
+	[BNXT_ULP_CLASS_HID_00a8] = 25,
+	[BNXT_ULP_CLASS_HID_0cd2] = 26,
+	[BNXT_ULP_CLASS_HID_10f4] = 27,
+	[BNXT_ULP_CLASS_HID_1d1e] = 28,
+	[BNXT_ULP_CLASS_HID_1488] = 29,
+	[BNXT_ULP_CLASS_HID_0110] = 30,
+	[BNXT_ULP_CLASS_HID_0532] = 31,
+	[BNXT_ULP_CLASS_HID_115c] = 32,
+	[BNXT_ULP_CLASS_HID_0ab8] = 33,
+	[BNXT_ULP_CLASS_HID_16a2] = 34,
+	[BNXT_ULP_CLASS_HID_1ac4] = 35,
+	[BNXT_ULP_CLASS_HID_074c] = 36,
+	[BNXT_ULP_CLASS_HID_1e98] = 37,
+	[BNXT_ULP_CLASS_HID_0ae0] = 38,
+	[BNXT_ULP_CLASS_HID_0f02] = 39,
+	[BNXT_ULP_CLASS_HID_1b2c] = 40,
+	[BNXT_ULP_CLASS_HID_0296] = 41,
+	[BNXT_ULP_CLASS_HID_0e88] = 42,
+	[BNXT_ULP_CLASS_HID_1676] = 43,
+	[BNXT_ULP_CLASS_HID_02ce] = 44,
+	[BNXT_ULP_CLASS_HID_8076e] = 45,
+	[BNXT_ULP_CLASS_HID_81380] = 46,
+	[BNXT_ULP_CLASS_HID_81b4e] = 47,
+	[BNXT_ULP_CLASS_HID_807c6] = 48,
+	[BNXT_ULP_CLASS_HID_404ea] = 49,
+	[BNXT_ULP_CLASS_HID_4110c] = 50,
+	[BNXT_ULP_CLASS_HID_418ca] = 51,
+	[BNXT_ULP_CLASS_HID_40542] = 52,
+	[BNXT_ULP_CLASS_HID_c09e2] = 53,
+	[BNXT_ULP_CLASS_HID_c1604] = 54,
+	[BNXT_ULP_CLASS_HID_c1dc2] = 55,
+	[BNXT_ULP_CLASS_HID_c0a5a] = 56,
+	[BNXT_ULP_CLASS_HID_0098] = 57,
+	[BNXT_ULP_CLASS_HID_0ce2] = 58,
+	[BNXT_ULP_CLASS_HID_10c4] = 59,
+	[BNXT_ULP_CLASS_HID_1d2e] = 60,
+	[BNXT_ULP_CLASS_HID_14b8] = 61,
+	[BNXT_ULP_CLASS_HID_0120] = 62,
+	[BNXT_ULP_CLASS_HID_0502] = 63,
+	[BNXT_ULP_CLASS_HID_116c] = 64,
+	[BNXT_ULP_CLASS_HID_0a88] = 65,
+	[BNXT_ULP_CLASS_HID_1692] = 66,
+	[BNXT_ULP_CLASS_HID_1af4] = 67,
+	[BNXT_ULP_CLASS_HID_077c] = 68,
+	[BNXT_ULP_CLASS_HID_1ea8] = 69,
+	[BNXT_ULP_CLASS_HID_0ad0] = 70,
+	[BNXT_ULP_CLASS_HID_0f32] = 71,
+	[BNXT_ULP_CLASS_HID_1b1c] = 72,
+	[BNXT_ULP_CLASS_HID_02a6] = 73,
+	[BNXT_ULP_CLASS_HID_0eb8] = 74,
+	[BNXT_ULP_CLASS_HID_1646] = 75,
+	[BNXT_ULP_CLASS_HID_02fe] = 76,
+	[BNXT_ULP_CLASS_HID_8075e] = 77,
+	[BNXT_ULP_CLASS_HID_813b0] = 78,
+	[BNXT_ULP_CLASS_HID_81b7e] = 79,
+	[BNXT_ULP_CLASS_HID_807f6] = 80,
+	[BNXT_ULP_CLASS_HID_404da] = 81,
+	[BNXT_ULP_CLASS_HID_4113c] = 82,
+	[BNXT_ULP_CLASS_HID_418fa] = 83,
+	[BNXT_ULP_CLASS_HID_40572] = 84,
+	[BNXT_ULP_CLASS_HID_c09d2] = 85,
+	[BNXT_ULP_CLASS_HID_c1634] = 86,
+	[BNXT_ULP_CLASS_HID_c1df2] = 87,
+	[BNXT_ULP_CLASS_HID_c0a6a] = 88,
+	[BNXT_ULP_CLASS_HID_81d35] = 89,
+	[BNXT_ULP_CLASS_HID_809bd] = 90,
+	[BNXT_ULP_CLASS_HID_80af3] = 91,
+	[BNXT_ULP_CLASS_HID_8171d] = 92,
+	[BNXT_ULP_CLASS_HID_80763] = 93,
+	[BNXT_ULP_CLASS_HID_8138d] = 94,
+	[BNXT_ULP_CLASS_HID_814c3] = 95,
+	[BNXT_ULP_CLASS_HID_8014b] = 96,
+	[BNXT_ULP_CLASS_HID_c001f] = 97,
+	[BNXT_ULP_CLASS_HID_c0c39] = 98,
+	[BNXT_ULP_CLASS_HID_c0d7f] = 99,
+	[BNXT_ULP_CLASS_HID_c1999] = 100,
+	[BNXT_ULP_CLASS_HID_c09ef] = 101,
+	[BNXT_ULP_CLASS_HID_c1609] = 102,
+	[BNXT_ULP_CLASS_HID_c174f] = 103,
+	[BNXT_ULP_CLASS_HID_c03d7] = 104,
+	[BNXT_ULP_CLASS_HID_a1e73] = 105,
+	[BNXT_ULP_CLASS_HID_a0afb] = 106,
+	[BNXT_ULP_CLASS_HID_a0c31] = 107,
+	[BNXT_ULP_CLASS_HID_a185b] = 108,
+	[BNXT_ULP_CLASS_HID_a08a1] = 109,
+	[BNXT_ULP_CLASS_HID_a14cb] = 110,
+	[BNXT_ULP_CLASS_HID_a1601] = 111,
+	[BNXT_ULP_CLASS_HID_a0289] = 112,
+	[BNXT_ULP_CLASS_HID_e015d] = 113,
+	[BNXT_ULP_CLASS_HID_e0d47] = 114,
+	[BNXT_ULP_CLASS_HID_e0ebd] = 115,
+	[BNXT_ULP_CLASS_HID_e1aa7] = 116,
+	[BNXT_ULP_CLASS_HID_e0b2d] = 117,
+	[BNXT_ULP_CLASS_HID_e1757] = 118,
+	[BNXT_ULP_CLASS_HID_e188d] = 119,
+	[BNXT_ULP_CLASS_HID_e0515] = 120,
+	[BNXT_ULP_CLASS_HID_21967] = 121,
+	[BNXT_ULP_CLASS_HID_205ff] = 122,
+	[BNXT_ULP_CLASS_HID_20725] = 123,
+	[BNXT_ULP_CLASS_HID_2135f] = 124,
+	[BNXT_ULP_CLASS_HID_61bfb] = 125,
+	[BNXT_ULP_CLASS_HID_60873] = 126,
+	[BNXT_ULP_CLASS_HID_609b9] = 127,
+	[BNXT_ULP_CLASS_HID_615d3] = 128,
+	[BNXT_ULP_CLASS_HID_30a55] = 129,
+	[BNXT_ULP_CLASS_HID_3164f] = 130,
+	[BNXT_ULP_CLASS_HID_317b5] = 131,
+	[BNXT_ULP_CLASS_HID_3040d] = 132,
+	[BNXT_ULP_CLASS_HID_70ca9] = 133,
+	[BNXT_ULP_CLASS_HID_718c3] = 134,
+	[BNXT_ULP_CLASS_HID_71a09] = 135,
+	[BNXT_ULP_CLASS_HID_70681] = 136,
+	[BNXT_ULP_CLASS_HID_2821d] = 137,
+	[BNXT_ULP_CLASS_HID_28e37] = 138,
+	[BNXT_ULP_CLASS_HID_28f7d] = 139,
+	[BNXT_ULP_CLASS_HID_29b97] = 140,
+	[BNXT_ULP_CLASS_HID_68491] = 141,
+	[BNXT_ULP_CLASS_HID_6908b] = 142,
+	[BNXT_ULP_CLASS_HID_691f1] = 143,
+	[BNXT_ULP_CLASS_HID_69deb] = 144,
+	[BNXT_ULP_CLASS_HID_3926d] = 145,
+	[BNXT_ULP_CLASS_HID_39e87] = 146,
+	[BNXT_ULP_CLASS_HID_38023] = 147,
+	[BNXT_ULP_CLASS_HID_38c45] = 148,
+	[BNXT_ULP_CLASS_HID_794e1] = 149,
+	[BNXT_ULP_CLASS_HID_78179] = 150,
+	[BNXT_ULP_CLASS_HID_782a7] = 151,
+	[BNXT_ULP_CLASS_HID_78ed9] = 152,
+	[BNXT_ULP_CLASS_HID_81d05] = 153,
+	[BNXT_ULP_CLASS_HID_8098d] = 154,
+	[BNXT_ULP_CLASS_HID_80ac3] = 155,
+	[BNXT_ULP_CLASS_HID_8172d] = 156,
+	[BNXT_ULP_CLASS_HID_80753] = 157,
+	[BNXT_ULP_CLASS_HID_813bd] = 158,
+	[BNXT_ULP_CLASS_HID_814f3] = 159,
+	[BNXT_ULP_CLASS_HID_8017b] = 160,
+	[BNXT_ULP_CLASS_HID_c002f] = 161,
+	[BNXT_ULP_CLASS_HID_c0c09] = 162,
+	[BNXT_ULP_CLASS_HID_c0d4f] = 163,
+	[BNXT_ULP_CLASS_HID_c19a9] = 164,
+	[BNXT_ULP_CLASS_HID_c09df] = 165,
+	[BNXT_ULP_CLASS_HID_c1639] = 166,
+	[BNXT_ULP_CLASS_HID_c177f] = 167,
+	[BNXT_ULP_CLASS_HID_c03e7] = 168,
+	[BNXT_ULP_CLASS_HID_a1e43] = 169,
+	[BNXT_ULP_CLASS_HID_a0acb] = 170,
+	[BNXT_ULP_CLASS_HID_a0c01] = 171,
+	[BNXT_ULP_CLASS_HID_a186b] = 172,
+	[BNXT_ULP_CLASS_HID_a0891] = 173,
+	[BNXT_ULP_CLASS_HID_a14fb] = 174,
+	[BNXT_ULP_CLASS_HID_a1631] = 175,
+	[BNXT_ULP_CLASS_HID_a02b9] = 176,
+	[BNXT_ULP_CLASS_HID_e016d] = 177,
+	[BNXT_ULP_CLASS_HID_e0d77] = 178,
+	[BNXT_ULP_CLASS_HID_e0e8d] = 179,
+	[BNXT_ULP_CLASS_HID_e1a97] = 180,
+	[BNXT_ULP_CLASS_HID_e0b1d] = 181,
+	[BNXT_ULP_CLASS_HID_e1767] = 182,
+	[BNXT_ULP_CLASS_HID_e18bd] = 183,
+	[BNXT_ULP_CLASS_HID_e0525] = 184,
+	[BNXT_ULP_CLASS_HID_21957] = 185,
+	[BNXT_ULP_CLASS_HID_205cf] = 186,
+	[BNXT_ULP_CLASS_HID_20715] = 187,
+	[BNXT_ULP_CLASS_HID_2136f] = 188,
+	[BNXT_ULP_CLASS_HID_61bcb] = 189,
+	[BNXT_ULP_CLASS_HID_60843] = 190,
+	[BNXT_ULP_CLASS_HID_60989] = 191,
+	[BNXT_ULP_CLASS_HID_615e3] = 192,
+	[BNXT_ULP_CLASS_HID_30a65] = 193,
+	[BNXT_ULP_CLASS_HID_3167f] = 194,
+	[BNXT_ULP_CLASS_HID_31785] = 195,
+	[BNXT_ULP_CLASS_HID_3043d] = 196,
+	[BNXT_ULP_CLASS_HID_70c99] = 197,
+	[BNXT_ULP_CLASS_HID_718f3] = 198,
+	[BNXT_ULP_CLASS_HID_71a39] = 199,
+	[BNXT_ULP_CLASS_HID_706b1] = 200,
+	[BNXT_ULP_CLASS_HID_2822d] = 201,
+	[BNXT_ULP_CLASS_HID_28e07] = 202,
+	[BNXT_ULP_CLASS_HID_28f4d] = 203,
+	[BNXT_ULP_CLASS_HID_29ba7] = 204,
+	[BNXT_ULP_CLASS_HID_684a1] = 205,
+	[BNXT_ULP_CLASS_HID_690bb] = 206,
+	[BNXT_ULP_CLASS_HID_691c1] = 207,
+	[BNXT_ULP_CLASS_HID_69ddb] = 208,
+	[BNXT_ULP_CLASS_HID_3925d] = 209,
+	[BNXT_ULP_CLASS_HID_39eb7] = 210,
+	[BNXT_ULP_CLASS_HID_38013] = 211,
+	[BNXT_ULP_CLASS_HID_38c75] = 212,
+	[BNXT_ULP_CLASS_HID_794d1] = 213,
+	[BNXT_ULP_CLASS_HID_78149] = 214,
+	[BNXT_ULP_CLASS_HID_78297] = 215,
+	[BNXT_ULP_CLASS_HID_78ee9] = 216,
+	[BNXT_ULP_CLASS_HID_0816] = 217,
+	[BNXT_ULP_CLASS_HID_1852] = 218,
+	[BNXT_ULP_CLASS_HID_09f4] = 219,
+	[BNXT_ULP_CLASS_HID_1dd4] = 220,
+	[BNXT_ULP_CLASS_HID_804f1] = 221,
+	[BNXT_ULP_CLASS_HID_81251] = 222,
+	[BNXT_ULP_CLASS_HID_80ee1] = 223,
+	[BNXT_ULP_CLASS_HID_81c41] = 224,
+	[BNXT_ULP_CLASS_HID_2013b] = 225,
+	[BNXT_ULP_CLASS_HID_20e9b] = 226,
+	[BNXT_ULP_CLASS_HID_603bf] = 227,
+	[BNXT_ULP_CLASS_HID_6111f] = 228,
+	[BNXT_ULP_CLASS_HID_0806] = 229,
+	[BNXT_ULP_CLASS_HID_1842] = 230,
+	[BNXT_ULP_CLASS_HID_1be6] = 231,
+	[BNXT_ULP_CLASS_HID_0c80] = 232,
+	[BNXT_ULP_CLASS_HID_1216] = 233,
+	[BNXT_ULP_CLASS_HID_02b0] = 234,
+	[BNXT_ULP_CLASS_HID_0654] = 235,
+	[BNXT_ULP_CLASS_HID_1690] = 236,
+	[BNXT_ULP_CLASS_HID_09e4] = 237,
+	[BNXT_ULP_CLASS_HID_1dc4] = 238,
+	[BNXT_ULP_CLASS_HID_80efc] = 239,
+	[BNXT_ULP_CLASS_HID_80332] = 240,
+	[BNXT_ULP_CLASS_HID_40c78] = 241,
+	[BNXT_ULP_CLASS_HID_400be] = 242,
+	[BNXT_ULP_CLASS_HID_c1170] = 243,
+	[BNXT_ULP_CLASS_HID_c05b6] = 244,
+	[BNXT_ULP_CLASS_HID_0836] = 245,
+	[BNXT_ULP_CLASS_HID_1872] = 246,
+	[BNXT_ULP_CLASS_HID_1bd6] = 247,
+	[BNXT_ULP_CLASS_HID_0cb0] = 248,
+	[BNXT_ULP_CLASS_HID_1226] = 249,
+	[BNXT_ULP_CLASS_HID_0280] = 250,
+	[BNXT_ULP_CLASS_HID_0664] = 251,
+	[BNXT_ULP_CLASS_HID_16a0] = 252,
+	[BNXT_ULP_CLASS_HID_09d4] = 253,
+	[BNXT_ULP_CLASS_HID_1df4] = 254,
+	[BNXT_ULP_CLASS_HID_80ecc] = 255,
+	[BNXT_ULP_CLASS_HID_80302] = 256,
+	[BNXT_ULP_CLASS_HID_40c48] = 257,
+	[BNXT_ULP_CLASS_HID_4008e] = 258,
+	[BNXT_ULP_CLASS_HID_c1140] = 259,
+	[BNXT_ULP_CLASS_HID_c0586] = 260,
+	[BNXT_ULP_CLASS_HID_804e1] = 261,
+	[BNXT_ULP_CLASS_HID_81241] = 262,
+	[BNXT_ULP_CLASS_HID_80ef1] = 263,
+	[BNXT_ULP_CLASS_HID_81c51] = 264,
+	[BNXT_ULP_CLASS_HID_c076d] = 265,
+	[BNXT_ULP_CLASS_HID_c14cd] = 266,
+	[BNXT_ULP_CLASS_HID_c117d] = 267,
+	[BNXT_ULP_CLASS_HID_c1edd] = 268,
+	[BNXT_ULP_CLASS_HID_a062f] = 269,
+	[BNXT_ULP_CLASS_HID_a138f] = 270,
+	[BNXT_ULP_CLASS_HID_a103f] = 271,
+	[BNXT_ULP_CLASS_HID_a1d9f] = 272,
+	[BNXT_ULP_CLASS_HID_e08ab] = 273,
+	[BNXT_ULP_CLASS_HID_e160b] = 274,
+	[BNXT_ULP_CLASS_HID_e12bb] = 275,
+	[BNXT_ULP_CLASS_HID_e0079] = 276,
+	[BNXT_ULP_CLASS_HID_2012b] = 277,
+	[BNXT_ULP_CLASS_HID_20e8b] = 278,
+	[BNXT_ULP_CLASS_HID_603af] = 279,
+	[BNXT_ULP_CLASS_HID_6110f] = 280,
+	[BNXT_ULP_CLASS_HID_311bb] = 281,
+	[BNXT_ULP_CLASS_HID_31f1b] = 282,
+	[BNXT_ULP_CLASS_HID_7143f] = 283,
+	[BNXT_ULP_CLASS_HID_701fd] = 284,
+	[BNXT_ULP_CLASS_HID_28963] = 285,
+	[BNXT_ULP_CLASS_HID_296c3] = 286,
+	[BNXT_ULP_CLASS_HID_68be7] = 287,
+	[BNXT_ULP_CLASS_HID_69947] = 288,
+	[BNXT_ULP_CLASS_HID_399f3] = 289,
+	[BNXT_ULP_CLASS_HID_387b1] = 290,
+	[BNXT_ULP_CLASS_HID_79c77] = 291,
+	[BNXT_ULP_CLASS_HID_78a35] = 292,
+	[BNXT_ULP_CLASS_HID_804d1] = 293,
+	[BNXT_ULP_CLASS_HID_81271] = 294,
+	[BNXT_ULP_CLASS_HID_80ec1] = 295,
+	[BNXT_ULP_CLASS_HID_81c61] = 296,
+	[BNXT_ULP_CLASS_HID_c075d] = 297,
+	[BNXT_ULP_CLASS_HID_c14fd] = 298,
+	[BNXT_ULP_CLASS_HID_c114d] = 299,
+	[BNXT_ULP_CLASS_HID_c1eed] = 300,
+	[BNXT_ULP_CLASS_HID_a061f] = 301,
+	[BNXT_ULP_CLASS_HID_a13bf] = 302,
+	[BNXT_ULP_CLASS_HID_a100f] = 303,
+	[BNXT_ULP_CLASS_HID_a1daf] = 304,
+	[BNXT_ULP_CLASS_HID_e089b] = 305,
+	[BNXT_ULP_CLASS_HID_e163b] = 306,
+	[BNXT_ULP_CLASS_HID_e128b] = 307,
+	[BNXT_ULP_CLASS_HID_e0049] = 308,
+	[BNXT_ULP_CLASS_HID_2011b] = 309,
+	[BNXT_ULP_CLASS_HID_20ebb] = 310,
+	[BNXT_ULP_CLASS_HID_6039f] = 311,
+	[BNXT_ULP_CLASS_HID_6113f] = 312,
+	[BNXT_ULP_CLASS_HID_3118b] = 313,
+	[BNXT_ULP_CLASS_HID_31f2b] = 314,
+	[BNXT_ULP_CLASS_HID_7140f] = 315,
+	[BNXT_ULP_CLASS_HID_701cd] = 316,
+	[BNXT_ULP_CLASS_HID_28953] = 317,
+	[BNXT_ULP_CLASS_HID_296f3] = 318,
+	[BNXT_ULP_CLASS_HID_68bd7] = 319,
+	[BNXT_ULP_CLASS_HID_69977] = 320,
+	[BNXT_ULP_CLASS_HID_399c3] = 321,
+	[BNXT_ULP_CLASS_HID_38781] = 322,
+	[BNXT_ULP_CLASS_HID_79c47] = 323,
+	[BNXT_ULP_CLASS_HID_78a05] = 324,
+	[BNXT_ULP_CLASS_HID_04a4] = 325,
+	[BNXT_ULP_CLASS_HID_04a8] = 326,
+	[BNXT_ULP_CLASS_HID_04a5] = 327,
+	[BNXT_ULP_CLASS_HID_1205] = 328,
+	[BNXT_ULP_CLASS_HID_04a9] = 329,
+	[BNXT_ULP_CLASS_HID_1209] = 330,
+	[BNXT_ULP_CLASS_HID_04b4] = 331,
+	[BNXT_ULP_CLASS_HID_04b8] = 332,
+	[BNXT_ULP_CLASS_HID_0484] = 333,
+	[BNXT_ULP_CLASS_HID_0488] = 334,
+	[BNXT_ULP_CLASS_HID_04b5] = 335,
+	[BNXT_ULP_CLASS_HID_1215] = 336,
+	[BNXT_ULP_CLASS_HID_04b9] = 337,
+	[BNXT_ULP_CLASS_HID_1219] = 338,
+	[BNXT_ULP_CLASS_HID_0485] = 339,
+	[BNXT_ULP_CLASS_HID_1225] = 340,
+	[BNXT_ULP_CLASS_HID_0489] = 341,
+	[BNXT_ULP_CLASS_HID_1229] = 342,
+	[BNXT_ULP_CLASS_HID_0226] = 343,
+	[BNXT_ULP_CLASS_HID_4045a] = 344,
+	[BNXT_ULP_CLASS_HID_0daa] = 345,
+	[BNXT_ULP_CLASS_HID_11b0] = 346,
+	[BNXT_ULP_CLASS_HID_403f8] = 347,
+	[BNXT_ULP_CLASS_HID_4161e] = 348,
+	[BNXT_ULP_CLASS_HID_40439] = 349,
+	[BNXT_ULP_CLASS_HID_41405] = 350,
+	[BNXT_ULP_CLASS_HID_51449] = 351,
+	[BNXT_ULP_CLASS_HID_50b33] = 352,
+	[BNXT_ULP_CLASS_HID_48c01] = 353,
+	[BNXT_ULP_CLASS_HID_483eb] = 354,
+	[BNXT_ULP_CLASS_HID_5833f] = 355,
+	[BNXT_ULP_CLASS_HID_5937b] = 356,
+	[BNXT_ULP_CLASS_HID_41875] = 357,
+	[BNXT_ULP_CLASS_HID_40f5f] = 358,
+	[BNXT_ULP_CLASS_HID_50f23] = 359,
+	[BNXT_ULP_CLASS_HID_51f6f] = 360,
+	[BNXT_ULP_CLASS_HID_4875b] = 361,
+	[BNXT_ULP_CLASS_HID_49727] = 362,
+	[BNXT_ULP_CLASS_HID_5976b] = 363,
+	[BNXT_ULP_CLASS_HID_58655] = 364,
+	[BNXT_ULP_CLASS_HID_4125f] = 365,
+	[BNXT_ULP_CLASS_HID_401f9] = 366,
+	[BNXT_ULP_CLASS_HID_501cd] = 367,
+	[BNXT_ULP_CLASS_HID_51149] = 368,
+	[BNXT_ULP_CLASS_HID_49a67] = 369,
+	[BNXT_ULP_CLASS_HID_489c1] = 370,
+	[BNXT_ULP_CLASS_HID_58955] = 371,
+	[BNXT_ULP_CLASS_HID_59951] = 372,
+	[BNXT_ULP_CLASS_HID_40569] = 373,
+	[BNXT_ULP_CLASS_HID_41575] = 374,
+	[BNXT_ULP_CLASS_HID_51579] = 375,
+	[BNXT_ULP_CLASS_HID_50463] = 376,
+	[BNXT_ULP_CLASS_HID_48d71] = 377,
+	[BNXT_ULP_CLASS_HID_49d7d] = 378,
+	[BNXT_ULP_CLASS_HID_59d41] = 379,
+	[BNXT_ULP_CLASS_HID_58c6b] = 380,
+	[BNXT_ULP_CLASS_HID_10255] = 381,
+	[BNXT_ULP_CLASS_HID_11675] = 382,
+	[BNXT_ULP_CLASS_HID_14649] = 383,
+	[BNXT_ULP_CLASS_HID_15a69] = 384,
+	[BNXT_ULP_CLASS_HID_1205b] = 385,
+	[BNXT_ULP_CLASS_HID_1347b] = 386,
+	[BNXT_ULP_CLASS_HID_16bbf] = 387,
+	[BNXT_ULP_CLASS_HID_1785f] = 388,
+	[BNXT_ULP_CLASS_HID_11551] = 389,
+	[BNXT_ULP_CLASS_HID_10897] = 390,
+	[BNXT_ULP_CLASS_HID_15955] = 391,
+	[BNXT_ULP_CLASS_HID_14c8b] = 392,
+	[BNXT_ULP_CLASS_HID_13b47] = 393,
+	[BNXT_ULP_CLASS_HID_12e85] = 394,
+	[BNXT_ULP_CLASS_HID_17f5b] = 395,
+	[BNXT_ULP_CLASS_HID_17299] = 396,
+	[BNXT_ULP_CLASS_HID_10fe7] = 397,
+	[BNXT_ULP_CLASS_HID_10325] = 398,
+	[BNXT_ULP_CLASS_HID_153cb] = 399,
+	[BNXT_ULP_CLASS_HID_14709] = 400,
+	[BNXT_ULP_CLASS_HID_12dc5] = 401,
+	[BNXT_ULP_CLASS_HID_1212b] = 402,
+	[BNXT_ULP_CLASS_HID_171c9] = 403,
+	[BNXT_ULP_CLASS_HID_1650f] = 404,
+	[BNXT_ULP_CLASS_HID_10201] = 405,
+	[BNXT_ULP_CLASS_HID_116c1] = 406,
+	[BNXT_ULP_CLASS_HID_14605] = 407,
+	[BNXT_ULP_CLASS_HID_15a05] = 408,
+	[BNXT_ULP_CLASS_HID_12007] = 409,
+	[BNXT_ULP_CLASS_HID_13407] = 410,
+	[BNXT_ULP_CLASS_HID_1640b] = 411,
+	[BNXT_ULP_CLASS_HID_1780b] = 412,
+	[BNXT_ULP_CLASS_HID_404b0] = 413,
+	[BNXT_ULP_CLASS_HID_4148c] = 414,
+	[BNXT_ULP_CLASS_HID_514c0] = 415,
+	[BNXT_ULP_CLASS_HID_50bba] = 416,
+	[BNXT_ULP_CLASS_HID_48c88] = 417,
+	[BNXT_ULP_CLASS_HID_48362] = 418,
+	[BNXT_ULP_CLASS_HID_583b6] = 419,
+	[BNXT_ULP_CLASS_HID_593f2] = 420,
+	[BNXT_ULP_CLASS_HID_41f54] = 421,
+	[BNXT_ULP_CLASS_HID_40fce] = 422,
+	[BNXT_ULP_CLASS_HID_50e02] = 423,
+	[BNXT_ULP_CLASS_HID_51e5e] = 424,
+	[BNXT_ULP_CLASS_HID_487ca] = 425,
+	[BNXT_ULP_CLASS_HID_49606] = 426,
+	[BNXT_ULP_CLASS_HID_5965a] = 427,
+	[BNXT_ULP_CLASS_HID_58514] = 428,
+	[BNXT_ULP_CLASS_HID_412c2] = 429,
+	[BNXT_ULP_CLASS_HID_401ac] = 430,
+	[BNXT_ULP_CLASS_HID_501e0] = 431,
+	[BNXT_ULP_CLASS_HID_511cc] = 432,
+	[BNXT_ULP_CLASS_HID_4990a] = 433,
+	[BNXT_ULP_CLASS_HID_489e4] = 434,
+	[BNXT_ULP_CLASS_HID_589c8] = 435,
+	[BNXT_ULP_CLASS_HID_59804] = 436,
+	[BNXT_ULP_CLASS_HID_40404] = 437,
+	[BNXT_ULP_CLASS_HID_41440] = 438,
+	[BNXT_ULP_CLASS_HID_51484] = 439,
+	[BNXT_ULP_CLASS_HID_50b0e] = 440,
+	[BNXT_ULP_CLASS_HID_48c4c] = 441,
+	[BNXT_ULP_CLASS_HID_48306] = 442,
+	[BNXT_ULP_CLASS_HID_5830a] = 443,
+	[BNXT_ULP_CLASS_HID_59346] = 444,
+	[BNXT_ULP_CLASS_HID_102cc] = 445,
+	[BNXT_ULP_CLASS_HID_116ec] = 446,
+	[BNXT_ULP_CLASS_HID_146d0] = 447,
+	[BNXT_ULP_CLASS_HID_15af0] = 448,
+	[BNXT_ULP_CLASS_HID_120c2] = 449,
+	[BNXT_ULP_CLASS_HID_134e2] = 450,
+	[BNXT_ULP_CLASS_HID_16b26] = 451,
+	[BNXT_ULP_CLASS_HID_178c6] = 452,
+	[BNXT_ULP_CLASS_HID_115c6] = 453,
+	[BNXT_ULP_CLASS_HID_10804] = 454,
+	[BNXT_ULP_CLASS_HID_15822] = 455,
+	[BNXT_ULP_CLASS_HID_14c60] = 456,
+	[BNXT_ULP_CLASS_HID_13bd4] = 457,
+	[BNXT_ULP_CLASS_HID_12e12] = 458,
+	[BNXT_ULP_CLASS_HID_17e30] = 459,
+	[BNXT_ULP_CLASS_HID_17276] = 460,
+	[BNXT_ULP_CLASS_HID_11f1a] = 461,
+	[BNXT_ULP_CLASS_HID_11358] = 462,
+	[BNXT_ULP_CLASS_HID_14398] = 463,
+	[BNXT_ULP_CLASS_HID_157b8] = 464,
+	[BNXT_ULP_CLASS_HID_13d68] = 465,
+	[BNXT_ULP_CLASS_HID_131aa] = 466,
+	[BNXT_ULP_CLASS_HID_16192] = 467,
+	[BNXT_ULP_CLASS_HID_175b2] = 468,
+	[BNXT_ULP_CLASS_HID_112b2] = 469,
+	[BNXT_ULP_CLASS_HID_106f0] = 470,
+	[BNXT_ULP_CLASS_HID_15692] = 471,
+	[BNXT_ULP_CLASS_HID_14ad0] = 472,
+	[BNXT_ULP_CLASS_HID_13080] = 473,
+	[BNXT_ULP_CLASS_HID_124c2] = 474,
+	[BNXT_ULP_CLASS_HID_174e0] = 475,
+	[BNXT_ULP_CLASS_HID_16f22] = 476,
+	[BNXT_ULP_CLASS_HID_4025b] = 477,
+	[BNXT_ULP_CLASS_HID_41267] = 478,
+	[BNXT_ULP_CLASS_HID_5122b] = 479,
+	[BNXT_ULP_CLASS_HID_50d51] = 480,
+	[BNXT_ULP_CLASS_HID_48a63] = 481,
+	[BNXT_ULP_CLASS_HID_48589] = 482,
+	[BNXT_ULP_CLASS_HID_5855d] = 483,
+	[BNXT_ULP_CLASS_HID_59519] = 484,
+	[BNXT_ULP_CLASS_HID_41e17] = 485,
+	[BNXT_ULP_CLASS_HID_4093d] = 486,
+	[BNXT_ULP_CLASS_HID_50941] = 487,
+	[BNXT_ULP_CLASS_HID_5190d] = 488,
+	[BNXT_ULP_CLASS_HID_48139] = 489,
+	[BNXT_ULP_CLASS_HID_49145] = 490,
+	[BNXT_ULP_CLASS_HID_59109] = 491,
+	[BNXT_ULP_CLASS_HID_58037] = 492,
+	[BNXT_ULP_CLASS_HID_4143d] = 493,
+	[BNXT_ULP_CLASS_HID_4079b] = 494,
+	[BNXT_ULP_CLASS_HID_507af] = 495,
+	[BNXT_ULP_CLASS_HID_5172b] = 496,
+	[BNXT_ULP_CLASS_HID_49c05] = 497,
+	[BNXT_ULP_CLASS_HID_48fa3] = 498,
+	[BNXT_ULP_CLASS_HID_58f37] = 499,
+	[BNXT_ULP_CLASS_HID_59f33] = 500,
+	[BNXT_ULP_CLASS_HID_4030b] = 501,
+	[BNXT_ULP_CLASS_HID_41317] = 502,
+	[BNXT_ULP_CLASS_HID_5131b] = 503,
+	[BNXT_ULP_CLASS_HID_50201] = 504,
+	[BNXT_ULP_CLASS_HID_48b13] = 505,
+	[BNXT_ULP_CLASS_HID_49b1f] = 506,
+	[BNXT_ULP_CLASS_HID_59b23] = 507,
+	[BNXT_ULP_CLASS_HID_58a09] = 508,
+	[BNXT_ULP_CLASS_HID_419bf] = 509,
+	[BNXT_ULP_CLASS_HID_40925] = 510,
+	[BNXT_ULP_CLASS_HID_508e9] = 511,
+	[BNXT_ULP_CLASS_HID_518b5] = 512,
+	[BNXT_ULP_CLASS_HID_48121] = 513,
+	[BNXT_ULP_CLASS_HID_490ed] = 514,
+	[BNXT_ULP_CLASS_HID_590b1] = 515,
+	[BNXT_ULP_CLASS_HID_583ff] = 516,
+	[BNXT_ULP_CLASS_HID_41475] = 517,
+	[BNXT_ULP_CLASS_HID_40473] = 518,
+	[BNXT_ULP_CLASS_HID_50427] = 519,
+	[BNXT_ULP_CLASS_HID_51763] = 520,
+	[BNXT_ULP_CLASS_HID_49c3d] = 521,
+	[BNXT_ULP_CLASS_HID_48c3b] = 522,
+	[BNXT_ULP_CLASS_HID_58f6f] = 523,
+	[BNXT_ULP_CLASS_HID_59f2b] = 524,
+	[BNXT_ULP_CLASS_HID_40333] = 525,
+	[BNXT_ULP_CLASS_HID_412bf] = 526,
+	[BNXT_ULP_CLASS_HID_512a3] = 527,
+	[BNXT_ULP_CLASS_HID_50229] = 528,
+	[BNXT_ULP_CLASS_HID_48abb] = 529,
+	[BNXT_ULP_CLASS_HID_49aa7] = 530,
+	[BNXT_ULP_CLASS_HID_59a2b] = 531,
+	[BNXT_ULP_CLASS_HID_595b1] = 532,
+	[BNXT_ULP_CLASS_HID_41e2f] = 533,
+	[BNXT_ULP_CLASS_HID_40e35] = 534,
+	[BNXT_ULP_CLASS_HID_50939] = 535,
+	[BNXT_ULP_CLASS_HID_51925] = 536,
+	[BNXT_ULP_CLASS_HID_48631] = 537,
+	[BNXT_ULP_CLASS_HID_4913d] = 538,
+	[BNXT_ULP_CLASS_HID_59121] = 539,
+	[BNXT_ULP_CLASS_HID_5812f] = 540,
+	[BNXT_ULP_CLASS_HID_41429] = 541,
+	[BNXT_ULP_CLASS_HID_40747] = 542,
+	[BNXT_ULP_CLASS_HID_5070b] = 543,
+	[BNXT_ULP_CLASS_HID_51727] = 544,
+	[BNXT_ULP_CLASS_HID_49fe1] = 545,
+	[BNXT_ULP_CLASS_HID_48f0f] = 546,
+	[BNXT_ULP_CLASS_HID_58f23] = 547,
+	[BNXT_ULP_CLASS_HID_59eef] = 548,
+	[BNXT_ULP_CLASS_HID_40347] = 549,
+	[BNXT_ULP_CLASS_HID_41303] = 550,
+	[BNXT_ULP_CLASS_HID_51247] = 551,
+	[BNXT_ULP_CLASS_HID_5026d] = 552,
+	[BNXT_ULP_CLASS_HID_48b0f] = 553,
+	[BNXT_ULP_CLASS_HID_49a4b] = 554,
+	[BNXT_ULP_CLASS_HID_59a0f] = 555,
+	[BNXT_ULP_CLASS_HID_58a05] = 556,
+	[BNXT_ULP_CLASS_HID_41983] = 557,
+	[BNXT_ULP_CLASS_HID_40929] = 558,
+	[BNXT_ULP_CLASS_HID_5092d] = 559,
+	[BNXT_ULP_CLASS_HID_518a9] = 560,
+	[BNXT_ULP_CLASS_HID_48125] = 561,
+	[BNXT_ULP_CLASS_HID_49121] = 562,
+	[BNXT_ULP_CLASS_HID_59085] = 563,
+	[BNXT_ULP_CLASS_HID_58023] = 564,
+	[BNXT_ULP_CLASS_HID_41509] = 565,
+	[BNXT_ULP_CLASS_HID_40407] = 566,
+	[BNXT_ULP_CLASS_HID_5040b] = 567,
+	[BNXT_ULP_CLASS_HID_51407] = 568,
+	[BNXT_ULP_CLASS_HID_49d21] = 569,
+	[BNXT_ULP_CLASS_HID_48c0f] = 570,
+	[BNXT_ULP_CLASS_HID_58c03] = 571,
+	[BNXT_ULP_CLASS_HID_59f0f] = 572,
+	[BNXT_ULP_CLASS_HID_402ef] = 573,
+	[BNXT_ULP_CLASS_HID_412ab] = 574,
+	[BNXT_ULP_CLASS_HID_5126f] = 575,
+	[BNXT_ULP_CLASS_HID_50de5] = 576,
+	[BNXT_ULP_CLASS_HID_48aa7] = 577,
+	[BNXT_ULP_CLASS_HID_485ed] = 578,
+	[BNXT_ULP_CLASS_HID_585e1] = 579,
+	[BNXT_ULP_CLASS_HID_595ad] = 580,
+	[BNXT_ULP_CLASS_HID_41e6b] = 581,
+	[BNXT_ULP_CLASS_HID_40961] = 582,
+	[BNXT_ULP_CLASS_HID_50925] = 583,
+	[BNXT_ULP_CLASS_HID_51961] = 584,
+	[BNXT_ULP_CLASS_HID_4816d] = 585,
+	[BNXT_ULP_CLASS_HID_49129] = 586,
+	[BNXT_ULP_CLASS_HID_5916d] = 587,
+	[BNXT_ULP_CLASS_HID_5806b] = 588,
+	[BNXT_ULP_CLASS_HID_414a1] = 589,
+	[BNXT_ULP_CLASS_HID_4042f] = 590,
+	[BNXT_ULP_CLASS_HID_507a3] = 591,
+	[BNXT_ULP_CLASS_HID_517af] = 592,
+	[BNXT_ULP_CLASS_HID_49c29] = 593,
+	[BNXT_ULP_CLASS_HID_48fa7] = 594,
+	[BNXT_ULP_CLASS_HID_58fab] = 595,
+	[BNXT_ULP_CLASS_HID_59f27] = 596,
+	[BNXT_ULP_CLASS_HID_4032f] = 597,
+	[BNXT_ULP_CLASS_HID_4132b] = 598,
+	[BNXT_ULP_CLASS_HID_5132f] = 599,
+	[BNXT_ULP_CLASS_HID_50225] = 600,
+	[BNXT_ULP_CLASS_HID_48b27] = 601,
+	[BNXT_ULP_CLASS_HID_49b23] = 602,
+	[BNXT_ULP_CLASS_HID_59b27] = 603,
+	[BNXT_ULP_CLASS_HID_58a2d] = 604,
+	[BNXT_ULP_CLASS_HID_10437] = 605,
+	[BNXT_ULP_CLASS_HID_11017] = 606,
+	[BNXT_ULP_CLASS_HID_1402b] = 607,
+	[BNXT_ULP_CLASS_HID_15c0b] = 608,
+	[BNXT_ULP_CLASS_HID_12639] = 609,
+	[BNXT_ULP_CLASS_HID_13219] = 610,
+	[BNXT_ULP_CLASS_HID_16ddd] = 611,
+	[BNXT_ULP_CLASS_HID_17e3d] = 612,
+	[BNXT_ULP_CLASS_HID_11333] = 613,
+	[BNXT_ULP_CLASS_HID_10ef5] = 614,
+	[BNXT_ULP_CLASS_HID_15f37] = 615,
+	[BNXT_ULP_CLASS_HID_14ae9] = 616,
+	[BNXT_ULP_CLASS_HID_13d25] = 617,
+	[BNXT_ULP_CLASS_HID_128e7] = 618,
+	[BNXT_ULP_CLASS_HID_17939] = 619,
+	[BNXT_ULP_CLASS_HID_174fb] = 620,
+	[BNXT_ULP_CLASS_HID_10985] = 621,
+	[BNXT_ULP_CLASS_HID_10547] = 622,
+	[BNXT_ULP_CLASS_HID_155a9] = 623,
+	[BNXT_ULP_CLASS_HID_1416b] = 624,
+	[BNXT_ULP_CLASS_HID_12ba7] = 625,
+	[BNXT_ULP_CLASS_HID_12749] = 626,
+	[BNXT_ULP_CLASS_HID_177ab] = 627,
+	[BNXT_ULP_CLASS_HID_1636d] = 628,
+	[BNXT_ULP_CLASS_HID_10463] = 629,
+	[BNXT_ULP_CLASS_HID_110a3] = 630,
+	[BNXT_ULP_CLASS_HID_14067] = 631,
+	[BNXT_ULP_CLASS_HID_15c67] = 632,
+	[BNXT_ULP_CLASS_HID_12665] = 633,
+	[BNXT_ULP_CLASS_HID_13265] = 634,
+	[BNXT_ULP_CLASS_HID_16269] = 635,
+	[BNXT_ULP_CLASS_HID_17e69] = 636,
+	[BNXT_ULP_CLASS_HID_1133d] = 637,
+	[BNXT_ULP_CLASS_HID_10eff] = 638,
+	[BNXT_ULP_CLASS_HID_15ed9] = 639,
+	[BNXT_ULP_CLASS_HID_14a9b] = 640,
+	[BNXT_ULP_CLASS_HID_13d2f] = 641,
+	[BNXT_ULP_CLASS_HID_128e9] = 642,
+	[BNXT_ULP_CLASS_HID_178cb] = 643,
+	[BNXT_ULP_CLASS_HID_1748d] = 644,
+	[BNXT_ULP_CLASS_HID_109fb] = 645,
+	[BNXT_ULP_CLASS_HID_105bd] = 646,
+	[BNXT_ULP_CLASS_HID_155bf] = 647,
+	[BNXT_ULP_CLASS_HID_14179] = 648,
+	[BNXT_ULP_CLASS_HID_12bed] = 649,
+	[BNXT_ULP_CLASS_HID_127af] = 650,
+	[BNXT_ULP_CLASS_HID_177a9] = 651,
+	[BNXT_ULP_CLASS_HID_1636b] = 652,
+	[BNXT_ULP_CLASS_HID_1046d] = 653,
+	[BNXT_ULP_CLASS_HID_1104d] = 654,
+	[BNXT_ULP_CLASS_HID_14009] = 655,
+	[BNXT_ULP_CLASS_HID_15c69] = 656,
+	[BNXT_ULP_CLASS_HID_1260f] = 657,
+	[BNXT_ULP_CLASS_HID_1326f] = 658,
+	[BNXT_ULP_CLASS_HID_1622b] = 659,
+	[BNXT_ULP_CLASS_HID_17e0b] = 660,
+	[BNXT_ULP_CLASS_HID_11369] = 661,
+	[BNXT_ULP_CLASS_HID_10f2b] = 662,
+	[BNXT_ULP_CLASS_HID_15f6d] = 663,
+	[BNXT_ULP_CLASS_HID_14b2f] = 664,
+	[BNXT_ULP_CLASS_HID_13d6b] = 665,
+	[BNXT_ULP_CLASS_HID_1292d] = 666,
+	[BNXT_ULP_CLASS_HID_1792f] = 667,
+	[BNXT_ULP_CLASS_HID_174e9] = 668,
+	[BNXT_ULP_CLASS_HID_119e1] = 669,
+	[BNXT_ULP_CLASS_HID_115a3] = 670,
+	[BNXT_ULP_CLASS_HID_14563] = 671,
+	[BNXT_ULP_CLASS_HID_15143] = 672,
+	[BNXT_ULP_CLASS_HID_13b93] = 673,
+	[BNXT_ULP_CLASS_HID_13751] = 674,
+	[BNXT_ULP_CLASS_HID_16769] = 675,
+	[BNXT_ULP_CLASS_HID_17349] = 676,
+	[BNXT_ULP_CLASS_HID_114ab] = 677,
+	[BNXT_ULP_CLASS_HID_10061] = 678,
+	[BNXT_ULP_CLASS_HID_15063] = 679,
+	[BNXT_ULP_CLASS_HID_14c21] = 680,
+	[BNXT_ULP_CLASS_HID_13671] = 681,
+	[BNXT_ULP_CLASS_HID_12233] = 682,
+	[BNXT_ULP_CLASS_HID_17271] = 683,
+	[BNXT_ULP_CLASS_HID_16e33] = 684,
+	[BNXT_ULP_CLASS_HID_102c1] = 685,
+	[BNXT_ULP_CLASS_HID_11f21] = 686,
+	[BNXT_ULP_CLASS_HID_14ee1] = 687,
+	[BNXT_ULP_CLASS_HID_15ac1] = 688,
+	[BNXT_ULP_CLASS_HID_12cc3] = 689,
+	[BNXT_ULP_CLASS_HID_13923] = 690,
+	[BNXT_ULP_CLASS_HID_168e3] = 691,
+	[BNXT_ULP_CLASS_HID_164a9] = 692,
+	[BNXT_ULP_CLASS_HID_11e29] = 693,
+	[BNXT_ULP_CLASS_HID_115eb] = 694,
+	[BNXT_ULP_CLASS_HID_145a3] = 695,
+	[BNXT_ULP_CLASS_HID_151a3] = 696,
+	[BNXT_ULP_CLASS_HID_1382b] = 697,
+	[BNXT_ULP_CLASS_HID_137e1] = 698,
+	[BNXT_ULP_CLASS_HID_167a1] = 699,
+	[BNXT_ULP_CLASS_HID_173a1] = 700,
+	[BNXT_ULP_CLASS_HID_11449] = 701,
+	[BNXT_ULP_CLASS_HID_1000b] = 702,
+	[BNXT_ULP_CLASS_HID_15069] = 703,
+	[BNXT_ULP_CLASS_HID_14c2b] = 704,
+	[BNXT_ULP_CLASS_HID_1367b] = 705,
+	[BNXT_ULP_CLASS_HID_12239] = 706,
+	[BNXT_ULP_CLASS_HID_1721b] = 707,
+	[BNXT_ULP_CLASS_HID_169d9] = 708,
+	[BNXT_ULP_CLASS_HID_1033b] = 709,
+	[BNXT_ULP_CLASS_HID_11f3b] = 710,
+	[BNXT_ULP_CLASS_HID_14f2b] = 711,
+	[BNXT_ULP_CLASS_HID_15b2b] = 712,
+	[BNXT_ULP_CLASS_HID_12d39] = 713,
+	[BNXT_ULP_CLASS_HID_13939] = 714,
+	[BNXT_ULP_CLASS_HID_168f9] = 715,
+	[BNXT_ULP_CLASS_HID_164bb] = 716,
+	[BNXT_ULP_CLASS_HID_119cb] = 717,
+	[BNXT_ULP_CLASS_HID_11589] = 718,
+	[BNXT_ULP_CLASS_HID_14549] = 719,
+	[BNXT_ULP_CLASS_HID_151a9] = 720,
+	[BNXT_ULP_CLASS_HID_13bc9] = 721,
+	[BNXT_ULP_CLASS_HID_1378b] = 722,
+	[BNXT_ULP_CLASS_HID_1674b] = 723,
+	[BNXT_ULP_CLASS_HID_173ab] = 724,
+	[BNXT_ULP_CLASS_HID_114a9] = 725,
+	[BNXT_ULP_CLASS_HID_1006b] = 726,
+	[BNXT_ULP_CLASS_HID_150a9] = 727,
+	[BNXT_ULP_CLASS_HID_14c6b] = 728,
+	[BNXT_ULP_CLASS_HID_136ab] = 729,
+	[BNXT_ULP_CLASS_HID_12269] = 730,
+	[BNXT_ULP_CLASS_HID_172ab] = 731,
+	[BNXT_ULP_CLASS_HID_16e69] = 732,
+	[BNXT_ULP_CLASS_HID_402d2] = 733,
+	[BNXT_ULP_CLASS_HID_412ee] = 734,
+	[BNXT_ULP_CLASS_HID_512a2] = 735,
+	[BNXT_ULP_CLASS_HID_50dd8] = 736,
+	[BNXT_ULP_CLASS_HID_48aea] = 737,
+	[BNXT_ULP_CLASS_HID_48500] = 738,
+	[BNXT_ULP_CLASS_HID_585d4] = 739,
+	[BNXT_ULP_CLASS_HID_59590] = 740,
+	[BNXT_ULP_CLASS_HID_41936] = 741,
+	[BNXT_ULP_CLASS_HID_409ac] = 742,
+	[BNXT_ULP_CLASS_HID_50860] = 743,
+	[BNXT_ULP_CLASS_HID_5183c] = 744,
+	[BNXT_ULP_CLASS_HID_481a8] = 745,
+	[BNXT_ULP_CLASS_HID_49064] = 746,
+	[BNXT_ULP_CLASS_HID_59038] = 747,
+	[BNXT_ULP_CLASS_HID_58376] = 748,
+	[BNXT_ULP_CLASS_HID_414a0] = 749,
+	[BNXT_ULP_CLASS_HID_407ce] = 750,
+	[BNXT_ULP_CLASS_HID_50782] = 751,
+	[BNXT_ULP_CLASS_HID_517ae] = 752,
+	[BNXT_ULP_CLASS_HID_49f68] = 753,
+	[BNXT_ULP_CLASS_HID_48f86] = 754,
+	[BNXT_ULP_CLASS_HID_58faa] = 755,
+	[BNXT_ULP_CLASS_HID_59e66] = 756,
+	[BNXT_ULP_CLASS_HID_40266] = 757,
+	[BNXT_ULP_CLASS_HID_41222] = 758,
+	[BNXT_ULP_CLASS_HID_512e6] = 759,
+	[BNXT_ULP_CLASS_HID_50d6c] = 760,
+	[BNXT_ULP_CLASS_HID_48a2e] = 761,
+	[BNXT_ULP_CLASS_HID_48564] = 762,
+	[BNXT_ULP_CLASS_HID_58568] = 763,
+	[BNXT_ULP_CLASS_HID_59524] = 764,
+	[BNXT_ULP_CLASS_HID_419d8] = 765,
+	[BNXT_ULP_CLASS_HID_4087e] = 766,
+	[BNXT_ULP_CLASS_HID_5080a] = 767,
+	[BNXT_ULP_CLASS_HID_518ce] = 768,
+	[BNXT_ULP_CLASS_HID_4807a] = 769,
+	[BNXT_ULP_CLASS_HID_4900e] = 770,
+	[BNXT_ULP_CLASS_HID_590ca] = 771,
+	[BNXT_ULP_CLASS_HID_58378] = 772,
+	[BNXT_ULP_CLASS_HID_414be] = 773,
+	[BNXT_ULP_CLASS_HID_4073c] = 774,
+	[BNXT_ULP_CLASS_HID_507e8] = 775,
+	[BNXT_ULP_CLASS_HID_517ac] = 776,
+	[BNXT_ULP_CLASS_HID_49f7e] = 777,
+	[BNXT_ULP_CLASS_HID_48fec] = 778,
+	[BNXT_ULP_CLASS_HID_58fa8] = 779,
+	[BNXT_ULP_CLASS_HID_59e7c] = 780,
+	[BNXT_ULP_CLASS_HID_40208] = 781,
+	[BNXT_ULP_CLASS_HID_412cc] = 782,
+	[BNXT_ULP_CLASS_HID_51288] = 783,
+	[BNXT_ULP_CLASS_HID_50d2e] = 784,
+	[BNXT_ULP_CLASS_HID_48ac8] = 785,
+	[BNXT_ULP_CLASS_HID_4856e] = 786,
+	[BNXT_ULP_CLASS_HID_5852a] = 787,
+	[BNXT_ULP_CLASS_HID_595ce] = 788,
+	[BNXT_ULP_CLASS_HID_4196c] = 789,
+	[BNXT_ULP_CLASS_HID_409aa] = 790,
+	[BNXT_ULP_CLASS_HID_5086e] = 791,
+	[BNXT_ULP_CLASS_HID_5182a] = 792,
+	[BNXT_ULP_CLASS_HID_481ae] = 793,
+	[BNXT_ULP_CLASS_HID_4906a] = 794,
+	[BNXT_ULP_CLASS_HID_5902e] = 795,
+	[BNXT_ULP_CLASS_HID_580ac] = 796,
+	[BNXT_ULP_CLASS_HID_40766] = 797,
+	[BNXT_ULP_CLASS_HID_41726] = 798,
+	[BNXT_ULP_CLASS_HID_517f6] = 799,
+	[BNXT_ULP_CLASS_HID_5066c] = 800,
+	[BNXT_ULP_CLASS_HID_48f3e] = 801,
+	[BNXT_ULP_CLASS_HID_49ffe] = 802,
+	[BNXT_ULP_CLASS_HID_59f8e] = 803,
+	[BNXT_ULP_CLASS_HID_58e24] = 804,
+	[BNXT_ULP_CLASS_HID_4126e] = 805,
+	[BNXT_ULP_CLASS_HID_402e4] = 806,
+	[BNXT_ULP_CLASS_HID_502b4] = 807,
+	[BNXT_ULP_CLASS_HID_51d74] = 808,
+	[BNXT_ULP_CLASS_HID_49a26] = 809,
+	[BNXT_ULP_CLASS_HID_48abc] = 810,
+	[BNXT_ULP_CLASS_HID_5956c] = 811,
+	[BNXT_ULP_CLASS_HID_585ee] = 812,
+	[BNXT_ULP_CLASS_HID_409e4] = 813,
+	[BNXT_ULP_CLASS_HID_419a4] = 814,
+	[BNXT_ULP_CLASS_HID_51844] = 815,
+	[BNXT_ULP_CLASS_HID_508e6] = 816,
+	[BNXT_ULP_CLASS_HID_4918c] = 817,
+	[BNXT_ULP_CLASS_HID_4802e] = 818,
+	[BNXT_ULP_CLASS_HID_580ee] = 819,
+	[BNXT_ULP_CLASS_HID_590ae] = 820,
+	[BNXT_ULP_CLASS_HID_404ae] = 821,
+	[BNXT_ULP_CLASS_HID_41766] = 822,
+	[BNXT_ULP_CLASS_HID_5172e] = 823,
+	[BNXT_ULP_CLASS_HID_507a4] = 824,
+	[BNXT_ULP_CLASS_HID_48f66] = 825,
+	[BNXT_ULP_CLASS_HID_49f2e] = 826,
+	[BNXT_ULP_CLASS_HID_59fe6] = 827,
+	[BNXT_ULP_CLASS_HID_58e6c] = 828,
+	[BNXT_ULP_CLASS_HID_4126c] = 829,
+	[BNXT_ULP_CLASS_HID_4028e] = 830,
+	[BNXT_ULP_CLASS_HID_50d5e] = 831,
+	[BNXT_ULP_CLASS_HID_51d1e] = 832,
+	[BNXT_ULP_CLASS_HID_49a2c] = 833,
+	[BNXT_ULP_CLASS_HID_4954e] = 834,
+	[BNXT_ULP_CLASS_HID_5951e] = 835,
+	[BNXT_ULP_CLASS_HID_5858c] = 836,
+	[BNXT_ULP_CLASS_HID_409fe] = 837,
+	[BNXT_ULP_CLASS_HID_419ee] = 838,
+	[BNXT_ULP_CLASS_HID_519ae] = 839,
+	[BNXT_ULP_CLASS_HID_508fc] = 840,
+	[BNXT_ULP_CLASS_HID_491ee] = 841,
+	[BNXT_ULP_CLASS_HID_4802c] = 842,
+	[BNXT_ULP_CLASS_HID_580fc] = 843,
+	[BNXT_ULP_CLASS_HID_590bc] = 844,
+	[BNXT_ULP_CLASS_HID_4074c] = 845,
+	[BNXT_ULP_CLASS_HID_4170c] = 846,
+	[BNXT_ULP_CLASS_HID_5172c] = 847,
+	[BNXT_ULP_CLASS_HID_5064e] = 848,
+	[BNXT_ULP_CLASS_HID_48f0c] = 849,
+	[BNXT_ULP_CLASS_HID_49fcc] = 850,
+	[BNXT_ULP_CLASS_HID_59fec] = 851,
+	[BNXT_ULP_CLASS_HID_58e0e] = 852,
+	[BNXT_ULP_CLASS_HID_413ac] = 853,
+	[BNXT_ULP_CLASS_HID_402ee] = 854,
+	[BNXT_ULP_CLASS_HID_502ae] = 855,
+	[BNXT_ULP_CLASS_HID_512ae] = 856,
+	[BNXT_ULP_CLASS_HID_49a6c] = 857,
+	[BNXT_ULP_CLASS_HID_48aae] = 858,
+	[BNXT_ULP_CLASS_HID_58aae] = 859,
+	[BNXT_ULP_CLASS_HID_585ec] = 860,
+	[BNXT_ULP_CLASS_HID_104ae] = 861,
+	[BNXT_ULP_CLASS_HID_1108e] = 862,
+	[BNXT_ULP_CLASS_HID_140b2] = 863,
+	[BNXT_ULP_CLASS_HID_15c92] = 864,
+	[BNXT_ULP_CLASS_HID_126a0] = 865,
+	[BNXT_ULP_CLASS_HID_13280] = 866,
+	[BNXT_ULP_CLASS_HID_16d44] = 867,
+	[BNXT_ULP_CLASS_HID_17ea4] = 868,
+	[BNXT_ULP_CLASS_HID_113a4] = 869,
+	[BNXT_ULP_CLASS_HID_10e66] = 870,
+	[BNXT_ULP_CLASS_HID_15e40] = 871,
+	[BNXT_ULP_CLASS_HID_14a02] = 872,
+	[BNXT_ULP_CLASS_HID_13db6] = 873,
+	[BNXT_ULP_CLASS_HID_12870] = 874,
+	[BNXT_ULP_CLASS_HID_17852] = 875,
+	[BNXT_ULP_CLASS_HID_17414] = 876,
+	[BNXT_ULP_CLASS_HID_11978] = 877,
+	[BNXT_ULP_CLASS_HID_1153a] = 878,
+	[BNXT_ULP_CLASS_HID_145fa] = 879,
+	[BNXT_ULP_CLASS_HID_151da] = 880,
+	[BNXT_ULP_CLASS_HID_13b0a] = 881,
+	[BNXT_ULP_CLASS_HID_137c8] = 882,
+	[BNXT_ULP_CLASS_HID_167f0] = 883,
+	[BNXT_ULP_CLASS_HID_173d0] = 884,
+	[BNXT_ULP_CLASS_HID_114d0] = 885,
+	[BNXT_ULP_CLASS_HID_10092] = 886,
+	[BNXT_ULP_CLASS_HID_150f0] = 887,
+	[BNXT_ULP_CLASS_HID_14cb2] = 888,
+	[BNXT_ULP_CLASS_HID_136e2] = 889,
+	[BNXT_ULP_CLASS_HID_122a0] = 890,
+	[BNXT_ULP_CLASS_HID_17282] = 891,
+	[BNXT_ULP_CLASS_HID_16940] = 892,
+	[BNXT_ULP_CLASS_HID_11b90] = 893,
+	[BNXT_ULP_CLASS_HID_11654] = 894,
+	[BNXT_ULP_CLASS_HID_14618] = 895,
+	[BNXT_ULP_CLASS_HID_15278] = 896,
+	[BNXT_ULP_CLASS_HID_12404] = 897,
+	[BNXT_ULP_CLASS_HID_13064] = 898,
+	[BNXT_ULP_CLASS_HID_16028] = 899,
+	[BNXT_ULP_CLASS_HID_17c08] = 900,
+	[BNXT_ULP_CLASS_HID_11100] = 901,
+	[BNXT_ULP_CLASS_HID_10dc4] = 902,
+	[BNXT_ULP_CLASS_HID_15d24] = 903,
+	[BNXT_ULP_CLASS_HID_149d0] = 904,
+	[BNXT_ULP_CLASS_HID_13314] = 905,
+	[BNXT_ULP_CLASS_HID_12fd4] = 906,
+	[BNXT_ULP_CLASS_HID_17f20] = 907,
+	[BNXT_ULP_CLASS_HID_16be0] = 908,
+	[BNXT_ULP_CLASS_HID_11cd8] = 909,
+	[BNXT_ULP_CLASS_HID_10880] = 910,
+	[BNXT_ULP_CLASS_HID_158e0] = 911,
+	[BNXT_ULP_CLASS_HID_154a0] = 912,
+	[BNXT_ULP_CLASS_HID_13ed0] = 913,
+	[BNXT_ULP_CLASS_HID_12a90] = 914,
+	[BNXT_ULP_CLASS_HID_16550] = 915,
+	[BNXT_ULP_CLASS_HID_176b0] = 916,
+	[BNXT_ULP_CLASS_HID_10bb0] = 917,
+	[BNXT_ULP_CLASS_HID_10670] = 918,
+	[BNXT_ULP_CLASS_HID_15650] = 919,
+	[BNXT_ULP_CLASS_HID_14210] = 920,
+	[BNXT_ULP_CLASS_HID_13440] = 921,
+	[BNXT_ULP_CLASS_HID_12000] = 922,
+	[BNXT_ULP_CLASS_HID_17060] = 923,
+	[BNXT_ULP_CLASS_HID_16c20] = 924,
+	[BNXT_ULP_CLASS_HID_11511] = 925,
+	[BNXT_ULP_CLASS_HID_101d3] = 926,
+	[BNXT_ULP_CLASS_HID_15135] = 927,
+	[BNXT_ULP_CLASS_HID_14df7] = 928,
+	[BNXT_ULP_CLASS_HID_13723] = 929,
+	[BNXT_ULP_CLASS_HID_123e5] = 930,
+	[BNXT_ULP_CLASS_HID_173c7] = 931,
+	[BNXT_ULP_CLASS_HID_16f89] = 932,
+	[BNXT_ULP_CLASS_HID_10081] = 933,
+	[BNXT_ULP_CLASS_HID_11ce1] = 934,
+	[BNXT_ULP_CLASS_HID_14ca5] = 935,
+	[BNXT_ULP_CLASS_HID_15885] = 936,
+	[BNXT_ULP_CLASS_HID_12293] = 937,
+	[BNXT_ULP_CLASS_HID_13ef3] = 938,
+	[BNXT_ULP_CLASS_HID_16eb7] = 939,
+	[BNXT_ULP_CLASS_HID_16561] = 940,
+	[BNXT_ULP_CLASS_HID_10e59] = 941,
+	[BNXT_ULP_CLASS_HID_11bb9] = 942,
+	[BNXT_ULP_CLASS_HID_14a61] = 943,
+	[BNXT_ULP_CLASS_HID_14623] = 944,
+	[BNXT_ULP_CLASS_HID_1286b] = 945,
+	[BNXT_ULP_CLASS_HID_12411] = 946,
+	[BNXT_ULP_CLASS_HID_17473] = 947,
+	[BNXT_ULP_CLASS_HID_16031] = 948,
+	[BNXT_ULP_CLASS_HID_10531] = 949,
+	[BNXT_ULP_CLASS_HID_11111] = 950,
+	[BNXT_ULP_CLASS_HID_141d1] = 951,
+	[BNXT_ULP_CLASS_HID_15d31] = 952,
+	[BNXT_ULP_CLASS_HID_127c3] = 953,
+	[BNXT_ULP_CLASS_HID_13323] = 954,
+	[BNXT_ULP_CLASS_HID_163e3] = 955,
+	[BNXT_ULP_CLASS_HID_17fc3] = 956,
+	[BNXT_ULP_CLASS_HID_108f5] = 957,
+	[BNXT_ULP_CLASS_HID_104b9] = 958,
+	[BNXT_ULP_CLASS_HID_15499] = 959,
+	[BNXT_ULP_CLASS_HID_1435d] = 960,
+	[BNXT_ULP_CLASS_HID_12a89] = 961,
+	[BNXT_ULP_CLASS_HID_12149] = 962,
+	[BNXT_ULP_CLASS_HID_176ad] = 963,
+	[BNXT_ULP_CLASS_HID_16d6d] = 964,
+	[BNXT_ULP_CLASS_HID_10665] = 965,
+	[BNXT_ULP_CLASS_HID_11245] = 966,
+	[BNXT_ULP_CLASS_HID_14271] = 967,
+	[BNXT_ULP_CLASS_HID_15e51] = 968,
+	[BNXT_ULP_CLASS_HID_12061] = 969,
+	[BNXT_ULP_CLASS_HID_13c41] = 970,
+	[BNXT_ULP_CLASS_HID_16c05] = 971,
+	[BNXT_ULP_CLASS_HID_17865] = 972,
+	[BNXT_ULP_CLASS_HID_10d21] = 973,
+	[BNXT_ULP_CLASS_HID_11901] = 974,
+	[BNXT_ULP_CLASS_HID_149c1] = 975,
+	[BNXT_ULP_CLASS_HID_14589] = 976,
+	[BNXT_ULP_CLASS_HID_12f31] = 977,
+	[BNXT_ULP_CLASS_HID_13b11] = 978,
+	[BNXT_ULP_CLASS_HID_16bd9] = 979,
+	[BNXT_ULP_CLASS_HID_16799] = 980,
+	[BNXT_ULP_CLASS_HID_11831] = 981,
+	[BNXT_ULP_CLASS_HID_114f1] = 982,
+	[BNXT_ULP_CLASS_HID_144b1] = 983,
+	[BNXT_ULP_CLASS_HID_15091] = 984,
+	[BNXT_ULP_CLASS_HID_13ac1] = 985,
+	[BNXT_ULP_CLASS_HID_13681] = 986,
+	[BNXT_ULP_CLASS_HID_166b1] = 987,
+	[BNXT_ULP_CLASS_HID_17291] = 988,
+	[BNXT_ULP_CLASS_HID_4007d] = 989,
+	[BNXT_ULP_CLASS_HID_41041] = 990,
+	[BNXT_ULP_CLASS_HID_5100d] = 991,
+	[BNXT_ULP_CLASS_HID_50f77] = 992,
+	[BNXT_ULP_CLASS_HID_48845] = 993,
+	[BNXT_ULP_CLASS_HID_487af] = 994,
+	[BNXT_ULP_CLASS_HID_5877b] = 995,
+	[BNXT_ULP_CLASS_HID_5973f] = 996,
+	[BNXT_ULP_CLASS_HID_41c31] = 997,
+	[BNXT_ULP_CLASS_HID_40b1b] = 998,
+	[BNXT_ULP_CLASS_HID_50b67] = 999,
+	[BNXT_ULP_CLASS_HID_51b2b] = 1000,
+	[BNXT_ULP_CLASS_HID_4831f] = 1001,
+	[BNXT_ULP_CLASS_HID_49363] = 1002,
+	[BNXT_ULP_CLASS_HID_5932f] = 1003,
+	[BNXT_ULP_CLASS_HID_58211] = 1004,
+	[BNXT_ULP_CLASS_HID_4161b] = 1005,
+	[BNXT_ULP_CLASS_HID_405bd] = 1006,
+	[BNXT_ULP_CLASS_HID_50589] = 1007,
+	[BNXT_ULP_CLASS_HID_5150d] = 1008,
+	[BNXT_ULP_CLASS_HID_49e23] = 1009,
+	[BNXT_ULP_CLASS_HID_48d85] = 1010,
+	[BNXT_ULP_CLASS_HID_58d11] = 1011,
+	[BNXT_ULP_CLASS_HID_59d15] = 1012,
+	[BNXT_ULP_CLASS_HID_4012d] = 1013,
+	[BNXT_ULP_CLASS_HID_41131] = 1014,
+	[BNXT_ULP_CLASS_HID_5113d] = 1015,
+	[BNXT_ULP_CLASS_HID_50027] = 1016,
+	[BNXT_ULP_CLASS_HID_48935] = 1017,
+	[BNXT_ULP_CLASS_HID_49939] = 1018,
+	[BNXT_ULP_CLASS_HID_59905] = 1019,
+	[BNXT_ULP_CLASS_HID_5882f] = 1020,
+	[BNXT_ULP_CLASS_HID_41b99] = 1021,
+	[BNXT_ULP_CLASS_HID_40b03] = 1022,
+	[BNXT_ULP_CLASS_HID_50acf] = 1023,
+	[BNXT_ULP_CLASS_HID_51a93] = 1024,
+	[BNXT_ULP_CLASS_HID_48307] = 1025,
+	[BNXT_ULP_CLASS_HID_492cb] = 1026,
+	[BNXT_ULP_CLASS_HID_59297] = 1027,
+	[BNXT_ULP_CLASS_HID_581d9] = 1028,
+	[BNXT_ULP_CLASS_HID_41653] = 1029,
+	[BNXT_ULP_CLASS_HID_40655] = 1030,
+	[BNXT_ULP_CLASS_HID_50601] = 1031,
+	[BNXT_ULP_CLASS_HID_51545] = 1032,
+	[BNXT_ULP_CLASS_HID_49e1b] = 1033,
+	[BNXT_ULP_CLASS_HID_48e1d] = 1034,
+	[BNXT_ULP_CLASS_HID_58d49] = 1035,
+	[BNXT_ULP_CLASS_HID_59d0d] = 1036,
+	[BNXT_ULP_CLASS_HID_40115] = 1037,
+	[BNXT_ULP_CLASS_HID_41099] = 1038,
+	[BNXT_ULP_CLASS_HID_51085] = 1039,
+	[BNXT_ULP_CLASS_HID_5000f] = 1040,
+	[BNXT_ULP_CLASS_HID_4889d] = 1041,
+	[BNXT_ULP_CLASS_HID_49881] = 1042,
+	[BNXT_ULP_CLASS_HID_5980d] = 1043,
+	[BNXT_ULP_CLASS_HID_59797] = 1044,
+	[BNXT_ULP_CLASS_HID_41c09] = 1045,
+	[BNXT_ULP_CLASS_HID_40c13] = 1046,
+	[BNXT_ULP_CLASS_HID_50b1f] = 1047,
+	[BNXT_ULP_CLASS_HID_51b03] = 1048,
+	[BNXT_ULP_CLASS_HID_48417] = 1049,
+	[BNXT_ULP_CLASS_HID_4931b] = 1050,
+	[BNXT_ULP_CLASS_HID_59307] = 1051,
+	[BNXT_ULP_CLASS_HID_58309] = 1052,
+	[BNXT_ULP_CLASS_HID_4160f] = 1053,
+	[BNXT_ULP_CLASS_HID_40561] = 1054,
+	[BNXT_ULP_CLASS_HID_5052d] = 1055,
+	[BNXT_ULP_CLASS_HID_51501] = 1056,
+	[BNXT_ULP_CLASS_HID_49dc7] = 1057,
+	[BNXT_ULP_CLASS_HID_48d29] = 1058,
+	[BNXT_ULP_CLASS_HID_58d05] = 1059,
+	[BNXT_ULP_CLASS_HID_59cc9] = 1060,
+	[BNXT_ULP_CLASS_HID_40161] = 1061,
+	[BNXT_ULP_CLASS_HID_41125] = 1062,
+	[BNXT_ULP_CLASS_HID_51061] = 1063,
+	[BNXT_ULP_CLASS_HID_5004b] = 1064,
+	[BNXT_ULP_CLASS_HID_48929] = 1065,
+	[BNXT_ULP_CLASS_HID_4986d] = 1066,
+	[BNXT_ULP_CLASS_HID_59829] = 1067,
+	[BNXT_ULP_CLASS_HID_58823] = 1068,
+	[BNXT_ULP_CLASS_HID_41ba5] = 1069,
+	[BNXT_ULP_CLASS_HID_40b0f] = 1070,
+	[BNXT_ULP_CLASS_HID_50b0b] = 1071,
+	[BNXT_ULP_CLASS_HID_51a8f] = 1072,
+	[BNXT_ULP_CLASS_HID_48303] = 1073,
+	[BNXT_ULP_CLASS_HID_49307] = 1074,
+	[BNXT_ULP_CLASS_HID_592a3] = 1075,
+	[BNXT_ULP_CLASS_HID_58205] = 1076,
+	[BNXT_ULP_CLASS_HID_4172f] = 1077,
+	[BNXT_ULP_CLASS_HID_40621] = 1078,
+	[BNXT_ULP_CLASS_HID_5062d] = 1079,
+	[BNXT_ULP_CLASS_HID_51621] = 1080,
+	[BNXT_ULP_CLASS_HID_49f07] = 1081,
+	[BNXT_ULP_CLASS_HID_48e29] = 1082,
+	[BNXT_ULP_CLASS_HID_58e25] = 1083,
+	[BNXT_ULP_CLASS_HID_59d29] = 1084,
+	[BNXT_ULP_CLASS_HID_400c9] = 1085,
+	[BNXT_ULP_CLASS_HID_4108d] = 1086,
+	[BNXT_ULP_CLASS_HID_51049] = 1087,
+	[BNXT_ULP_CLASS_HID_50fc3] = 1088,
+	[BNXT_ULP_CLASS_HID_48881] = 1089,
+	[BNXT_ULP_CLASS_HID_487cb] = 1090,
+	[BNXT_ULP_CLASS_HID_587c7] = 1091,
+	[BNXT_ULP_CLASS_HID_5978b] = 1092,
+	[BNXT_ULP_CLASS_HID_41c4d] = 1093,
+	[BNXT_ULP_CLASS_HID_40b47] = 1094,
+	[BNXT_ULP_CLASS_HID_50b03] = 1095,
+	[BNXT_ULP_CLASS_HID_51b47] = 1096,
+	[BNXT_ULP_CLASS_HID_4834b] = 1097,
+	[BNXT_ULP_CLASS_HID_4930f] = 1098,
+	[BNXT_ULP_CLASS_HID_5934b] = 1099,
+	[BNXT_ULP_CLASS_HID_5824d] = 1100,
+	[BNXT_ULP_CLASS_HID_41687] = 1101,
+	[BNXT_ULP_CLASS_HID_40609] = 1102,
+	[BNXT_ULP_CLASS_HID_50585] = 1103,
+	[BNXT_ULP_CLASS_HID_51589] = 1104,
+	[BNXT_ULP_CLASS_HID_49e0f] = 1105,
+	[BNXT_ULP_CLASS_HID_48d81] = 1106,
+	[BNXT_ULP_CLASS_HID_58d8d] = 1107,
+	[BNXT_ULP_CLASS_HID_59d01] = 1108,
+	[BNXT_ULP_CLASS_HID_40109] = 1109,
+	[BNXT_ULP_CLASS_HID_4110d] = 1110,
+	[BNXT_ULP_CLASS_HID_51109] = 1111,
+	[BNXT_ULP_CLASS_HID_50003] = 1112,
+	[BNXT_ULP_CLASS_HID_48901] = 1113,
+	[BNXT_ULP_CLASS_HID_49905] = 1114,
+	[BNXT_ULP_CLASS_HID_59901] = 1115,
+	[BNXT_ULP_CLASS_HID_5880b] = 1116,
+	[BNXT_ULP_CLASS_HID_10619] = 1117,
+	[BNXT_ULP_CLASS_HID_11239] = 1118,
+	[BNXT_ULP_CLASS_HID_14205] = 1119,
+	[BNXT_ULP_CLASS_HID_15e25] = 1120,
+	[BNXT_ULP_CLASS_HID_12417] = 1121,
+	[BNXT_ULP_CLASS_HID_13037] = 1122,
+	[BNXT_ULP_CLASS_HID_16ff3] = 1123,
+	[BNXT_ULP_CLASS_HID_17c13] = 1124,
+	[BNXT_ULP_CLASS_HID_1111d] = 1125,
+	[BNXT_ULP_CLASS_HID_10cdb] = 1126,
+	[BNXT_ULP_CLASS_HID_15d19] = 1127,
+	[BNXT_ULP_CLASS_HID_148c7] = 1128,
+	[BNXT_ULP_CLASS_HID_13f0b] = 1129,
+	[BNXT_ULP_CLASS_HID_12ac9] = 1130,
+	[BNXT_ULP_CLASS_HID_17b17] = 1131,
+	[BNXT_ULP_CLASS_HID_176d5] = 1132,
+	[BNXT_ULP_CLASS_HID_10bab] = 1133,
+	[BNXT_ULP_CLASS_HID_10769] = 1134,
+	[BNXT_ULP_CLASS_HID_15787] = 1135,
+	[BNXT_ULP_CLASS_HID_14345] = 1136,
+	[BNXT_ULP_CLASS_HID_12989] = 1137,
+	[BNXT_ULP_CLASS_HID_12567] = 1138,
+	[BNXT_ULP_CLASS_HID_17585] = 1139,
+	[BNXT_ULP_CLASS_HID_16143] = 1140,
+	[BNXT_ULP_CLASS_HID_1064d] = 1141,
+	[BNXT_ULP_CLASS_HID_1128d] = 1142,
+	[BNXT_ULP_CLASS_HID_14249] = 1143,
+	[BNXT_ULP_CLASS_HID_15e49] = 1144,
+	[BNXT_ULP_CLASS_HID_1244b] = 1145,
+	[BNXT_ULP_CLASS_HID_1304b] = 1146,
+	[BNXT_ULP_CLASS_HID_16047] = 1147,
+	[BNXT_ULP_CLASS_HID_17c47] = 1148,
+	[BNXT_ULP_CLASS_HID_11113] = 1149,
+	[BNXT_ULP_CLASS_HID_10cd1] = 1150,
+	[BNXT_ULP_CLASS_HID_15cf7] = 1151,
+	[BNXT_ULP_CLASS_HID_148b5] = 1152,
+	[BNXT_ULP_CLASS_HID_13f01] = 1153,
+	[BNXT_ULP_CLASS_HID_12ac7] = 1154,
+	[BNXT_ULP_CLASS_HID_17ae5] = 1155,
+	[BNXT_ULP_CLASS_HID_176a3] = 1156,
+	[BNXT_ULP_CLASS_HID_10bd5] = 1157,
+	[BNXT_ULP_CLASS_HID_10793] = 1158,
+	[BNXT_ULP_CLASS_HID_15791] = 1159,
+	[BNXT_ULP_CLASS_HID_14357] = 1160,
+	[BNXT_ULP_CLASS_HID_129c3] = 1161,
+	[BNXT_ULP_CLASS_HID_12581] = 1162,
+	[BNXT_ULP_CLASS_HID_17587] = 1163,
+	[BNXT_ULP_CLASS_HID_16145] = 1164,
+	[BNXT_ULP_CLASS_HID_10643] = 1165,
+	[BNXT_ULP_CLASS_HID_11263] = 1166,
+	[BNXT_ULP_CLASS_HID_14227] = 1167,
+	[BNXT_ULP_CLASS_HID_15e47] = 1168,
+	[BNXT_ULP_CLASS_HID_12421] = 1169,
+	[BNXT_ULP_CLASS_HID_13041] = 1170,
+	[BNXT_ULP_CLASS_HID_16005] = 1171,
+	[BNXT_ULP_CLASS_HID_17c25] = 1172,
+	[BNXT_ULP_CLASS_HID_11147] = 1173,
+	[BNXT_ULP_CLASS_HID_10d05] = 1174,
+	[BNXT_ULP_CLASS_HID_15d43] = 1175,
+	[BNXT_ULP_CLASS_HID_14901] = 1176,
+	[BNXT_ULP_CLASS_HID_13f45] = 1177,
+	[BNXT_ULP_CLASS_HID_12b03] = 1178,
+	[BNXT_ULP_CLASS_HID_17b01] = 1179,
+	[BNXT_ULP_CLASS_HID_176c7] = 1180,
+	[BNXT_ULP_CLASS_HID_11bcf] = 1181,
+	[BNXT_ULP_CLASS_HID_1178d] = 1182,
+	[BNXT_ULP_CLASS_HID_1474d] = 1183,
+	[BNXT_ULP_CLASS_HID_1536d] = 1184,
+	[BNXT_ULP_CLASS_HID_139bd] = 1185,
+	[BNXT_ULP_CLASS_HID_1357f] = 1186,
+	[BNXT_ULP_CLASS_HID_16547] = 1187,
+	[BNXT_ULP_CLASS_HID_17167] = 1188,
+	[BNXT_ULP_CLASS_HID_11685] = 1189,
+	[BNXT_ULP_CLASS_HID_1024f] = 1190,
+	[BNXT_ULP_CLASS_HID_1524d] = 1191,
+	[BNXT_ULP_CLASS_HID_14e0f] = 1192,
+	[BNXT_ULP_CLASS_HID_1345f] = 1193,
+	[BNXT_ULP_CLASS_HID_1201d] = 1194,
+	[BNXT_ULP_CLASS_HID_1705f] = 1195,
+	[BNXT_ULP_CLASS_HID_16c1d] = 1196,
+	[BNXT_ULP_CLASS_HID_100ef] = 1197,
+	[BNXT_ULP_CLASS_HID_11d0f] = 1198,
+	[BNXT_ULP_CLASS_HID_14ccf] = 1199,
+	[BNXT_ULP_CLASS_HID_158ef] = 1200,
+	[BNXT_ULP_CLASS_HID_12eed] = 1201,
+	[BNXT_ULP_CLASS_HID_13b0d] = 1202,
+	[BNXT_ULP_CLASS_HID_16acd] = 1203,
+	[BNXT_ULP_CLASS_HID_16687] = 1204,
+	[BNXT_ULP_CLASS_HID_11c07] = 1205,
+	[BNXT_ULP_CLASS_HID_117c5] = 1206,
+	[BNXT_ULP_CLASS_HID_1478d] = 1207,
+	[BNXT_ULP_CLASS_HID_1538d] = 1208,
+	[BNXT_ULP_CLASS_HID_13a05] = 1209,
+	[BNXT_ULP_CLASS_HID_135cf] = 1210,
+	[BNXT_ULP_CLASS_HID_1658f] = 1211,
+	[BNXT_ULP_CLASS_HID_1718f] = 1212,
+	[BNXT_ULP_CLASS_HID_11667] = 1213,
+	[BNXT_ULP_CLASS_HID_10225] = 1214,
+	[BNXT_ULP_CLASS_HID_15247] = 1215,
+	[BNXT_ULP_CLASS_HID_14e05] = 1216,
+	[BNXT_ULP_CLASS_HID_13455] = 1217,
+	[BNXT_ULP_CLASS_HID_12017] = 1218,
+	[BNXT_ULP_CLASS_HID_17035] = 1219,
+	[BNXT_ULP_CLASS_HID_16bf7] = 1220,
+	[BNXT_ULP_CLASS_HID_10115] = 1221,
+	[BNXT_ULP_CLASS_HID_11d15] = 1222,
+	[BNXT_ULP_CLASS_HID_14d05] = 1223,
+	[BNXT_ULP_CLASS_HID_15905] = 1224,
+	[BNXT_ULP_CLASS_HID_12f17] = 1225,
+	[BNXT_ULP_CLASS_HID_13b17] = 1226,
+	[BNXT_ULP_CLASS_HID_16ad7] = 1227,
+	[BNXT_ULP_CLASS_HID_16695] = 1228,
+	[BNXT_ULP_CLASS_HID_11be5] = 1229,
+	[BNXT_ULP_CLASS_HID_117a7] = 1230,
+	[BNXT_ULP_CLASS_HID_14767] = 1231,
+	[BNXT_ULP_CLASS_HID_15387] = 1232,
+	[BNXT_ULP_CLASS_HID_139e7] = 1233,
+	[BNXT_ULP_CLASS_HID_135a5] = 1234,
+	[BNXT_ULP_CLASS_HID_16565] = 1235,
+	[BNXT_ULP_CLASS_HID_17185] = 1236,
+	[BNXT_ULP_CLASS_HID_11687] = 1237,
+	[BNXT_ULP_CLASS_HID_10245] = 1238,
+	[BNXT_ULP_CLASS_HID_15287] = 1239,
+	[BNXT_ULP_CLASS_HID_14e45] = 1240,
+	[BNXT_ULP_CLASS_HID_13485] = 1241,
+	[BNXT_ULP_CLASS_HID_12047] = 1242,
+	[BNXT_ULP_CLASS_HID_17085] = 1243,
+	[BNXT_ULP_CLASS_HID_16c47] = 1244,
+	[BNXT_ULP_CLASS_HID_400f4] = 1245,
+	[BNXT_ULP_CLASS_HID_410c8] = 1246,
+	[BNXT_ULP_CLASS_HID_51084] = 1247,
+	[BNXT_ULP_CLASS_HID_50ffe] = 1248,
+	[BNXT_ULP_CLASS_HID_488cc] = 1249,
+	[BNXT_ULP_CLASS_HID_48726] = 1250,
+	[BNXT_ULP_CLASS_HID_587f2] = 1251,
+	[BNXT_ULP_CLASS_HID_597b6] = 1252,
+	[BNXT_ULP_CLASS_HID_41b10] = 1253,
+	[BNXT_ULP_CLASS_HID_40b8a] = 1254,
+	[BNXT_ULP_CLASS_HID_50a46] = 1255,
+	[BNXT_ULP_CLASS_HID_51a1a] = 1256,
+	[BNXT_ULP_CLASS_HID_4838e] = 1257,
+	[BNXT_ULP_CLASS_HID_49242] = 1258,
+	[BNXT_ULP_CLASS_HID_5921e] = 1259,
+	[BNXT_ULP_CLASS_HID_58150] = 1260,
+	[BNXT_ULP_CLASS_HID_41686] = 1261,
+	[BNXT_ULP_CLASS_HID_405e8] = 1262,
+	[BNXT_ULP_CLASS_HID_505a4] = 1263,
+	[BNXT_ULP_CLASS_HID_51588] = 1264,
+	[BNXT_ULP_CLASS_HID_49d4e] = 1265,
+	[BNXT_ULP_CLASS_HID_48da0] = 1266,
+	[BNXT_ULP_CLASS_HID_58d8c] = 1267,
+	[BNXT_ULP_CLASS_HID_59c40] = 1268,
+	[BNXT_ULP_CLASS_HID_40040] = 1269,
+	[BNXT_ULP_CLASS_HID_41004] = 1270,
+	[BNXT_ULP_CLASS_HID_510c0] = 1271,
+	[BNXT_ULP_CLASS_HID_50f4a] = 1272,
+	[BNXT_ULP_CLASS_HID_48808] = 1273,
+	[BNXT_ULP_CLASS_HID_48742] = 1274,
+	[BNXT_ULP_CLASS_HID_5874e] = 1275,
+	[BNXT_ULP_CLASS_HID_59702] = 1276,
+	[BNXT_ULP_CLASS_HID_41bfe] = 1277,
+	[BNXT_ULP_CLASS_HID_40a58] = 1278,
+	[BNXT_ULP_CLASS_HID_50a2c] = 1279,
+	[BNXT_ULP_CLASS_HID_51ae8] = 1280,
+	[BNXT_ULP_CLASS_HID_4825c] = 1281,
+	[BNXT_ULP_CLASS_HID_49228] = 1282,
+	[BNXT_ULP_CLASS_HID_592ec] = 1283,
+	[BNXT_ULP_CLASS_HID_5815e] = 1284,
+	[BNXT_ULP_CLASS_HID_41698] = 1285,
+	[BNXT_ULP_CLASS_HID_4051a] = 1286,
+	[BNXT_ULP_CLASS_HID_505ce] = 1287,
+	[BNXT_ULP_CLASS_HID_5158a] = 1288,
+	[BNXT_ULP_CLASS_HID_49d58] = 1289,
+	[BNXT_ULP_CLASS_HID_48dca] = 1290,
+	[BNXT_ULP_CLASS_HID_58d8e] = 1291,
+	[BNXT_ULP_CLASS_HID_59c5a] = 1292,
+	[BNXT_ULP_CLASS_HID_4002e] = 1293,
+	[BNXT_ULP_CLASS_HID_410ea] = 1294,
+	[BNXT_ULP_CLASS_HID_510ae] = 1295,
+	[BNXT_ULP_CLASS_HID_50f08] = 1296,
+	[BNXT_ULP_CLASS_HID_488ee] = 1297,
+	[BNXT_ULP_CLASS_HID_48748] = 1298,
+	[BNXT_ULP_CLASS_HID_5870c] = 1299,
+	[BNXT_ULP_CLASS_HID_597e8] = 1300,
+	[BNXT_ULP_CLASS_HID_41b4a] = 1301,
+	[BNXT_ULP_CLASS_HID_40b8c] = 1302,
+	[BNXT_ULP_CLASS_HID_50a48] = 1303,
+	[BNXT_ULP_CLASS_HID_51a0c] = 1304,
+	[BNXT_ULP_CLASS_HID_48388] = 1305,
+	[BNXT_ULP_CLASS_HID_4924c] = 1306,
+	[BNXT_ULP_CLASS_HID_59208] = 1307,
+	[BNXT_ULP_CLASS_HID_5828a] = 1308,
+	[BNXT_ULP_CLASS_HID_40540] = 1309,
+	[BNXT_ULP_CLASS_HID_41500] = 1310,
+	[BNXT_ULP_CLASS_HID_515d0] = 1311,
+	[BNXT_ULP_CLASS_HID_5044a] = 1312,
+	[BNXT_ULP_CLASS_HID_48d18] = 1313,
+	[BNXT_ULP_CLASS_HID_49dd8] = 1314,
+	[BNXT_ULP_CLASS_HID_59da8] = 1315,
+	[BNXT_ULP_CLASS_HID_58c02] = 1316,
+	[BNXT_ULP_CLASS_HID_41048] = 1317,
+	[BNXT_ULP_CLASS_HID_400c2] = 1318,
+	[BNXT_ULP_CLASS_HID_50092] = 1319,
+	[BNXT_ULP_CLASS_HID_51f52] = 1320,
+	[BNXT_ULP_CLASS_HID_49800] = 1321,
+	[BNXT_ULP_CLASS_HID_4889a] = 1322,
+	[BNXT_ULP_CLASS_HID_5974a] = 1323,
+	[BNXT_ULP_CLASS_HID_587c8] = 1324,
+	[BNXT_ULP_CLASS_HID_40bc2] = 1325,
+	[BNXT_ULP_CLASS_HID_41b82] = 1326,
+	[BNXT_ULP_CLASS_HID_51a62] = 1327,
+	[BNXT_ULP_CLASS_HID_50ac0] = 1328,
+	[BNXT_ULP_CLASS_HID_493aa] = 1329,
+	[BNXT_ULP_CLASS_HID_48208] = 1330,
+	[BNXT_ULP_CLASS_HID_582c8] = 1331,
+	[BNXT_ULP_CLASS_HID_59288] = 1332,
+	[BNXT_ULP_CLASS_HID_40688] = 1333,
+	[BNXT_ULP_CLASS_HID_41540] = 1334,
+	[BNXT_ULP_CLASS_HID_51508] = 1335,
+	[BNXT_ULP_CLASS_HID_50582] = 1336,
+	[BNXT_ULP_CLASS_HID_48d40] = 1337,
+	[BNXT_ULP_CLASS_HID_49d08] = 1338,
+	[BNXT_ULP_CLASS_HID_59dc0] = 1339,
+	[BNXT_ULP_CLASS_HID_58c4a] = 1340,
+	[BNXT_ULP_CLASS_HID_4104a] = 1341,
+	[BNXT_ULP_CLASS_HID_400a8] = 1342,
+	[BNXT_ULP_CLASS_HID_50f78] = 1343,
+	[BNXT_ULP_CLASS_HID_51f38] = 1344,
+	[BNXT_ULP_CLASS_HID_4980a] = 1345,
+	[BNXT_ULP_CLASS_HID_49768] = 1346,
+	[BNXT_ULP_CLASS_HID_59738] = 1347,
+	[BNXT_ULP_CLASS_HID_587aa] = 1348,
+	[BNXT_ULP_CLASS_HID_40bd8] = 1349,
+	[BNXT_ULP_CLASS_HID_41bc8] = 1350,
+	[BNXT_ULP_CLASS_HID_51b88] = 1351,
+	[BNXT_ULP_CLASS_HID_50ada] = 1352,
+	[BNXT_ULP_CLASS_HID_493c8] = 1353,
+	[BNXT_ULP_CLASS_HID_4820a] = 1354,
+	[BNXT_ULP_CLASS_HID_582da] = 1355,
+	[BNXT_ULP_CLASS_HID_5929a] = 1356,
+	[BNXT_ULP_CLASS_HID_4056a] = 1357,
+	[BNXT_ULP_CLASS_HID_4152a] = 1358,
+	[BNXT_ULP_CLASS_HID_5150a] = 1359,
+	[BNXT_ULP_CLASS_HID_50468] = 1360,
+	[BNXT_ULP_CLASS_HID_48d2a] = 1361,
+	[BNXT_ULP_CLASS_HID_49dea] = 1362,
+	[BNXT_ULP_CLASS_HID_59dca] = 1363,
+	[BNXT_ULP_CLASS_HID_58c28] = 1364,
+	[BNXT_ULP_CLASS_HID_4118a] = 1365,
+	[BNXT_ULP_CLASS_HID_400c8] = 1366,
+	[BNXT_ULP_CLASS_HID_50088] = 1367,
+	[BNXT_ULP_CLASS_HID_51088] = 1368,
+	[BNXT_ULP_CLASS_HID_4984a] = 1369,
+	[BNXT_ULP_CLASS_HID_48888] = 1370,
+	[BNXT_ULP_CLASS_HID_58888] = 1371,
+	[BNXT_ULP_CLASS_HID_587ca] = 1372,
+	[BNXT_ULP_CLASS_HID_10690] = 1373,
+	[BNXT_ULP_CLASS_HID_112b0] = 1374,
+	[BNXT_ULP_CLASS_HID_1428c] = 1375,
+	[BNXT_ULP_CLASS_HID_15eac] = 1376,
+	[BNXT_ULP_CLASS_HID_1249e] = 1377,
+	[BNXT_ULP_CLASS_HID_130be] = 1378,
+	[BNXT_ULP_CLASS_HID_16f7a] = 1379,
+	[BNXT_ULP_CLASS_HID_17c9a] = 1380,
+	[BNXT_ULP_CLASS_HID_1119a] = 1381,
+	[BNXT_ULP_CLASS_HID_10c58] = 1382,
+	[BNXT_ULP_CLASS_HID_15c7e] = 1383,
+	[BNXT_ULP_CLASS_HID_1483c] = 1384,
+	[BNXT_ULP_CLASS_HID_13f88] = 1385,
+	[BNXT_ULP_CLASS_HID_12a4e] = 1386,
+	[BNXT_ULP_CLASS_HID_17a6c] = 1387,
+	[BNXT_ULP_CLASS_HID_1762a] = 1388,
+	[BNXT_ULP_CLASS_HID_11b46] = 1389,
+	[BNXT_ULP_CLASS_HID_11704] = 1390,
+	[BNXT_ULP_CLASS_HID_147c4] = 1391,
+	[BNXT_ULP_CLASS_HID_153e4] = 1392,
+	[BNXT_ULP_CLASS_HID_13934] = 1393,
+	[BNXT_ULP_CLASS_HID_135f6] = 1394,
+	[BNXT_ULP_CLASS_HID_165ce] = 1395,
+	[BNXT_ULP_CLASS_HID_171ee] = 1396,
+	[BNXT_ULP_CLASS_HID_116ee] = 1397,
+	[BNXT_ULP_CLASS_HID_102ac] = 1398,
+	[BNXT_ULP_CLASS_HID_152ce] = 1399,
+	[BNXT_ULP_CLASS_HID_14e8c] = 1400,
+	[BNXT_ULP_CLASS_HID_134dc] = 1401,
+	[BNXT_ULP_CLASS_HID_1209e] = 1402,
+	[BNXT_ULP_CLASS_HID_170bc] = 1403,
+	[BNXT_ULP_CLASS_HID_16b7e] = 1404,
+	[BNXT_ULP_CLASS_HID_119ae] = 1405,
+	[BNXT_ULP_CLASS_HID_1146a] = 1406,
+	[BNXT_ULP_CLASS_HID_14426] = 1407,
+	[BNXT_ULP_CLASS_HID_15046] = 1408,
+	[BNXT_ULP_CLASS_HID_1263a] = 1409,
+	[BNXT_ULP_CLASS_HID_1325a] = 1410,
+	[BNXT_ULP_CLASS_HID_16216] = 1411,
+	[BNXT_ULP_CLASS_HID_17e36] = 1412,
+	[BNXT_ULP_CLASS_HID_1133e] = 1413,
+	[BNXT_ULP_CLASS_HID_10ffa] = 1414,
+	[BNXT_ULP_CLASS_HID_15f1a] = 1415,
+	[BNXT_ULP_CLASS_HID_14bee] = 1416,
+	[BNXT_ULP_CLASS_HID_1312a] = 1417,
+	[BNXT_ULP_CLASS_HID_12dea] = 1418,
+	[BNXT_ULP_CLASS_HID_17d1e] = 1419,
+	[BNXT_ULP_CLASS_HID_169de] = 1420,
+	[BNXT_ULP_CLASS_HID_11ee6] = 1421,
+	[BNXT_ULP_CLASS_HID_10abe] = 1422,
+	[BNXT_ULP_CLASS_HID_15ade] = 1423,
+	[BNXT_ULP_CLASS_HID_1569e] = 1424,
+	[BNXT_ULP_CLASS_HID_13cee] = 1425,
+	[BNXT_ULP_CLASS_HID_128ae] = 1426,
+	[BNXT_ULP_CLASS_HID_1676e] = 1427,
+	[BNXT_ULP_CLASS_HID_1748e] = 1428,
+	[BNXT_ULP_CLASS_HID_1098e] = 1429,
+	[BNXT_ULP_CLASS_HID_1044e] = 1430,
+	[BNXT_ULP_CLASS_HID_1546e] = 1431,
+	[BNXT_ULP_CLASS_HID_1402e] = 1432,
+	[BNXT_ULP_CLASS_HID_1367e] = 1433,
+	[BNXT_ULP_CLASS_HID_1223e] = 1434,
+	[BNXT_ULP_CLASS_HID_1725e] = 1435,
+	[BNXT_ULP_CLASS_HID_16e1e] = 1436,
+	[BNXT_ULP_CLASS_HID_1172f] = 1437,
+	[BNXT_ULP_CLASS_HID_103ed] = 1438,
+	[BNXT_ULP_CLASS_HID_1530b] = 1439,
+	[BNXT_ULP_CLASS_HID_14fc9] = 1440,
+	[BNXT_ULP_CLASS_HID_1351d] = 1441,
+	[BNXT_ULP_CLASS_HID_121db] = 1442,
+	[BNXT_ULP_CLASS_HID_171f9] = 1443,
+	[BNXT_ULP_CLASS_HID_16db7] = 1444,
+	[BNXT_ULP_CLASS_HID_102bf] = 1445,
+	[BNXT_ULP_CLASS_HID_11edf] = 1446,
+	[BNXT_ULP_CLASS_HID_14e9b] = 1447,
+	[BNXT_ULP_CLASS_HID_15abb] = 1448,
+	[BNXT_ULP_CLASS_HID_120ad] = 1449,
+	[BNXT_ULP_CLASS_HID_13ccd] = 1450,
+	[BNXT_ULP_CLASS_HID_16c89] = 1451,
+	[BNXT_ULP_CLASS_HID_1675f] = 1452,
+	[BNXT_ULP_CLASS_HID_10c67] = 1453,
+	[BNXT_ULP_CLASS_HID_11987] = 1454,
+	[BNXT_ULP_CLASS_HID_1485f] = 1455,
+	[BNXT_ULP_CLASS_HID_1441d] = 1456,
+	[BNXT_ULP_CLASS_HID_12a55] = 1457,
+	[BNXT_ULP_CLASS_HID_1262f] = 1458,
+	[BNXT_ULP_CLASS_HID_1764d] = 1459,
+	[BNXT_ULP_CLASS_HID_1620f] = 1460,
+	[BNXT_ULP_CLASS_HID_1070f] = 1461,
+	[BNXT_ULP_CLASS_HID_1132f] = 1462,
+	[BNXT_ULP_CLASS_HID_143ef] = 1463,
+	[BNXT_ULP_CLASS_HID_15f0f] = 1464,
+	[BNXT_ULP_CLASS_HID_125fd] = 1465,
+	[BNXT_ULP_CLASS_HID_1311d] = 1466,
+	[BNXT_ULP_CLASS_HID_161dd] = 1467,
+	[BNXT_ULP_CLASS_HID_17dfd] = 1468,
+	[BNXT_ULP_CLASS_HID_10acb] = 1469,
+	[BNXT_ULP_CLASS_HID_10687] = 1470,
+	[BNXT_ULP_CLASS_HID_156a7] = 1471,
+	[BNXT_ULP_CLASS_HID_14163] = 1472,
+	[BNXT_ULP_CLASS_HID_128b7] = 1473,
+	[BNXT_ULP_CLASS_HID_12377] = 1474,
+	[BNXT_ULP_CLASS_HID_17493] = 1475,
+	[BNXT_ULP_CLASS_HID_16f53] = 1476,
+	[BNXT_ULP_CLASS_HID_1045b] = 1477,
+	[BNXT_ULP_CLASS_HID_1107b] = 1478,
+	[BNXT_ULP_CLASS_HID_1404f] = 1479,
+	[BNXT_ULP_CLASS_HID_15c6f] = 1480,
+	[BNXT_ULP_CLASS_HID_1225f] = 1481,
+	[BNXT_ULP_CLASS_HID_13e7f] = 1482,
+	[BNXT_ULP_CLASS_HID_16e3b] = 1483,
+	[BNXT_ULP_CLASS_HID_17a5b] = 1484,
+	[BNXT_ULP_CLASS_HID_10f1f] = 1485,
+	[BNXT_ULP_CLASS_HID_11b3f] = 1486,
+	[BNXT_ULP_CLASS_HID_14bff] = 1487,
+	[BNXT_ULP_CLASS_HID_147b7] = 1488,
+	[BNXT_ULP_CLASS_HID_12d0f] = 1489,
+	[BNXT_ULP_CLASS_HID_1392f] = 1490,
+	[BNXT_ULP_CLASS_HID_169e7] = 1491,
+	[BNXT_ULP_CLASS_HID_165a7] = 1492,
+	[BNXT_ULP_CLASS_HID_11a0f] = 1493,
+	[BNXT_ULP_CLASS_HID_116cf] = 1494,
+	[BNXT_ULP_CLASS_HID_1468f] = 1495,
+	[BNXT_ULP_CLASS_HID_152af] = 1496,
+	[BNXT_ULP_CLASS_HID_138ff] = 1497,
+	[BNXT_ULP_CLASS_HID_134bf] = 1498,
+	[BNXT_ULP_CLASS_HID_1648f] = 1499,
+	[BNXT_ULP_CLASS_HID_170af] = 1500,
+	[BNXT_ULP_CLASS_HID_40c38] = 1501,
+	[BNXT_ULP_CLASS_HID_41c04] = 1502,
+	[BNXT_ULP_CLASS_HID_51c48] = 1503,
+	[BNXT_ULP_CLASS_HID_50332] = 1504,
+	[BNXT_ULP_CLASS_HID_48400] = 1505,
+	[BNXT_ULP_CLASS_HID_48bea] = 1506,
+	[BNXT_ULP_CLASS_HID_58b3e] = 1507,
+	[BNXT_ULP_CLASS_HID_59b7a] = 1508,
+	[BNXT_ULP_CLASS_HID_417dc] = 1509,
+	[BNXT_ULP_CLASS_HID_40746] = 1510,
+	[BNXT_ULP_CLASS_HID_5068a] = 1511,
+	[BNXT_ULP_CLASS_HID_516d6] = 1512,
+	[BNXT_ULP_CLASS_HID_48f42] = 1513,
+	[BNXT_ULP_CLASS_HID_49e8e] = 1514,
+	[BNXT_ULP_CLASS_HID_59ed2] = 1515,
+	[BNXT_ULP_CLASS_HID_58d9c] = 1516,
+	[BNXT_ULP_CLASS_HID_41a4a] = 1517,
+	[BNXT_ULP_CLASS_HID_40924] = 1518,
+	[BNXT_ULP_CLASS_HID_50968] = 1519,
+	[BNXT_ULP_CLASS_HID_51944] = 1520,
+	[BNXT_ULP_CLASS_HID_49182] = 1521,
+	[BNXT_ULP_CLASS_HID_4816c] = 1522,
+	[BNXT_ULP_CLASS_HID_58140] = 1523,
+	[BNXT_ULP_CLASS_HID_5908c] = 1524,
+	[BNXT_ULP_CLASS_HID_40c8c] = 1525,
+	[BNXT_ULP_CLASS_HID_41cc8] = 1526,
+	[BNXT_ULP_CLASS_HID_51c0c] = 1527,
+	[BNXT_ULP_CLASS_HID_50386] = 1528,
+	[BNXT_ULP_CLASS_HID_484c4] = 1529,
+	[BNXT_ULP_CLASS_HID_48b8e] = 1530,
+	[BNXT_ULP_CLASS_HID_58b82] = 1531,
+	[BNXT_ULP_CLASS_HID_59bce] = 1532,
+	[BNXT_ULP_CLASS_HID_10a54] = 1533,
+	[BNXT_ULP_CLASS_HID_11e74] = 1534,
+	[BNXT_ULP_CLASS_HID_14e48] = 1535,
+	[BNXT_ULP_CLASS_HID_15268] = 1536,
+	[BNXT_ULP_CLASS_HID_1285a] = 1537,
+	[BNXT_ULP_CLASS_HID_13c7a] = 1538,
+	[BNXT_ULP_CLASS_HID_163be] = 1539,
+	[BNXT_ULP_CLASS_HID_1705e] = 1540,
+	[BNXT_ULP_CLASS_HID_11d5e] = 1541,
+	[BNXT_ULP_CLASS_HID_1009c] = 1542,
+	[BNXT_ULP_CLASS_HID_150ba] = 1543,
+	[BNXT_ULP_CLASS_HID_144f8] = 1544,
+	[BNXT_ULP_CLASS_HID_1334c] = 1545,
+	[BNXT_ULP_CLASS_HID_1268a] = 1546,
+	[BNXT_ULP_CLASS_HID_176a8] = 1547,
+	[BNXT_ULP_CLASS_HID_17aee] = 1548,
+	[BNXT_ULP_CLASS_HID_11782] = 1549,
+	[BNXT_ULP_CLASS_HID_11bc0] = 1550,
+	[BNXT_ULP_CLASS_HID_14b00] = 1551,
+	[BNXT_ULP_CLASS_HID_15f20] = 1552,
+	[BNXT_ULP_CLASS_HID_135f0] = 1553,
+	[BNXT_ULP_CLASS_HID_13932] = 1554,
+	[BNXT_ULP_CLASS_HID_1690a] = 1555,
+	[BNXT_ULP_CLASS_HID_17d2a] = 1556,
+	[BNXT_ULP_CLASS_HID_11a2a] = 1557,
+	[BNXT_ULP_CLASS_HID_10e68] = 1558,
+	[BNXT_ULP_CLASS_HID_15e0a] = 1559,
+	[BNXT_ULP_CLASS_HID_14248] = 1560,
+	[BNXT_ULP_CLASS_HID_13818] = 1561,
+	[BNXT_ULP_CLASS_HID_12c5a] = 1562,
+	[BNXT_ULP_CLASS_HID_17c78] = 1563,
+	[BNXT_ULP_CLASS_HID_167ba] = 1564,
+	[BNXT_ULP_CLASS_HID_1f91] = 1565,
+	[BNXT_ULP_CLASS_HID_0763] = 1566,
+	[BNXT_ULP_CLASS_HID_0f7b] = 1567,
+	[BNXT_ULP_CLASS_HID_16af] = 1568,
+	[BNXT_ULP_CLASS_HID_1daf] = 1569,
+	[BNXT_ULP_CLASS_HID_0539] = 1570,
+	[BNXT_ULP_CLASS_HID_01ed] = 1571,
+	[BNXT_ULP_CLASS_HID_097f] = 1572,
+	[BNXT_ULP_CLASS_HID_81ab8] = 1573,
+	[BNXT_ULP_CLASS_HID_8020e] = 1574,
+	[BNXT_ULP_CLASS_HID_815d8] = 1575,
+	[BNXT_ULP_CLASS_HID_81cae] = 1576,
+	[BNXT_ULP_CLASS_HID_810a8] = 1577,
+	[BNXT_ULP_CLASS_HID_8183e] = 1578,
+	[BNXT_ULP_CLASS_HID_8036a] = 1579,
+	[BNXT_ULP_CLASS_HID_80af8] = 1580,
+	[BNXT_ULP_CLASS_HID_206fe] = 1581,
+	[BNXT_ULP_CLASS_HID_20e4c] = 1582,
+	[BNXT_ULP_CLASS_HID_2111e] = 1583,
+	[BNXT_ULP_CLASS_HID_218ec] = 1584,
+	[BNXT_ULP_CLASS_HID_60472] = 1585,
+	[BNXT_ULP_CLASS_HID_603c0] = 1586,
+	[BNXT_ULP_CLASS_HID_61692] = 1587,
+	[BNXT_ULP_CLASS_HID_61e60] = 1588,
+	[BNXT_ULP_CLASS_HID_1f81] = 1589,
+	[BNXT_ULP_CLASS_HID_0773] = 1590,
+	[BNXT_ULP_CLASS_HID_0f6b] = 1591,
+	[BNXT_ULP_CLASS_HID_16bf] = 1592,
+	[BNXT_ULP_CLASS_HID_03cf] = 1593,
+	[BNXT_ULP_CLASS_HID_0ab1] = 1594,
+	[BNXT_ULP_CLASS_HID_130b] = 1595,
+	[BNXT_ULP_CLASS_HID_1afd] = 1596,
+	[BNXT_ULP_CLASS_HID_1591] = 1597,
+	[BNXT_ULP_CLASS_HID_1d03] = 1598,
+	[BNXT_ULP_CLASS_HID_057b] = 1599,
+	[BNXT_ULP_CLASS_HID_0ced] = 1600,
+	[BNXT_ULP_CLASS_HID_19df] = 1601,
+	[BNXT_ULP_CLASS_HID_0141] = 1602,
+	[BNXT_ULP_CLASS_HID_08b9] = 1603,
+	[BNXT_ULP_CLASS_HID_108d] = 1604,
+	[BNXT_ULP_CLASS_HID_1dbf] = 1605,
+	[BNXT_ULP_CLASS_HID_0529] = 1606,
+	[BNXT_ULP_CLASS_HID_01fd] = 1607,
+	[BNXT_ULP_CLASS_HID_096f] = 1608,
+	[BNXT_ULP_CLASS_HID_810b7] = 1609,
+	[BNXT_ULP_CLASS_HID_81821] = 1610,
+	[BNXT_ULP_CLASS_HID_804f5] = 1611,
+	[BNXT_ULP_CLASS_HID_80c67] = 1612,
+	[BNXT_ULP_CLASS_HID_41333] = 1613,
+	[BNXT_ULP_CLASS_HID_41aad] = 1614,
+	[BNXT_ULP_CLASS_HID_40771] = 1615,
+	[BNXT_ULP_CLASS_HID_40ee3] = 1616,
+	[BNXT_ULP_CLASS_HID_c16cb] = 1617,
+	[BNXT_ULP_CLASS_HID_c1da5] = 1618,
+	[BNXT_ULP_CLASS_HID_c1a09] = 1619,
+	[BNXT_ULP_CLASS_HID_c01fb] = 1620,
+	[BNXT_ULP_CLASS_HID_1ff1] = 1621,
+	[BNXT_ULP_CLASS_HID_0703] = 1622,
+	[BNXT_ULP_CLASS_HID_0f1b] = 1623,
+	[BNXT_ULP_CLASS_HID_16cf] = 1624,
+	[BNXT_ULP_CLASS_HID_03bf] = 1625,
+	[BNXT_ULP_CLASS_HID_0ac1] = 1626,
+	[BNXT_ULP_CLASS_HID_137b] = 1627,
+	[BNXT_ULP_CLASS_HID_1a8d] = 1628,
+	[BNXT_ULP_CLASS_HID_15e1] = 1629,
+	[BNXT_ULP_CLASS_HID_1d73] = 1630,
+	[BNXT_ULP_CLASS_HID_050b] = 1631,
+	[BNXT_ULP_CLASS_HID_0c9d] = 1632,
+	[BNXT_ULP_CLASS_HID_19af] = 1633,
+	[BNXT_ULP_CLASS_HID_0131] = 1634,
+	[BNXT_ULP_CLASS_HID_08c9] = 1635,
+	[BNXT_ULP_CLASS_HID_10fd] = 1636,
+	[BNXT_ULP_CLASS_HID_1dcf] = 1637,
+	[BNXT_ULP_CLASS_HID_0559] = 1638,
+	[BNXT_ULP_CLASS_HID_018d] = 1639,
+	[BNXT_ULP_CLASS_HID_091f] = 1640,
+	[BNXT_ULP_CLASS_HID_810c7] = 1641,
+	[BNXT_ULP_CLASS_HID_81851] = 1642,
+	[BNXT_ULP_CLASS_HID_80485] = 1643,
+	[BNXT_ULP_CLASS_HID_80c17] = 1644,
+	[BNXT_ULP_CLASS_HID_41343] = 1645,
+	[BNXT_ULP_CLASS_HID_41add] = 1646,
+	[BNXT_ULP_CLASS_HID_40701] = 1647,
+	[BNXT_ULP_CLASS_HID_40e93] = 1648,
+	[BNXT_ULP_CLASS_HID_c16bb] = 1649,
+	[BNXT_ULP_CLASS_HID_c1dd5] = 1650,
+	[BNXT_ULP_CLASS_HID_c1a79] = 1651,
+	[BNXT_ULP_CLASS_HID_c018b] = 1652,
+	[BNXT_ULP_CLASS_HID_81aa8] = 1653,
+	[BNXT_ULP_CLASS_HID_8021e] = 1654,
+	[BNXT_ULP_CLASS_HID_815c8] = 1655,
+	[BNXT_ULP_CLASS_HID_81cbe] = 1656,
+	[BNXT_ULP_CLASS_HID_810b8] = 1657,
+	[BNXT_ULP_CLASS_HID_8182e] = 1658,
+	[BNXT_ULP_CLASS_HID_8037a] = 1659,
+	[BNXT_ULP_CLASS_HID_80ae8] = 1660,
+	[BNXT_ULP_CLASS_HID_c1834] = 1661,
+	[BNXT_ULP_CLASS_HID_c079a] = 1662,
+	[BNXT_ULP_CLASS_HID_c0af6] = 1663,
+	[BNXT_ULP_CLASS_HID_c123a] = 1664,
+	[BNXT_ULP_CLASS_HID_c16c4] = 1665,
+	[BNXT_ULP_CLASS_HID_c1daa] = 1666,
+	[BNXT_ULP_CLASS_HID_c0086] = 1667,
+	[BNXT_ULP_CLASS_HID_c0874] = 1668,
+	[BNXT_ULP_CLASS_HID_a19ea] = 1669,
+	[BNXT_ULP_CLASS_HID_a0158] = 1670,
+	[BNXT_ULP_CLASS_HID_a0bb4] = 1671,
+	[BNXT_ULP_CLASS_HID_a13f8] = 1672,
+	[BNXT_ULP_CLASS_HID_a17fa] = 1673,
+	[BNXT_ULP_CLASS_HID_a1f68] = 1674,
+	[BNXT_ULP_CLASS_HID_a0244] = 1675,
+	[BNXT_ULP_CLASS_HID_a092a] = 1676,
+	[BNXT_ULP_CLASS_HID_e1f76] = 1677,
+	[BNXT_ULP_CLASS_HID_e06e4] = 1678,
+	[BNXT_ULP_CLASS_HID_e0930] = 1679,
+	[BNXT_ULP_CLASS_HID_e1104] = 1680,
+	[BNXT_ULP_CLASS_HID_e1506] = 1681,
+	[BNXT_ULP_CLASS_HID_e1cf4] = 1682,
+	[BNXT_ULP_CLASS_HID_e07c0] = 1683,
+	[BNXT_ULP_CLASS_HID_e0eb6] = 1684,
+	[BNXT_ULP_CLASS_HID_206ee] = 1685,
+	[BNXT_ULP_CLASS_HID_20e5c] = 1686,
+	[BNXT_ULP_CLASS_HID_2110e] = 1687,
+	[BNXT_ULP_CLASS_HID_218fc] = 1688,
+	[BNXT_ULP_CLASS_HID_60462] = 1689,
+	[BNXT_ULP_CLASS_HID_603d0] = 1690,
+	[BNXT_ULP_CLASS_HID_61682] = 1691,
+	[BNXT_ULP_CLASS_HID_61e70] = 1692,
+	[BNXT_ULP_CLASS_HID_3167e] = 1693,
+	[BNXT_ULP_CLASS_HID_31dec] = 1694,
+	[BNXT_ULP_CLASS_HID_30030] = 1695,
+	[BNXT_ULP_CLASS_HID_30fae] = 1696,
+	[BNXT_ULP_CLASS_HID_70b14] = 1697,
+	[BNXT_ULP_CLASS_HID_71360] = 1698,
+	[BNXT_ULP_CLASS_HID_705b4] = 1699,
+	[BNXT_ULP_CLASS_HID_70d22] = 1700,
+	[BNXT_ULP_CLASS_HID_29e26] = 1701,
+	[BNXT_ULP_CLASS_HID_28594] = 1702,
+	[BNXT_ULP_CLASS_HID_288f8] = 1703,
+	[BNXT_ULP_CLASS_HID_29034] = 1704,
+	[BNXT_ULP_CLASS_HID_693ba] = 1705,
+	[BNXT_ULP_CLASS_HID_69b28] = 1706,
+	[BNXT_ULP_CLASS_HID_68e7c] = 1707,
+	[BNXT_ULP_CLASS_HID_69648] = 1708,
+	[BNXT_ULP_CLASS_HID_38de8] = 1709,
+	[BNXT_ULP_CLASS_HID_39524] = 1710,
+	[BNXT_ULP_CLASS_HID_39808] = 1711,
+	[BNXT_ULP_CLASS_HID_387e6] = 1712,
+	[BNXT_ULP_CLASS_HID_7836c] = 1713,
+	[BNXT_ULP_CLASS_HID_78ada] = 1714,
+	[BNXT_ULP_CLASS_HID_79d8c] = 1715,
+	[BNXT_ULP_CLASS_HID_7857a] = 1716,
+	[BNXT_ULP_CLASS_HID_81ad8] = 1717,
+	[BNXT_ULP_CLASS_HID_8026e] = 1718,
+	[BNXT_ULP_CLASS_HID_815b8] = 1719,
+	[BNXT_ULP_CLASS_HID_81cce] = 1720,
+	[BNXT_ULP_CLASS_HID_810c8] = 1721,
+	[BNXT_ULP_CLASS_HID_8185e] = 1722,
+	[BNXT_ULP_CLASS_HID_8030a] = 1723,
+	[BNXT_ULP_CLASS_HID_80a98] = 1724,
+	[BNXT_ULP_CLASS_HID_c1844] = 1725,
+	[BNXT_ULP_CLASS_HID_c07ea] = 1726,
+	[BNXT_ULP_CLASS_HID_c0a86] = 1727,
+	[BNXT_ULP_CLASS_HID_c124a] = 1728,
+	[BNXT_ULP_CLASS_HID_c16b4] = 1729,
+	[BNXT_ULP_CLASS_HID_c1dda] = 1730,
+	[BNXT_ULP_CLASS_HID_c00f6] = 1731,
+	[BNXT_ULP_CLASS_HID_c0804] = 1732,
+	[BNXT_ULP_CLASS_HID_a199a] = 1733,
+	[BNXT_ULP_CLASS_HID_a0128] = 1734,
+	[BNXT_ULP_CLASS_HID_a0bc4] = 1735,
+	[BNXT_ULP_CLASS_HID_a1388] = 1736,
+	[BNXT_ULP_CLASS_HID_a178a] = 1737,
+	[BNXT_ULP_CLASS_HID_a1f18] = 1738,
+	[BNXT_ULP_CLASS_HID_a0234] = 1739,
+	[BNXT_ULP_CLASS_HID_a095a] = 1740,
+	[BNXT_ULP_CLASS_HID_e1f06] = 1741,
+	[BNXT_ULP_CLASS_HID_e0694] = 1742,
+	[BNXT_ULP_CLASS_HID_e0940] = 1743,
+	[BNXT_ULP_CLASS_HID_e1174] = 1744,
+	[BNXT_ULP_CLASS_HID_e1576] = 1745,
+	[BNXT_ULP_CLASS_HID_e1c84] = 1746,
+	[BNXT_ULP_CLASS_HID_e07b0] = 1747,
+	[BNXT_ULP_CLASS_HID_e0ec6] = 1748,
+	[BNXT_ULP_CLASS_HID_2069e] = 1749,
+	[BNXT_ULP_CLASS_HID_20e2c] = 1750,
+	[BNXT_ULP_CLASS_HID_2117e] = 1751,
+	[BNXT_ULP_CLASS_HID_2188c] = 1752,
+	[BNXT_ULP_CLASS_HID_60412] = 1753,
+	[BNXT_ULP_CLASS_HID_603a0] = 1754,
+	[BNXT_ULP_CLASS_HID_616f2] = 1755,
+	[BNXT_ULP_CLASS_HID_61e00] = 1756,
+	[BNXT_ULP_CLASS_HID_3160e] = 1757,
+	[BNXT_ULP_CLASS_HID_31d9c] = 1758,
+	[BNXT_ULP_CLASS_HID_30040] = 1759,
+	[BNXT_ULP_CLASS_HID_30fde] = 1760,
+	[BNXT_ULP_CLASS_HID_70b64] = 1761,
+	[BNXT_ULP_CLASS_HID_71310] = 1762,
+	[BNXT_ULP_CLASS_HID_705c4] = 1763,
+	[BNXT_ULP_CLASS_HID_70d52] = 1764,
+	[BNXT_ULP_CLASS_HID_29e56] = 1765,
+	[BNXT_ULP_CLASS_HID_285e4] = 1766,
+	[BNXT_ULP_CLASS_HID_28888] = 1767,
+	[BNXT_ULP_CLASS_HID_29044] = 1768,
+	[BNXT_ULP_CLASS_HID_693ca] = 1769,
+	[BNXT_ULP_CLASS_HID_69b58] = 1770,
+	[BNXT_ULP_CLASS_HID_68e0c] = 1771,
+	[BNXT_ULP_CLASS_HID_69638] = 1772,
+	[BNXT_ULP_CLASS_HID_38d98] = 1773,
+	[BNXT_ULP_CLASS_HID_39554] = 1774,
+	[BNXT_ULP_CLASS_HID_39878] = 1775,
+	[BNXT_ULP_CLASS_HID_38796] = 1776,
+	[BNXT_ULP_CLASS_HID_7831c] = 1777,
+	[BNXT_ULP_CLASS_HID_78aaa] = 1778,
+	[BNXT_ULP_CLASS_HID_79dfc] = 1779,
+	[BNXT_ULP_CLASS_HID_7850a] = 1780,
+	[BNXT_ULP_CLASS_HID_03b7] = 1781,
+	[BNXT_ULP_CLASS_HID_13f3] = 1782,
+	[BNXT_ULP_CLASS_HID_0255] = 1783,
+	[BNXT_ULP_CLASS_HID_1675] = 1784,
+	[BNXT_ULP_CLASS_HID_80f52] = 1785,
+	[BNXT_ULP_CLASS_HID_819f2] = 1786,
+	[BNXT_ULP_CLASS_HID_80542] = 1787,
+	[BNXT_ULP_CLASS_HID_817e2] = 1788,
+	[BNXT_ULP_CLASS_HID_20a98] = 1789,
+	[BNXT_ULP_CLASS_HID_20538] = 1790,
+	[BNXT_ULP_CLASS_HID_6081c] = 1791,
+	[BNXT_ULP_CLASS_HID_61abc] = 1792,
+	[BNXT_ULP_CLASS_HID_03a7] = 1793,
+	[BNXT_ULP_CLASS_HID_13e3] = 1794,
+	[BNXT_ULP_CLASS_HID_1047] = 1795,
+	[BNXT_ULP_CLASS_HID_0721] = 1796,
+	[BNXT_ULP_CLASS_HID_19b7] = 1797,
+	[BNXT_ULP_CLASS_HID_0911] = 1798,
+	[BNXT_ULP_CLASS_HID_0df5] = 1799,
+	[BNXT_ULP_CLASS_HID_1d31] = 1800,
+	[BNXT_ULP_CLASS_HID_0245] = 1801,
+	[BNXT_ULP_CLASS_HID_1665] = 1802,
+	[BNXT_ULP_CLASS_HID_8055d] = 1803,
+	[BNXT_ULP_CLASS_HID_80893] = 1804,
+	[BNXT_ULP_CLASS_HID_407d9] = 1805,
+	[BNXT_ULP_CLASS_HID_40b1f] = 1806,
+	[BNXT_ULP_CLASS_HID_c1ad1] = 1807,
+	[BNXT_ULP_CLASS_HID_c0e17] = 1808,
+	[BNXT_ULP_CLASS_HID_03d7] = 1809,
+	[BNXT_ULP_CLASS_HID_1393] = 1810,
+	[BNXT_ULP_CLASS_HID_1037] = 1811,
+	[BNXT_ULP_CLASS_HID_0751] = 1812,
+	[BNXT_ULP_CLASS_HID_19c7] = 1813,
+	[BNXT_ULP_CLASS_HID_0961] = 1814,
+	[BNXT_ULP_CLASS_HID_0d85] = 1815,
+	[BNXT_ULP_CLASS_HID_1d41] = 1816,
+	[BNXT_ULP_CLASS_HID_0235] = 1817,
+	[BNXT_ULP_CLASS_HID_1615] = 1818,
+	[BNXT_ULP_CLASS_HID_8052d] = 1819,
+	[BNXT_ULP_CLASS_HID_808e3] = 1820,
+	[BNXT_ULP_CLASS_HID_407a9] = 1821,
+	[BNXT_ULP_CLASS_HID_40b6f] = 1822,
+	[BNXT_ULP_CLASS_HID_c1aa1] = 1823,
+	[BNXT_ULP_CLASS_HID_c0e67] = 1824,
+	[BNXT_ULP_CLASS_HID_80f42] = 1825,
+	[BNXT_ULP_CLASS_HID_819e2] = 1826,
+	[BNXT_ULP_CLASS_HID_80552] = 1827,
+	[BNXT_ULP_CLASS_HID_817f2] = 1828,
+	[BNXT_ULP_CLASS_HID_c0cce] = 1829,
+	[BNXT_ULP_CLASS_HID_c1f6e] = 1830,
+	[BNXT_ULP_CLASS_HID_c1ade] = 1831,
+	[BNXT_ULP_CLASS_HID_c157e] = 1832,
+	[BNXT_ULP_CLASS_HID_a0d8c] = 1833,
+	[BNXT_ULP_CLASS_HID_a182c] = 1834,
+	[BNXT_ULP_CLASS_HID_a1b9c] = 1835,
+	[BNXT_ULP_CLASS_HID_a163c] = 1836,
+	[BNXT_ULP_CLASS_HID_e0308] = 1837,
+	[BNXT_ULP_CLASS_HID_e1da8] = 1838,
+	[BNXT_ULP_CLASS_HID_e1918] = 1839,
+	[BNXT_ULP_CLASS_HID_e0bda] = 1840,
+	[BNXT_ULP_CLASS_HID_20a88] = 1841,
+	[BNXT_ULP_CLASS_HID_20528] = 1842,
+	[BNXT_ULP_CLASS_HID_6080c] = 1843,
+	[BNXT_ULP_CLASS_HID_61aac] = 1844,
+	[BNXT_ULP_CLASS_HID_31a18] = 1845,
+	[BNXT_ULP_CLASS_HID_314b8] = 1846,
+	[BNXT_ULP_CLASS_HID_71f9c] = 1847,
+	[BNXT_ULP_CLASS_HID_70a5e] = 1848,
+	[BNXT_ULP_CLASS_HID_282c0] = 1849,
+	[BNXT_ULP_CLASS_HID_29d60] = 1850,
+	[BNXT_ULP_CLASS_HID_68044] = 1851,
+	[BNXT_ULP_CLASS_HID_692e4] = 1852,
+	[BNXT_ULP_CLASS_HID_39250] = 1853,
+	[BNXT_ULP_CLASS_HID_38c12] = 1854,
+	[BNXT_ULP_CLASS_HID_797d4] = 1855,
+	[BNXT_ULP_CLASS_HID_78196] = 1856,
+	[BNXT_ULP_CLASS_HID_80f32] = 1857,
+	[BNXT_ULP_CLASS_HID_81992] = 1858,
+	[BNXT_ULP_CLASS_HID_80522] = 1859,
+	[BNXT_ULP_CLASS_HID_81782] = 1860,
+	[BNXT_ULP_CLASS_HID_c0cbe] = 1861,
+	[BNXT_ULP_CLASS_HID_c1f1e] = 1862,
+	[BNXT_ULP_CLASS_HID_c1aae] = 1863,
+	[BNXT_ULP_CLASS_HID_c150e] = 1864,
+	[BNXT_ULP_CLASS_HID_a0dfc] = 1865,
+	[BNXT_ULP_CLASS_HID_a185c] = 1866,
+	[BNXT_ULP_CLASS_HID_a1bec] = 1867,
+	[BNXT_ULP_CLASS_HID_a164c] = 1868,
+	[BNXT_ULP_CLASS_HID_e0378] = 1869,
+	[BNXT_ULP_CLASS_HID_e1dd8] = 1870,
+	[BNXT_ULP_CLASS_HID_e1968] = 1871,
+	[BNXT_ULP_CLASS_HID_e0baa] = 1872,
+	[BNXT_ULP_CLASS_HID_20af8] = 1873,
+	[BNXT_ULP_CLASS_HID_20558] = 1874,
+	[BNXT_ULP_CLASS_HID_6087c] = 1875,
+	[BNXT_ULP_CLASS_HID_61adc] = 1876,
+	[BNXT_ULP_CLASS_HID_31a68] = 1877,
+	[BNXT_ULP_CLASS_HID_314c8] = 1878,
+	[BNXT_ULP_CLASS_HID_71fec] = 1879,
+	[BNXT_ULP_CLASS_HID_70a2e] = 1880,
+	[BNXT_ULP_CLASS_HID_282b0] = 1881,
+	[BNXT_ULP_CLASS_HID_29d10] = 1882,
+	[BNXT_ULP_CLASS_HID_68034] = 1883,
+	[BNXT_ULP_CLASS_HID_69294] = 1884,
+	[BNXT_ULP_CLASS_HID_39220] = 1885,
+	[BNXT_ULP_CLASS_HID_38c62] = 1886,
+	[BNXT_ULP_CLASS_HID_797a4] = 1887,
+	[BNXT_ULP_CLASS_HID_781e6] = 1888,
+	[BNXT_ULP_CLASS_HID_0f05] = 1889,
+	[BNXT_ULP_CLASS_HID_0f09] = 1890,
+	[BNXT_ULP_CLASS_HID_0f06] = 1891,
+	[BNXT_ULP_CLASS_HID_19a6] = 1892,
+	[BNXT_ULP_CLASS_HID_0f0a] = 1893,
+	[BNXT_ULP_CLASS_HID_19aa] = 1894,
+	[BNXT_ULP_CLASS_HID_0f15] = 1895,
+	[BNXT_ULP_CLASS_HID_0f19] = 1896,
+	[BNXT_ULP_CLASS_HID_0f65] = 1897,
+	[BNXT_ULP_CLASS_HID_0f69] = 1898,
+	[BNXT_ULP_CLASS_HID_0f16] = 1899,
+	[BNXT_ULP_CLASS_HID_19b6] = 1900,
+	[BNXT_ULP_CLASS_HID_0f1a] = 1901,
+	[BNXT_ULP_CLASS_HID_19ba] = 1902,
+	[BNXT_ULP_CLASS_HID_0f66] = 1903,
+	[BNXT_ULP_CLASS_HID_19c6] = 1904,
+	[BNXT_ULP_CLASS_HID_0f6a] = 1905,
+	[BNXT_ULP_CLASS_HID_19ca] = 1906
 };
 
 /* Array for the proto matcher list */
 struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	[1] = {
-	.class_hid = BNXT_ULP_CLASS_HID_55dd,
+	.class_hid = BNXT_ULP_CLASS_HID_00b8,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
 	.flow_sig_id = 4096UL,
@@ -1332,7 +1940,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[2] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1df1,
+	.class_hid = BNXT_ULP_CLASS_HID_0cc2,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
 	.flow_sig_id = 4104UL,
@@ -1348,7 +1956,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[3] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3e55,
+	.class_hid = BNXT_ULP_CLASS_HID_10e4,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
 	.flow_sig_id = 6144UL,
@@ -1364,7 +1972,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[4] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0649,
+	.class_hid = BNXT_ULP_CLASS_HID_1d0e,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
 	.flow_sig_id = 6152UL,
@@ -1381,7 +1989,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[5] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1011,
+	.class_hid = BNXT_ULP_CLASS_HID_0286,
 	.class_tid = 1,
 	.hdr_sig_id = 1,
 	.flow_sig_id = 16384UL,
@@ -1396,7 +2004,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[6] = {
-	.class_hid = BNXT_ULP_CLASS_HID_40e9,
+	.class_hid = BNXT_ULP_CLASS_HID_0e98,
 	.class_tid = 1,
 	.hdr_sig_id = 1,
 	.flow_sig_id = 16392UL,
@@ -1412,7 +2020,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[7] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3e99,
+	.class_hid = BNXT_ULP_CLASS_HID_1666,
 	.class_tid = 1,
 	.hdr_sig_id = 1,
 	.flow_sig_id = 24576UL,
@@ -1428,7 +2036,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[8] = {
-	.class_hid = BNXT_ULP_CLASS_HID_06ad,
+	.class_hid = BNXT_ULP_CLASS_HID_02de,
 	.class_tid = 1,
 	.hdr_sig_id = 1,
 	.flow_sig_id = 24584UL,
@@ -1445,7 +2053,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[9] = {
-	.class_hid = BNXT_ULP_CLASS_HID_38c7,
+	.class_hid = BNXT_ULP_CLASS_HID_81d25,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 32768UL,
@@ -1461,7 +2069,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[10] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00fb,
+	.class_hid = BNXT_ULP_CLASS_HID_809ad,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 32776UL,
@@ -1478,7 +2086,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[11] = {
-	.class_hid = BNXT_ULP_CLASS_HID_24d3,
+	.class_hid = BNXT_ULP_CLASS_HID_80ae3,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 32832UL,
@@ -1495,7 +2103,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[12] = {
-	.class_hid = BNXT_ULP_CLASS_HID_559b,
+	.class_hid = BNXT_ULP_CLASS_HID_8170d,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 32840UL,
@@ -1513,7 +2121,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[13] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5003,
+	.class_hid = BNXT_ULP_CLASS_HID_80773,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 49152UL,
@@ -1530,7 +2138,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[14] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1837,
+	.class_hid = BNXT_ULP_CLASS_HID_8139d,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 49160UL,
@@ -1548,7 +2156,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[15] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3bef,
+	.class_hid = BNXT_ULP_CLASS_HID_814d3,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 49216UL,
@@ -1566,7 +2174,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[16] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0403,
+	.class_hid = BNXT_ULP_CLASS_HID_8015b,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 49224UL,
@@ -1585,7 +2193,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[17] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3d3f,
+	.class_hid = BNXT_ULP_CLASS_HID_21977,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 131072UL,
@@ -1601,7 +2209,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[18] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0543,
+	.class_hid = BNXT_ULP_CLASS_HID_205ef,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 131080UL,
@@ -1618,7 +2226,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[19] = {
-	.class_hid = BNXT_ULP_CLASS_HID_292b,
+	.class_hid = BNXT_ULP_CLASS_HID_20735,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 131136UL,
@@ -1635,7 +2243,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[20] = {
-	.class_hid = BNXT_ULP_CLASS_HID_59e3,
+	.class_hid = BNXT_ULP_CLASS_HID_2134f,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 131144UL,
@@ -1653,7 +2261,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[21] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5d3b,
+	.class_hid = BNXT_ULP_CLASS_HID_61beb,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 196608UL,
@@ -1670,7 +2278,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[22] = {
-	.class_hid = BNXT_ULP_CLASS_HID_254f,
+	.class_hid = BNXT_ULP_CLASS_HID_60863,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 196616UL,
@@ -1688,7 +2296,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[23] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4917,
+	.class_hid = BNXT_ULP_CLASS_HID_609a9,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 196672UL,
@@ -1706,7 +2314,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[24] = {
-	.class_hid = BNXT_ULP_CLASS_HID_113b,
+	.class_hid = BNXT_ULP_CLASS_HID_615c3,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 196680UL,
@@ -1725,7 +2333,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[25] = {
-	.class_hid = BNXT_ULP_CLASS_HID_55fd,
+	.class_hid = BNXT_ULP_CLASS_HID_00a8,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 4096UL,
@@ -1741,7 +2349,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[26] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1dd1,
+	.class_hid = BNXT_ULP_CLASS_HID_0cd2,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 4104UL,
@@ -1758,7 +2366,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[27] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3e75,
+	.class_hid = BNXT_ULP_CLASS_HID_10f4,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 6144UL,
@@ -1775,7 +2383,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[28] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0669,
+	.class_hid = BNXT_ULP_CLASS_HID_1d1e,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 6152UL,
@@ -1793,7 +2401,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[29] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1ba1,
+	.class_hid = BNXT_ULP_CLASS_HID_1488,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 12288UL,
@@ -1810,7 +2418,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
 	},
 	[30] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4c69,
+	.class_hid = BNXT_ULP_CLASS_HID_0110,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 12296UL,
@@ -1828,7 +2436,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
 	},
 	[31] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0439,
+	.class_hid = BNXT_ULP_CLASS_HID_0532,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 14336UL,
@@ -1846,7 +2454,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
 	},
 	[32] = {
-	.class_hid = BNXT_ULP_CLASS_HID_34e1,
+	.class_hid = BNXT_ULP_CLASS_HID_115c,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 14344UL,
@@ -1865,7 +2473,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
 	},
 	[33] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0465,
+	.class_hid = BNXT_ULP_CLASS_HID_0ab8,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 20480UL,
@@ -1882,7 +2490,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[34] = {
-	.class_hid = BNXT_ULP_CLASS_HID_352d,
+	.class_hid = BNXT_ULP_CLASS_HID_16a2,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 20488UL,
@@ -1900,7 +2508,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[35] = {
-	.class_hid = BNXT_ULP_CLASS_HID_55b1,
+	.class_hid = BNXT_ULP_CLASS_HID_1ac4,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 22528UL,
@@ -1918,7 +2526,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[36] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1da5,
+	.class_hid = BNXT_ULP_CLASS_HID_074c,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 22536UL,
@@ -1937,7 +2545,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[37] = {
-	.class_hid = BNXT_ULP_CLASS_HID_32fd,
+	.class_hid = BNXT_ULP_CLASS_HID_1e98,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 28672UL,
@@ -1955,7 +2563,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[38] = {
-	.class_hid = BNXT_ULP_CLASS_HID_63a5,
+	.class_hid = BNXT_ULP_CLASS_HID_0ae0,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 28680UL,
@@ -1974,7 +2582,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[39] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1b75,
+	.class_hid = BNXT_ULP_CLASS_HID_0f02,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 30720UL,
@@ -1993,7 +2601,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[40] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4c3d,
+	.class_hid = BNXT_ULP_CLASS_HID_1b2c,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 30728UL,
@@ -2013,7 +2621,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[41] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1031,
+	.class_hid = BNXT_ULP_CLASS_HID_0296,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 16384UL,
@@ -2029,7 +2637,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[42] = {
-	.class_hid = BNXT_ULP_CLASS_HID_40c9,
+	.class_hid = BNXT_ULP_CLASS_HID_0e88,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 16392UL,
@@ -2046,7 +2654,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[43] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3eb9,
+	.class_hid = BNXT_ULP_CLASS_HID_1676,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 24576UL,
@@ -2063,7 +2671,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[44] = {
-	.class_hid = BNXT_ULP_CLASS_HID_068d,
+	.class_hid = BNXT_ULP_CLASS_HID_02ce,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 24584UL,
@@ -2081,7 +2689,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[45] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5039,
+	.class_hid = BNXT_ULP_CLASS_HID_8076e,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 49152UL,
@@ -2098,7 +2706,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
 	},
 	[46] = {
-	.class_hid = BNXT_ULP_CLASS_HID_180d,
+	.class_hid = BNXT_ULP_CLASS_HID_81380,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 49160UL,
@@ -2116,7 +2724,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
 	},
 	[47] = {
-	.class_hid = BNXT_ULP_CLASS_HID_15fd,
+	.class_hid = BNXT_ULP_CLASS_HID_81b4e,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 57344UL,
@@ -2134,7 +2742,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
 	},
 	[48] = {
-	.class_hid = BNXT_ULP_CLASS_HID_46b5,
+	.class_hid = BNXT_ULP_CLASS_HID_807c6,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 57352UL,
@@ -2153,7 +2761,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
 	},
 	[49] = {
-	.class_hid = BNXT_ULP_CLASS_HID_303d,
+	.class_hid = BNXT_ULP_CLASS_HID_404ea,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 81920UL,
@@ -2170,7 +2778,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[50] = {
-	.class_hid = BNXT_ULP_CLASS_HID_60f5,
+	.class_hid = BNXT_ULP_CLASS_HID_4110c,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 81928UL,
@@ -2188,7 +2796,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[51] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5ea5,
+	.class_hid = BNXT_ULP_CLASS_HID_418ca,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 90112UL,
@@ -2206,7 +2814,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[52] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2689,
+	.class_hid = BNXT_ULP_CLASS_HID_40542,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 90120UL,
@@ -2225,7 +2833,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[53] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0771,
+	.class_hid = BNXT_ULP_CLASS_HID_c09e2,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 114688UL,
@@ -2243,7 +2851,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[54] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3809,
+	.class_hid = BNXT_ULP_CLASS_HID_c1604,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 114696UL,
@@ -2262,7 +2870,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[55] = {
-	.class_hid = BNXT_ULP_CLASS_HID_35f9,
+	.class_hid = BNXT_ULP_CLASS_HID_c1dc2,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 122880UL,
@@ -2281,7 +2889,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[56] = {
-	.class_hid = BNXT_ULP_CLASS_HID_66b1,
+	.class_hid = BNXT_ULP_CLASS_HID_c0a5a,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 122888UL,
@@ -2301,7 +2909,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[57] = {
-	.class_hid = BNXT_ULP_CLASS_HID_559d,
+	.class_hid = BNXT_ULP_CLASS_HID_0098,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 4096UL,
@@ -2317,7 +2925,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[58] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1db1,
+	.class_hid = BNXT_ULP_CLASS_HID_0ce2,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 4104UL,
@@ -2334,7 +2942,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[59] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3e15,
+	.class_hid = BNXT_ULP_CLASS_HID_10c4,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 6144UL,
@@ -2351,7 +2959,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[60] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0609,
+	.class_hid = BNXT_ULP_CLASS_HID_1d2e,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 6152UL,
@@ -2369,7 +2977,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[61] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1bc1,
+	.class_hid = BNXT_ULP_CLASS_HID_14b8,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 12288UL,
@@ -2386,7 +2994,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
 	},
 	[62] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4c09,
+	.class_hid = BNXT_ULP_CLASS_HID_0120,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 12296UL,
@@ -2404,7 +3012,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
 	},
 	[63] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0459,
+	.class_hid = BNXT_ULP_CLASS_HID_0502,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 14336UL,
@@ -2422,7 +3030,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
 	},
 	[64] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3481,
+	.class_hid = BNXT_ULP_CLASS_HID_116c,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 14344UL,
@@ -2441,7 +3049,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
 	},
 	[65] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0405,
+	.class_hid = BNXT_ULP_CLASS_HID_0a88,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 20480UL,
@@ -2458,7 +3066,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[66] = {
-	.class_hid = BNXT_ULP_CLASS_HID_354d,
+	.class_hid = BNXT_ULP_CLASS_HID_1692,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 20488UL,
@@ -2476,7 +3084,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[67] = {
-	.class_hid = BNXT_ULP_CLASS_HID_55d1,
+	.class_hid = BNXT_ULP_CLASS_HID_1af4,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 22528UL,
@@ -2494,7 +3102,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[68] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1dc5,
+	.class_hid = BNXT_ULP_CLASS_HID_077c,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 22536UL,
@@ -2513,7 +3121,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[69] = {
-	.class_hid = BNXT_ULP_CLASS_HID_329d,
+	.class_hid = BNXT_ULP_CLASS_HID_1ea8,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 28672UL,
@@ -2531,7 +3139,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[70] = {
-	.class_hid = BNXT_ULP_CLASS_HID_63c5,
+	.class_hid = BNXT_ULP_CLASS_HID_0ad0,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 28680UL,
@@ -2550,7 +3158,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[71] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1b15,
+	.class_hid = BNXT_ULP_CLASS_HID_0f32,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 30720UL,
@@ -2569,7 +3177,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[72] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4c5d,
+	.class_hid = BNXT_ULP_CLASS_HID_1b1c,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 30728UL,
@@ -2589,7 +3197,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[73] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1051,
+	.class_hid = BNXT_ULP_CLASS_HID_02a6,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 16384UL,
@@ -2605,7 +3213,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[74] = {
-	.class_hid = BNXT_ULP_CLASS_HID_40a9,
+	.class_hid = BNXT_ULP_CLASS_HID_0eb8,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 16392UL,
@@ -2622,7 +3230,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[75] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3ed9,
+	.class_hid = BNXT_ULP_CLASS_HID_1646,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 24576UL,
@@ -2639,7 +3247,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[76] = {
-	.class_hid = BNXT_ULP_CLASS_HID_06ed,
+	.class_hid = BNXT_ULP_CLASS_HID_02fe,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 24584UL,
@@ -2657,7 +3265,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[77] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5059,
+	.class_hid = BNXT_ULP_CLASS_HID_8075e,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 49152UL,
@@ -2674,7 +3282,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
 	},
 	[78] = {
-	.class_hid = BNXT_ULP_CLASS_HID_186d,
+	.class_hid = BNXT_ULP_CLASS_HID_813b0,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 49160UL,
@@ -2692,7 +3300,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
 	},
 	[79] = {
-	.class_hid = BNXT_ULP_CLASS_HID_159d,
+	.class_hid = BNXT_ULP_CLASS_HID_81b7e,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 57344UL,
@@ -2710,7 +3318,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
 	},
 	[80] = {
-	.class_hid = BNXT_ULP_CLASS_HID_46d5,
+	.class_hid = BNXT_ULP_CLASS_HID_807f6,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 57352UL,
@@ -2729,7 +3337,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
 	},
 	[81] = {
-	.class_hid = BNXT_ULP_CLASS_HID_305d,
+	.class_hid = BNXT_ULP_CLASS_HID_404da,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 81920UL,
@@ -2746,7 +3354,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[82] = {
-	.class_hid = BNXT_ULP_CLASS_HID_6095,
+	.class_hid = BNXT_ULP_CLASS_HID_4113c,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 81928UL,
@@ -2764,7 +3372,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[83] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5ec5,
+	.class_hid = BNXT_ULP_CLASS_HID_418fa,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 90112UL,
@@ -2782,7 +3390,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[84] = {
-	.class_hid = BNXT_ULP_CLASS_HID_26e9,
+	.class_hid = BNXT_ULP_CLASS_HID_40572,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 90120UL,
@@ -2801,7 +3409,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[85] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0711,
+	.class_hid = BNXT_ULP_CLASS_HID_c09d2,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 114688UL,
@@ -2819,7 +3427,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[86] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3869,
+	.class_hid = BNXT_ULP_CLASS_HID_c1634,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 114696UL,
@@ -2838,7 +3446,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[87] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3599,
+	.class_hid = BNXT_ULP_CLASS_HID_c1df2,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 122880UL,
@@ -2857,7 +3465,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[88] = {
-	.class_hid = BNXT_ULP_CLASS_HID_66d1,
+	.class_hid = BNXT_ULP_CLASS_HID_c0a6a,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 122888UL,
@@ -2877,7 +3485,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[89] = {
-	.class_hid = BNXT_ULP_CLASS_HID_38e7,
+	.class_hid = BNXT_ULP_CLASS_HID_81d35,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 32768UL,
@@ -2894,7 +3502,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[90] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00db,
+	.class_hid = BNXT_ULP_CLASS_HID_809bd,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 32776UL,
@@ -2912,7 +3520,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[91] = {
-	.class_hid = BNXT_ULP_CLASS_HID_24f3,
+	.class_hid = BNXT_ULP_CLASS_HID_80af3,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 32832UL,
@@ -2930,7 +3538,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[92] = {
-	.class_hid = BNXT_ULP_CLASS_HID_55bb,
+	.class_hid = BNXT_ULP_CLASS_HID_8171d,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 32840UL,
@@ -2949,7 +3557,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[93] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5023,
+	.class_hid = BNXT_ULP_CLASS_HID_80763,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 49152UL,
@@ -2967,7 +3575,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[94] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1817,
+	.class_hid = BNXT_ULP_CLASS_HID_8138d,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 49160UL,
@@ -2986,7 +3594,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[95] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3bcf,
+	.class_hid = BNXT_ULP_CLASS_HID_814c3,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 49216UL,
@@ -3005,7 +3613,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[96] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0423,
+	.class_hid = BNXT_ULP_CLASS_HID_8014b,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 49224UL,
@@ -3025,7 +3633,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[97] = {
-	.class_hid = BNXT_ULP_CLASS_HID_58e3,
+	.class_hid = BNXT_ULP_CLASS_HID_c001f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 98304UL,
@@ -3043,7 +3651,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[98] = {
-	.class_hid = BNXT_ULP_CLASS_HID_20d7,
+	.class_hid = BNXT_ULP_CLASS_HID_c0c39,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 98312UL,
@@ -3062,7 +3670,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[99] = {
-	.class_hid = BNXT_ULP_CLASS_HID_448f,
+	.class_hid = BNXT_ULP_CLASS_HID_c0d7f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 98368UL,
@@ -3081,7 +3689,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[100] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0ce3,
+	.class_hid = BNXT_ULP_CLASS_HID_c1999,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 98376UL,
@@ -3101,7 +3709,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[101] = {
-	.class_hid = BNXT_ULP_CLASS_HID_076b,
+	.class_hid = BNXT_ULP_CLASS_HID_c09ef,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 114688UL,
@@ -3120,7 +3728,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[102] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3813,
+	.class_hid = BNXT_ULP_CLASS_HID_c1609,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 114696UL,
@@ -3140,7 +3748,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[103] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5bcb,
+	.class_hid = BNXT_ULP_CLASS_HID_c174f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 114752UL,
@@ -3160,7 +3768,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[104] = {
-	.class_hid = BNXT_ULP_CLASS_HID_243f,
+	.class_hid = BNXT_ULP_CLASS_HID_c03d7,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 114760UL,
@@ -3181,7 +3789,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[105] = {
-	.class_hid = BNXT_ULP_CLASS_HID_144b,
+	.class_hid = BNXT_ULP_CLASS_HID_a1e73,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 163840UL,
@@ -3199,7 +3807,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[106] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4573,
+	.class_hid = BNXT_ULP_CLASS_HID_a0afb,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 163848UL,
@@ -3218,7 +3826,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[107] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0057,
+	.class_hid = BNXT_ULP_CLASS_HID_a0c31,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 163904UL,
@@ -3237,7 +3845,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[108] = {
-	.class_hid = BNXT_ULP_CLASS_HID_311f,
+	.class_hid = BNXT_ULP_CLASS_HID_a185b,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 163912UL,
@@ -3257,7 +3865,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[109] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2b87,
+	.class_hid = BNXT_ULP_CLASS_HID_a08a1,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 180224UL,
@@ -3276,7 +3884,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[110] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5c4f,
+	.class_hid = BNXT_ULP_CLASS_HID_a14cb,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 180232UL,
@@ -3296,7 +3904,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[111] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1793,
+	.class_hid = BNXT_ULP_CLASS_HID_a1601,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 180288UL,
@@ -3316,7 +3924,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[112] = {
-	.class_hid = BNXT_ULP_CLASS_HID_485b,
+	.class_hid = BNXT_ULP_CLASS_HID_a0289,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 180296UL,
@@ -3337,7 +3945,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[113] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3447,
+	.class_hid = BNXT_ULP_CLASS_HID_e015d,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 229376UL,
@@ -3356,7 +3964,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[114] = {
-	.class_hid = BNXT_ULP_CLASS_HID_650f,
+	.class_hid = BNXT_ULP_CLASS_HID_e0d47,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 229384UL,
@@ -3376,7 +3984,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[115] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2053,
+	.class_hid = BNXT_ULP_CLASS_HID_e0ebd,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 229440UL,
@@ -3396,7 +4004,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[116] = {
-	.class_hid = BNXT_ULP_CLASS_HID_511b,
+	.class_hid = BNXT_ULP_CLASS_HID_e1aa7,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 229448UL,
@@ -3417,7 +4025,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[117] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4b83,
+	.class_hid = BNXT_ULP_CLASS_HID_e0b2d,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 245760UL,
@@ -3437,7 +4045,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[118] = {
-	.class_hid = BNXT_ULP_CLASS_HID_13f7,
+	.class_hid = BNXT_ULP_CLASS_HID_e1757,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 245768UL,
@@ -3458,7 +4066,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[119] = {
-	.class_hid = BNXT_ULP_CLASS_HID_37af,
+	.class_hid = BNXT_ULP_CLASS_HID_e188d,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 245824UL,
@@ -3479,7 +4087,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[120] = {
-	.class_hid = BNXT_ULP_CLASS_HID_6857,
+	.class_hid = BNXT_ULP_CLASS_HID_e0515,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 245832UL,
@@ -3501,7 +4109,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[121] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3d1f,
+	.class_hid = BNXT_ULP_CLASS_HID_21967,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 131072UL,
@@ -3518,7 +4126,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[122] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0563,
+	.class_hid = BNXT_ULP_CLASS_HID_205ff,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 131080UL,
@@ -3536,7 +4144,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[123] = {
-	.class_hid = BNXT_ULP_CLASS_HID_290b,
+	.class_hid = BNXT_ULP_CLASS_HID_20725,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 131136UL,
@@ -3554,7 +4162,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[124] = {
-	.class_hid = BNXT_ULP_CLASS_HID_59c3,
+	.class_hid = BNXT_ULP_CLASS_HID_2135f,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 131144UL,
@@ -3573,7 +4181,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[125] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5d1b,
+	.class_hid = BNXT_ULP_CLASS_HID_61bfb,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 196608UL,
@@ -3591,7 +4199,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[126] = {
-	.class_hid = BNXT_ULP_CLASS_HID_256f,
+	.class_hid = BNXT_ULP_CLASS_HID_60873,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 196616UL,
@@ -3610,7 +4218,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[127] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4937,
+	.class_hid = BNXT_ULP_CLASS_HID_609b9,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 196672UL,
@@ -3629,7 +4237,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[128] = {
-	.class_hid = BNXT_ULP_CLASS_HID_111b,
+	.class_hid = BNXT_ULP_CLASS_HID_615d3,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 196680UL,
@@ -3649,7 +4257,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[129] = {
-	.class_hid = BNXT_ULP_CLASS_HID_25f4b,
+	.class_hid = BNXT_ULP_CLASS_HID_30a55,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 393216UL,
@@ -3667,7 +4275,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[130] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2275f,
+	.class_hid = BNXT_ULP_CLASS_HID_3164f,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 393224UL,
@@ -3686,7 +4294,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[131] = {
-	.class_hid = BNXT_ULP_CLASS_HID_24b67,
+	.class_hid = BNXT_ULP_CLASS_HID_317b5,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 393280UL,
@@ -3705,7 +4313,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[132] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2134b,
+	.class_hid = BNXT_ULP_CLASS_HID_3040d,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 393288UL,
@@ -3725,7 +4333,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[133] = {
-	.class_hid = BNXT_ULP_CLASS_HID_21683,
+	.class_hid = BNXT_ULP_CLASS_HID_70ca9,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 458752UL,
@@ -3744,7 +4352,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[134] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2475b,
+	.class_hid = BNXT_ULP_CLASS_HID_718c3,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 458760UL,
@@ -3764,7 +4372,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[135] = {
-	.class_hid = BNXT_ULP_CLASS_HID_202bf,
+	.class_hid = BNXT_ULP_CLASS_HID_71a09,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 458816UL,
@@ -3784,7 +4392,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[136] = {
-	.class_hid = BNXT_ULP_CLASS_HID_23377,
+	.class_hid = BNXT_ULP_CLASS_HID_70681,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 458824UL,
@@ -3805,7 +4413,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[137] = {
-	.class_hid = BNXT_ULP_CLASS_HID_119db,
+	.class_hid = BNXT_ULP_CLASS_HID_2821d,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 655360UL,
@@ -3823,7 +4431,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[138] = {
-	.class_hid = BNXT_ULP_CLASS_HID_14a93,
+	.class_hid = BNXT_ULP_CLASS_HID_28e37,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 655368UL,
@@ -3842,7 +4450,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[139] = {
-	.class_hid = BNXT_ULP_CLASS_HID_105f7,
+	.class_hid = BNXT_ULP_CLASS_HID_28f7d,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 655424UL,
@@ -3861,7 +4469,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[140] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1368f,
+	.class_hid = BNXT_ULP_CLASS_HID_29b97,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 655432UL,
@@ -3881,7 +4489,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[141] = {
-	.class_hid = BNXT_ULP_CLASS_HID_139c7,
+	.class_hid = BNXT_ULP_CLASS_HID_68491,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 720896UL,
@@ -3900,7 +4508,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[142] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1022b,
+	.class_hid = BNXT_ULP_CLASS_HID_6908b,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 720904UL,
@@ -3920,7 +4528,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[143] = {
-	.class_hid = BNXT_ULP_CLASS_HID_125f3,
+	.class_hid = BNXT_ULP_CLASS_HID_691f1,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 720960UL,
@@ -3940,7 +4548,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[144] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1568b,
+	.class_hid = BNXT_ULP_CLASS_HID_69deb,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 720968UL,
@@ -3961,7 +4569,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[145] = {
-	.class_hid = BNXT_ULP_CLASS_HID_33c37,
+	.class_hid = BNXT_ULP_CLASS_HID_3926d,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 917504UL,
@@ -3980,7 +4588,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[146] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3041b,
+	.class_hid = BNXT_ULP_CLASS_HID_39e87,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 917512UL,
@@ -4000,7 +4608,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[147] = {
-	.class_hid = BNXT_ULP_CLASS_HID_32823,
+	.class_hid = BNXT_ULP_CLASS_HID_38023,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 917568UL,
@@ -4020,7 +4628,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[148] = {
-	.class_hid = BNXT_ULP_CLASS_HID_358fb,
+	.class_hid = BNXT_ULP_CLASS_HID_38c45,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 917576UL,
@@ -4041,7 +4649,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[149] = {
-	.class_hid = BNXT_ULP_CLASS_HID_35c33,
+	.class_hid = BNXT_ULP_CLASS_HID_794e1,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 983040UL,
@@ -4061,7 +4669,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[150] = {
-	.class_hid = BNXT_ULP_CLASS_HID_32407,
+	.class_hid = BNXT_ULP_CLASS_HID_78179,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 983048UL,
@@ -4082,7 +4690,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[151] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3482f,
+	.class_hid = BNXT_ULP_CLASS_HID_782a7,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 983104UL,
@@ -4103,7 +4711,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[152] = {
-	.class_hid = BNXT_ULP_CLASS_HID_31033,
+	.class_hid = BNXT_ULP_CLASS_HID_78ed9,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 983112UL,
@@ -4125,7 +4733,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[153] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3887,
+	.class_hid = BNXT_ULP_CLASS_HID_81d05,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 32768UL,
@@ -4142,7 +4750,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[154] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00bb,
+	.class_hid = BNXT_ULP_CLASS_HID_8098d,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 32776UL,
@@ -4160,7 +4768,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[155] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2493,
+	.class_hid = BNXT_ULP_CLASS_HID_80ac3,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 32832UL,
@@ -4178,7 +4786,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[156] = {
-	.class_hid = BNXT_ULP_CLASS_HID_55db,
+	.class_hid = BNXT_ULP_CLASS_HID_8172d,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 32840UL,
@@ -4197,7 +4805,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[157] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5043,
+	.class_hid = BNXT_ULP_CLASS_HID_80753,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 49152UL,
@@ -4215,7 +4823,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[158] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1877,
+	.class_hid = BNXT_ULP_CLASS_HID_813bd,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 49160UL,
@@ -4234,7 +4842,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[159] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3baf,
+	.class_hid = BNXT_ULP_CLASS_HID_814f3,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 49216UL,
@@ -4253,7 +4861,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[160] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0443,
+	.class_hid = BNXT_ULP_CLASS_HID_8017b,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 49224UL,
@@ -4273,7 +4881,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[161] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5883,
+	.class_hid = BNXT_ULP_CLASS_HID_c002f,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 98304UL,
@@ -4291,7 +4899,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[162] = {
-	.class_hid = BNXT_ULP_CLASS_HID_20b7,
+	.class_hid = BNXT_ULP_CLASS_HID_c0c09,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 98312UL,
@@ -4310,7 +4918,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[163] = {
-	.class_hid = BNXT_ULP_CLASS_HID_44ef,
+	.class_hid = BNXT_ULP_CLASS_HID_c0d4f,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 98368UL,
@@ -4329,7 +4937,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[164] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0c83,
+	.class_hid = BNXT_ULP_CLASS_HID_c19a9,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 98376UL,
@@ -4349,7 +4957,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[165] = {
-	.class_hid = BNXT_ULP_CLASS_HID_070b,
+	.class_hid = BNXT_ULP_CLASS_HID_c09df,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 114688UL,
@@ -4368,7 +4976,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[166] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3873,
+	.class_hid = BNXT_ULP_CLASS_HID_c1639,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 114696UL,
@@ -4388,7 +4996,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[167] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5bab,
+	.class_hid = BNXT_ULP_CLASS_HID_c177f,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 114752UL,
@@ -4408,7 +5016,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[168] = {
-	.class_hid = BNXT_ULP_CLASS_HID_245f,
+	.class_hid = BNXT_ULP_CLASS_HID_c03e7,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 114760UL,
@@ -4429,7 +5037,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[169] = {
-	.class_hid = BNXT_ULP_CLASS_HID_142b,
+	.class_hid = BNXT_ULP_CLASS_HID_a1e43,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 163840UL,
@@ -4447,7 +5055,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[170] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4513,
+	.class_hid = BNXT_ULP_CLASS_HID_a0acb,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 163848UL,
@@ -4466,7 +5074,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[171] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0037,
+	.class_hid = BNXT_ULP_CLASS_HID_a0c01,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 163904UL,
@@ -4485,7 +5093,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[172] = {
-	.class_hid = BNXT_ULP_CLASS_HID_317f,
+	.class_hid = BNXT_ULP_CLASS_HID_a186b,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 163912UL,
@@ -4505,7 +5113,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[173] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2be7,
+	.class_hid = BNXT_ULP_CLASS_HID_a0891,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 180224UL,
@@ -4524,7 +5132,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[174] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5c2f,
+	.class_hid = BNXT_ULP_CLASS_HID_a14fb,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 180232UL,
@@ -4544,7 +5152,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[175] = {
-	.class_hid = BNXT_ULP_CLASS_HID_17f3,
+	.class_hid = BNXT_ULP_CLASS_HID_a1631,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 180288UL,
@@ -4564,7 +5172,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[176] = {
-	.class_hid = BNXT_ULP_CLASS_HID_483b,
+	.class_hid = BNXT_ULP_CLASS_HID_a02b9,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 180296UL,
@@ -4585,7 +5193,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[177] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3427,
+	.class_hid = BNXT_ULP_CLASS_HID_e016d,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 229376UL,
@@ -4604,7 +5212,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[178] = {
-	.class_hid = BNXT_ULP_CLASS_HID_656f,
+	.class_hid = BNXT_ULP_CLASS_HID_e0d77,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 229384UL,
@@ -4624,7 +5232,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[179] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2033,
+	.class_hid = BNXT_ULP_CLASS_HID_e0e8d,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 229440UL,
@@ -4644,7 +5252,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[180] = {
-	.class_hid = BNXT_ULP_CLASS_HID_517b,
+	.class_hid = BNXT_ULP_CLASS_HID_e1a97,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 229448UL,
@@ -4665,7 +5273,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[181] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4be3,
+	.class_hid = BNXT_ULP_CLASS_HID_e0b1d,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 245760UL,
@@ -4685,7 +5293,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[182] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1397,
+	.class_hid = BNXT_ULP_CLASS_HID_e1767,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 245768UL,
@@ -4706,7 +5314,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[183] = {
-	.class_hid = BNXT_ULP_CLASS_HID_37cf,
+	.class_hid = BNXT_ULP_CLASS_HID_e18bd,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 245824UL,
@@ -4727,7 +5335,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[184] = {
-	.class_hid = BNXT_ULP_CLASS_HID_6837,
+	.class_hid = BNXT_ULP_CLASS_HID_e0525,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 245832UL,
@@ -4749,7 +5357,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[185] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3d7f,
+	.class_hid = BNXT_ULP_CLASS_HID_21957,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 131072UL,
@@ -4766,7 +5374,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[186] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0503,
+	.class_hid = BNXT_ULP_CLASS_HID_205cf,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 131080UL,
@@ -4784,7 +5392,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[187] = {
-	.class_hid = BNXT_ULP_CLASS_HID_296b,
+	.class_hid = BNXT_ULP_CLASS_HID_20715,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 131136UL,
@@ -4802,7 +5410,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[188] = {
-	.class_hid = BNXT_ULP_CLASS_HID_59a3,
+	.class_hid = BNXT_ULP_CLASS_HID_2136f,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 131144UL,
@@ -4821,7 +5429,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[189] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5d7b,
+	.class_hid = BNXT_ULP_CLASS_HID_61bcb,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 196608UL,
@@ -4839,7 +5447,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[190] = {
-	.class_hid = BNXT_ULP_CLASS_HID_250f,
+	.class_hid = BNXT_ULP_CLASS_HID_60843,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 196616UL,
@@ -4858,7 +5466,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[191] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4957,
+	.class_hid = BNXT_ULP_CLASS_HID_60989,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 196672UL,
@@ -4877,7 +5485,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[192] = {
-	.class_hid = BNXT_ULP_CLASS_HID_117b,
+	.class_hid = BNXT_ULP_CLASS_HID_615e3,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 196680UL,
@@ -4897,7 +5505,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[193] = {
-	.class_hid = BNXT_ULP_CLASS_HID_25f2b,
+	.class_hid = BNXT_ULP_CLASS_HID_30a65,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 393216UL,
@@ -4915,7 +5523,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[194] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2273f,
+	.class_hid = BNXT_ULP_CLASS_HID_3167f,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 393224UL,
@@ -4934,7 +5542,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[195] = {
-	.class_hid = BNXT_ULP_CLASS_HID_24b07,
+	.class_hid = BNXT_ULP_CLASS_HID_31785,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 393280UL,
@@ -4953,7 +5561,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[196] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2132b,
+	.class_hid = BNXT_ULP_CLASS_HID_3043d,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 393288UL,
@@ -4973,7 +5581,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[197] = {
-	.class_hid = BNXT_ULP_CLASS_HID_216e3,
+	.class_hid = BNXT_ULP_CLASS_HID_70c99,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 458752UL,
@@ -4992,7 +5600,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[198] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2473b,
+	.class_hid = BNXT_ULP_CLASS_HID_718f3,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 458760UL,
@@ -5012,7 +5620,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[199] = {
-	.class_hid = BNXT_ULP_CLASS_HID_202df,
+	.class_hid = BNXT_ULP_CLASS_HID_71a39,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 458816UL,
@@ -5032,7 +5640,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[200] = {
-	.class_hid = BNXT_ULP_CLASS_HID_23317,
+	.class_hid = BNXT_ULP_CLASS_HID_706b1,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 458824UL,
@@ -5053,7 +5661,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[201] = {
-	.class_hid = BNXT_ULP_CLASS_HID_119bb,
+	.class_hid = BNXT_ULP_CLASS_HID_2822d,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 655360UL,
@@ -5071,7 +5679,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[202] = {
-	.class_hid = BNXT_ULP_CLASS_HID_14af3,
+	.class_hid = BNXT_ULP_CLASS_HID_28e07,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 655368UL,
@@ -5090,7 +5698,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[203] = {
-	.class_hid = BNXT_ULP_CLASS_HID_10597,
+	.class_hid = BNXT_ULP_CLASS_HID_28f4d,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 655424UL,
@@ -5109,7 +5717,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[204] = {
-	.class_hid = BNXT_ULP_CLASS_HID_136ef,
+	.class_hid = BNXT_ULP_CLASS_HID_29ba7,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 655432UL,
@@ -5129,7 +5737,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[205] = {
-	.class_hid = BNXT_ULP_CLASS_HID_139a7,
+	.class_hid = BNXT_ULP_CLASS_HID_684a1,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 720896UL,
@@ -5148,7 +5756,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[206] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1024b,
+	.class_hid = BNXT_ULP_CLASS_HID_690bb,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 720904UL,
@@ -5168,7 +5776,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[207] = {
-	.class_hid = BNXT_ULP_CLASS_HID_12593,
+	.class_hid = BNXT_ULP_CLASS_HID_691c1,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 720960UL,
@@ -5188,7 +5796,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[208] = {
-	.class_hid = BNXT_ULP_CLASS_HID_156eb,
+	.class_hid = BNXT_ULP_CLASS_HID_69ddb,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 720968UL,
@@ -5209,7 +5817,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[209] = {
-	.class_hid = BNXT_ULP_CLASS_HID_33c57,
+	.class_hid = BNXT_ULP_CLASS_HID_3925d,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 917504UL,
@@ -5228,7 +5836,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[210] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3047b,
+	.class_hid = BNXT_ULP_CLASS_HID_39eb7,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 917512UL,
@@ -5248,7 +5856,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[211] = {
-	.class_hid = BNXT_ULP_CLASS_HID_32843,
+	.class_hid = BNXT_ULP_CLASS_HID_38013,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 917568UL,
@@ -5268,7 +5876,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[212] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3589b,
+	.class_hid = BNXT_ULP_CLASS_HID_38c75,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 917576UL,
@@ -5289,7 +5897,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[213] = {
-	.class_hid = BNXT_ULP_CLASS_HID_35c53,
+	.class_hid = BNXT_ULP_CLASS_HID_794d1,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 983040UL,
@@ -5309,7 +5917,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[214] = {
-	.class_hid = BNXT_ULP_CLASS_HID_32467,
+	.class_hid = BNXT_ULP_CLASS_HID_78149,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 983048UL,
@@ -5330,7 +5938,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[215] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3484f,
+	.class_hid = BNXT_ULP_CLASS_HID_78297,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 983104UL,
@@ -5351,7 +5959,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[216] = {
-	.class_hid = BNXT_ULP_CLASS_HID_31053,
+	.class_hid = BNXT_ULP_CLASS_HID_78ee9,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 983112UL,
@@ -5373,7 +5981,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[217] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5ce1,
+	.class_hid = BNXT_ULP_CLASS_HID_0816,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
 	.flow_sig_id = 4096UL,
@@ -5387,7 +5995,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[218] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4579,
+	.class_hid = BNXT_ULP_CLASS_HID_1852,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
 	.flow_sig_id = 6144UL,
@@ -5402,7 +6010,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[219] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1735,
+	.class_hid = BNXT_ULP_CLASS_HID_09f4,
 	.class_tid = 1,
 	.hdr_sig_id = 1,
 	.flow_sig_id = 16384UL,
@@ -5416,7 +6024,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[220] = {
-	.class_hid = BNXT_ULP_CLASS_HID_45bd,
+	.class_hid = BNXT_ULP_CLASS_HID_1dd4,
 	.class_tid = 1,
 	.hdr_sig_id = 1,
 	.flow_sig_id = 24576UL,
@@ -5431,7 +6039,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[221] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3feb,
+	.class_hid = BNXT_ULP_CLASS_HID_804f1,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 32768UL,
@@ -5446,7 +6054,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[222] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2bf7,
+	.class_hid = BNXT_ULP_CLASS_HID_81251,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 32832UL,
@@ -5462,7 +6070,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[223] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5727,
+	.class_hid = BNXT_ULP_CLASS_HID_80ee1,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 49152UL,
@@ -5478,7 +6086,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[224] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4333,
+	.class_hid = BNXT_ULP_CLASS_HID_81c41,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 49216UL,
@@ -5495,7 +6103,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[225] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4453,
+	.class_hid = BNXT_ULP_CLASS_HID_2013b,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 131072UL,
@@ -5510,7 +6118,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[226] = {
-	.class_hid = BNXT_ULP_CLASS_HID_304f,
+	.class_hid = BNXT_ULP_CLASS_HID_20e9b,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 131136UL,
@@ -5526,7 +6134,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[227] = {
-	.class_hid = BNXT_ULP_CLASS_HID_645f,
+	.class_hid = BNXT_ULP_CLASS_HID_603bf,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 196608UL,
@@ -5542,7 +6150,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[228] = {
-	.class_hid = BNXT_ULP_CLASS_HID_504b,
+	.class_hid = BNXT_ULP_CLASS_HID_6111f,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 196672UL,
@@ -5559,7 +6167,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[229] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5cc1,
+	.class_hid = BNXT_ULP_CLASS_HID_0806,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 4096UL,
@@ -5574,7 +6182,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[230] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4559,
+	.class_hid = BNXT_ULP_CLASS_HID_1842,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 6144UL,
@@ -5590,7 +6198,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[231] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2285,
+	.class_hid = BNXT_ULP_CLASS_HID_1be6,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 12288UL,
@@ -5606,7 +6214,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
 	},
 	[232] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0b1d,
+	.class_hid = BNXT_ULP_CLASS_HID_0c80,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 14336UL,
@@ -5623,7 +6231,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
 	},
 	[233] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0b49,
+	.class_hid = BNXT_ULP_CLASS_HID_1216,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 20480UL,
@@ -5639,7 +6247,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[234] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5c95,
+	.class_hid = BNXT_ULP_CLASS_HID_02b0,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 22528UL,
@@ -5656,7 +6264,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[235] = {
-	.class_hid = BNXT_ULP_CLASS_HID_39c1,
+	.class_hid = BNXT_ULP_CLASS_HID_0654,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 28672UL,
@@ -5673,7 +6281,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[236] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2259,
+	.class_hid = BNXT_ULP_CLASS_HID_1690,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 30720UL,
@@ -5691,7 +6299,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
 	},
 	[237] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1715,
+	.class_hid = BNXT_ULP_CLASS_HID_09e4,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 16384UL,
@@ -5706,7 +6314,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[238] = {
-	.class_hid = BNXT_ULP_CLASS_HID_459d,
+	.class_hid = BNXT_ULP_CLASS_HID_1dc4,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 24576UL,
@@ -5722,7 +6330,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[239] = {
-	.class_hid = BNXT_ULP_CLASS_HID_571d,
+	.class_hid = BNXT_ULP_CLASS_HID_80efc,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 49152UL,
@@ -5738,7 +6346,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
 	},
 	[240] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1cd1,
+	.class_hid = BNXT_ULP_CLASS_HID_80332,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 57344UL,
@@ -5755,7 +6363,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
 	},
 	[241] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3711,
+	.class_hid = BNXT_ULP_CLASS_HID_40c78,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 81920UL,
@@ -5771,7 +6379,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[242] = {
-	.class_hid = BNXT_ULP_CLASS_HID_6599,
+	.class_hid = BNXT_ULP_CLASS_HID_400be,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 90112UL,
@@ -5788,7 +6396,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[243] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0e55,
+	.class_hid = BNXT_ULP_CLASS_HID_c1170,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 114688UL,
@@ -5805,7 +6413,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[244] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3cdd,
+	.class_hid = BNXT_ULP_CLASS_HID_c05b6,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 122880UL,
@@ -5823,7 +6431,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
 	},
 	[245] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5ca1,
+	.class_hid = BNXT_ULP_CLASS_HID_0836,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 4096UL,
@@ -5838,7 +6446,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[246] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4539,
+	.class_hid = BNXT_ULP_CLASS_HID_1872,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 6144UL,
@@ -5854,7 +6462,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[247] = {
-	.class_hid = BNXT_ULP_CLASS_HID_22e5,
+	.class_hid = BNXT_ULP_CLASS_HID_1bd6,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 12288UL,
@@ -5870,7 +6478,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
 	},
 	[248] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0b7d,
+	.class_hid = BNXT_ULP_CLASS_HID_0cb0,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 14336UL,
@@ -5887,7 +6495,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
 	},
 	[249] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0b29,
+	.class_hid = BNXT_ULP_CLASS_HID_1226,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 20480UL,
@@ -5903,7 +6511,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[250] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5cf5,
+	.class_hid = BNXT_ULP_CLASS_HID_0280,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 22528UL,
@@ -5920,7 +6528,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[251] = {
-	.class_hid = BNXT_ULP_CLASS_HID_39a1,
+	.class_hid = BNXT_ULP_CLASS_HID_0664,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 28672UL,
@@ -5937,7 +6545,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[252] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2239,
+	.class_hid = BNXT_ULP_CLASS_HID_16a0,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 30720UL,
@@ -5955,7 +6563,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
 	},
 	[253] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1775,
+	.class_hid = BNXT_ULP_CLASS_HID_09d4,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 16384UL,
@@ -5970,7 +6578,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[254] = {
-	.class_hid = BNXT_ULP_CLASS_HID_45fd,
+	.class_hid = BNXT_ULP_CLASS_HID_1df4,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 24576UL,
@@ -5986,7 +6594,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[255] = {
-	.class_hid = BNXT_ULP_CLASS_HID_577d,
+	.class_hid = BNXT_ULP_CLASS_HID_80ecc,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 49152UL,
@@ -6002,7 +6610,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
 	},
 	[256] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1cb1,
+	.class_hid = BNXT_ULP_CLASS_HID_80302,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 57344UL,
@@ -6019,7 +6627,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
 	},
 	[257] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3771,
+	.class_hid = BNXT_ULP_CLASS_HID_40c48,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 81920UL,
@@ -6035,7 +6643,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[258] = {
-	.class_hid = BNXT_ULP_CLASS_HID_65f9,
+	.class_hid = BNXT_ULP_CLASS_HID_4008e,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 90112UL,
@@ -6052,7 +6660,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[259] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0e35,
+	.class_hid = BNXT_ULP_CLASS_HID_c1140,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 114688UL,
@@ -6069,7 +6677,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[260] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3cbd,
+	.class_hid = BNXT_ULP_CLASS_HID_c0586,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 122880UL,
@@ -6087,7 +6695,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
 	},
 	[261] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3fcb,
+	.class_hid = BNXT_ULP_CLASS_HID_804e1,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 32768UL,
@@ -6103,7 +6711,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[262] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2bd7,
+	.class_hid = BNXT_ULP_CLASS_HID_81241,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 32832UL,
@@ -6120,7 +6728,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[263] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5707,
+	.class_hid = BNXT_ULP_CLASS_HID_80ef1,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 49152UL,
@@ -6137,7 +6745,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[264] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4313,
+	.class_hid = BNXT_ULP_CLASS_HID_81c51,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 49216UL,
@@ -6155,7 +6763,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[265] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5fc7,
+	.class_hid = BNXT_ULP_CLASS_HID_c076d,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 98304UL,
@@ -6172,7 +6780,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[266] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4bd3,
+	.class_hid = BNXT_ULP_CLASS_HID_c14cd,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 98368UL,
@@ -6190,7 +6798,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[267] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0e4f,
+	.class_hid = BNXT_ULP_CLASS_HID_c117d,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 114688UL,
@@ -6208,7 +6816,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[268] = {
-	.class_hid = BNXT_ULP_CLASS_HID_632f,
+	.class_hid = BNXT_ULP_CLASS_HID_c1edd,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 114752UL,
@@ -6227,7 +6835,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
 	},
 	[269] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1baf,
+	.class_hid = BNXT_ULP_CLASS_HID_a062f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 163840UL,
@@ -6244,7 +6852,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[270] = {
-	.class_hid = BNXT_ULP_CLASS_HID_07bb,
+	.class_hid = BNXT_ULP_CLASS_HID_a138f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 163904UL,
@@ -6262,7 +6870,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[271] = {
-	.class_hid = BNXT_ULP_CLASS_HID_32eb,
+	.class_hid = BNXT_ULP_CLASS_HID_a103f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 180224UL,
@@ -6280,7 +6888,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[272] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1ef7,
+	.class_hid = BNXT_ULP_CLASS_HID_a1d9f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 180288UL,
@@ -6299,7 +6907,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[273] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3bab,
+	.class_hid = BNXT_ULP_CLASS_HID_e08ab,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 229376UL,
@@ -6317,7 +6925,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[274] = {
-	.class_hid = BNXT_ULP_CLASS_HID_27b7,
+	.class_hid = BNXT_ULP_CLASS_HID_e160b,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 229440UL,
@@ -6336,7 +6944,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[275] = {
-	.class_hid = BNXT_ULP_CLASS_HID_52e7,
+	.class_hid = BNXT_ULP_CLASS_HID_e12bb,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 245760UL,
@@ -6355,7 +6963,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[276] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3ef3,
+	.class_hid = BNXT_ULP_CLASS_HID_e0079,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 245824UL,
@@ -6375,7 +6983,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
 	},
 	[277] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4473,
+	.class_hid = BNXT_ULP_CLASS_HID_2012b,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 131072UL,
@@ -6391,7 +6999,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[278] = {
-	.class_hid = BNXT_ULP_CLASS_HID_306f,
+	.class_hid = BNXT_ULP_CLASS_HID_20e8b,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 131136UL,
@@ -6408,7 +7016,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[279] = {
-	.class_hid = BNXT_ULP_CLASS_HID_647f,
+	.class_hid = BNXT_ULP_CLASS_HID_603af,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 196608UL,
@@ -6425,7 +7033,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[280] = {
-	.class_hid = BNXT_ULP_CLASS_HID_506b,
+	.class_hid = BNXT_ULP_CLASS_HID_6110f,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 196672UL,
@@ -6443,7 +7051,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[281] = {
-	.class_hid = BNXT_ULP_CLASS_HID_266af,
+	.class_hid = BNXT_ULP_CLASS_HID_311bb,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 393216UL,
@@ -6460,7 +7068,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[282] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2525b,
+	.class_hid = BNXT_ULP_CLASS_HID_31f1b,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 393280UL,
@@ -6478,7 +7086,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[283] = {
-	.class_hid = BNXT_ULP_CLASS_HID_21de7,
+	.class_hid = BNXT_ULP_CLASS_HID_7143f,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 458752UL,
@@ -6496,7 +7104,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[284] = {
-	.class_hid = BNXT_ULP_CLASS_HID_20993,
+	.class_hid = BNXT_ULP_CLASS_HID_701fd,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 458816UL,
@@ -6515,7 +7123,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
 	},
 	[285] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1213f,
+	.class_hid = BNXT_ULP_CLASS_HID_28963,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 655360UL,
@@ -6532,7 +7140,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[286] = {
-	.class_hid = BNXT_ULP_CLASS_HID_10d2b,
+	.class_hid = BNXT_ULP_CLASS_HID_296c3,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 655424UL,
@@ -6550,7 +7158,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[287] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1413b,
+	.class_hid = BNXT_ULP_CLASS_HID_68be7,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 720896UL,
@@ -6568,7 +7176,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[288] = {
-	.class_hid = BNXT_ULP_CLASS_HID_12cd7,
+	.class_hid = BNXT_ULP_CLASS_HID_69947,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 720960UL,
@@ -6587,7 +7195,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[289] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3436b,
+	.class_hid = BNXT_ULP_CLASS_HID_399f3,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 917504UL,
@@ -6605,7 +7213,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[290] = {
-	.class_hid = BNXT_ULP_CLASS_HID_32f07,
+	.class_hid = BNXT_ULP_CLASS_HID_387b1,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 917568UL,
@@ -6624,7 +7232,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[291] = {
-	.class_hid = BNXT_ULP_CLASS_HID_36317,
+	.class_hid = BNXT_ULP_CLASS_HID_79c77,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 983040UL,
@@ -6643,7 +7251,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[292] = {
-	.class_hid = BNXT_ULP_CLASS_HID_34f03,
+	.class_hid = BNXT_ULP_CLASS_HID_78a35,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 983104UL,
@@ -6663,7 +7271,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
 	},
 	[293] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3fab,
+	.class_hid = BNXT_ULP_CLASS_HID_804d1,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 32768UL,
@@ -6679,7 +7287,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[294] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2bb7,
+	.class_hid = BNXT_ULP_CLASS_HID_81271,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 32832UL,
@@ -6696,7 +7304,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[295] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5767,
+	.class_hid = BNXT_ULP_CLASS_HID_80ec1,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 49152UL,
@@ -6713,7 +7321,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[296] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4373,
+	.class_hid = BNXT_ULP_CLASS_HID_81c61,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 49216UL,
@@ -6731,7 +7339,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
 	},
 	[297] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5fa7,
+	.class_hid = BNXT_ULP_CLASS_HID_c075d,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 98304UL,
@@ -6748,7 +7356,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[298] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4bb3,
+	.class_hid = BNXT_ULP_CLASS_HID_c14fd,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 98368UL,
@@ -6766,7 +7374,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[299] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0e2f,
+	.class_hid = BNXT_ULP_CLASS_HID_c114d,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 114688UL,
@@ -6784,7 +7392,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[300] = {
-	.class_hid = BNXT_ULP_CLASS_HID_634f,
+	.class_hid = BNXT_ULP_CLASS_HID_c1eed,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 114752UL,
@@ -6803,7 +7411,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
 	},
 	[301] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1bcf,
+	.class_hid = BNXT_ULP_CLASS_HID_a061f,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 163840UL,
@@ -6820,7 +7428,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[302] = {
-	.class_hid = BNXT_ULP_CLASS_HID_07db,
+	.class_hid = BNXT_ULP_CLASS_HID_a13bf,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 163904UL,
@@ -6838,7 +7446,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[303] = {
-	.class_hid = BNXT_ULP_CLASS_HID_328b,
+	.class_hid = BNXT_ULP_CLASS_HID_a100f,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 180224UL,
@@ -6856,7 +7464,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[304] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1e97,
+	.class_hid = BNXT_ULP_CLASS_HID_a1daf,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 180288UL,
@@ -6875,7 +7483,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[305] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3bcb,
+	.class_hid = BNXT_ULP_CLASS_HID_e089b,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 229376UL,
@@ -6893,7 +7501,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[306] = {
-	.class_hid = BNXT_ULP_CLASS_HID_27d7,
+	.class_hid = BNXT_ULP_CLASS_HID_e163b,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 229440UL,
@@ -6912,7 +7520,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[307] = {
-	.class_hid = BNXT_ULP_CLASS_HID_5287,
+	.class_hid = BNXT_ULP_CLASS_HID_e128b,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 245760UL,
@@ -6931,7 +7539,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[308] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3e93,
+	.class_hid = BNXT_ULP_CLASS_HID_e0049,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 245824UL,
@@ -6951,7 +7559,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
 	},
 	[309] = {
-	.class_hid = BNXT_ULP_CLASS_HID_4413,
+	.class_hid = BNXT_ULP_CLASS_HID_2011b,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 131072UL,
@@ -6967,7 +7575,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[310] = {
-	.class_hid = BNXT_ULP_CLASS_HID_300f,
+	.class_hid = BNXT_ULP_CLASS_HID_20ebb,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 131136UL,
@@ -6984,7 +7592,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[311] = {
-	.class_hid = BNXT_ULP_CLASS_HID_641f,
+	.class_hid = BNXT_ULP_CLASS_HID_6039f,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 196608UL,
@@ -7001,7 +7609,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[312] = {
-	.class_hid = BNXT_ULP_CLASS_HID_500b,
+	.class_hid = BNXT_ULP_CLASS_HID_6113f,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 196672UL,
@@ -7019,7 +7627,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[313] = {
-	.class_hid = BNXT_ULP_CLASS_HID_266cf,
+	.class_hid = BNXT_ULP_CLASS_HID_3118b,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 393216UL,
@@ -7036,7 +7644,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[314] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2523b,
+	.class_hid = BNXT_ULP_CLASS_HID_31f2b,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 393280UL,
@@ -7054,7 +7662,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[315] = {
-	.class_hid = BNXT_ULP_CLASS_HID_21d87,
+	.class_hid = BNXT_ULP_CLASS_HID_7140f,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 458752UL,
@@ -7072,7 +7680,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[316] = {
-	.class_hid = BNXT_ULP_CLASS_HID_209f3,
+	.class_hid = BNXT_ULP_CLASS_HID_701cd,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 458816UL,
@@ -7091,7 +7699,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
 	},
 	[317] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1215f,
+	.class_hid = BNXT_ULP_CLASS_HID_28953,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 655360UL,
@@ -7108,7 +7716,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[318] = {
-	.class_hid = BNXT_ULP_CLASS_HID_10d4b,
+	.class_hid = BNXT_ULP_CLASS_HID_296f3,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 655424UL,
@@ -7126,7 +7734,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[319] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1415b,
+	.class_hid = BNXT_ULP_CLASS_HID_68bd7,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 720896UL,
@@ -7144,7 +7752,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[320] = {
-	.class_hid = BNXT_ULP_CLASS_HID_12cb7,
+	.class_hid = BNXT_ULP_CLASS_HID_69977,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 720960UL,
@@ -7163,7 +7771,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[321] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3430b,
+	.class_hid = BNXT_ULP_CLASS_HID_399c3,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 917504UL,
@@ -7181,7 +7789,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[322] = {
-	.class_hid = BNXT_ULP_CLASS_HID_32f67,
+	.class_hid = BNXT_ULP_CLASS_HID_38781,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 917568UL,
@@ -7200,7 +7808,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[323] = {
-	.class_hid = BNXT_ULP_CLASS_HID_36377,
+	.class_hid = BNXT_ULP_CLASS_HID_79c47,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 983040UL,
@@ -7219,7 +7827,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[324] = {
-	.class_hid = BNXT_ULP_CLASS_HID_34f63,
+	.class_hid = BNXT_ULP_CLASS_HID_78a05,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 983104UL,
@@ -7239,7 +7847,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
 	},
 	[325] = {
-	.class_hid = BNXT_ULP_CLASS_HID_29b5,
+	.class_hid = BNXT_ULP_CLASS_HID_04a4,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
 	.flow_sig_id = 8UL,
@@ -7254,7 +7862,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_SMAC }
 	},
 	[326] = {
-	.class_hid = BNXT_ULP_CLASS_HID_29ad,
+	.class_hid = BNXT_ULP_CLASS_HID_04a8,
 	.class_tid = 1,
 	.hdr_sig_id = 1,
 	.flow_sig_id = 8UL,
@@ -7269,7 +7877,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_SMAC }
 	},
 	[327] = {
-	.class_hid = BNXT_ULP_CLASS_HID_29b7,
+	.class_hid = BNXT_ULP_CLASS_HID_04a5,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 8UL,
@@ -7285,7 +7893,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC }
 	},
 	[328] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1583,
+	.class_hid = BNXT_ULP_CLASS_HID_1205,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
 	.flow_sig_id = 72UL,
@@ -7302,7 +7910,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID }
 	},
 	[329] = {
-	.class_hid = BNXT_ULP_CLASS_HID_29af,
+	.class_hid = BNXT_ULP_CLASS_HID_04a9,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 8UL,
@@ -7318,7 +7926,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC }
 	},
 	[330] = {
-	.class_hid = BNXT_ULP_CLASS_HID_159b,
+	.class_hid = BNXT_ULP_CLASS_HID_1209,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
 	.flow_sig_id = 72UL,
@@ -7335,7 +7943,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID }
 	},
 	[331] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2995,
+	.class_hid = BNXT_ULP_CLASS_HID_04b4,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
 	.flow_sig_id = 8UL,
@@ -7351,7 +7959,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC }
 	},
 	[332] = {
-	.class_hid = BNXT_ULP_CLASS_HID_298d,
+	.class_hid = BNXT_ULP_CLASS_HID_04b8,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
 	.flow_sig_id = 8UL,
@@ -7367,7 +7975,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC }
 	},
 	[333] = {
-	.class_hid = BNXT_ULP_CLASS_HID_29f5,
+	.class_hid = BNXT_ULP_CLASS_HID_0484,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
 	.flow_sig_id = 8UL,
@@ -7383,7 +7991,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC }
 	},
 	[334] = {
-	.class_hid = BNXT_ULP_CLASS_HID_29ed,
+	.class_hid = BNXT_ULP_CLASS_HID_0488,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
 	.flow_sig_id = 8UL,
@@ -7399,7 +8007,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC }
 	},
 	[335] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2997,
+	.class_hid = BNXT_ULP_CLASS_HID_04b5,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 8UL,
@@ -7416,7 +8024,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC }
 	},
 	[336] = {
-	.class_hid = BNXT_ULP_CLASS_HID_15a3,
+	.class_hid = BNXT_ULP_CLASS_HID_1215,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
 	.flow_sig_id = 72UL,
@@ -7434,7 +8042,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID }
 	},
 	[337] = {
-	.class_hid = BNXT_ULP_CLASS_HID_298f,
+	.class_hid = BNXT_ULP_CLASS_HID_04b9,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 8UL,
@@ -7451,7 +8059,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC }
 	},
 	[338] = {
-	.class_hid = BNXT_ULP_CLASS_HID_15bb,
+	.class_hid = BNXT_ULP_CLASS_HID_1219,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
 	.flow_sig_id = 72UL,
@@ -7469,7 +8077,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID }
 	},
 	[339] = {
-	.class_hid = BNXT_ULP_CLASS_HID_29f7,
+	.class_hid = BNXT_ULP_CLASS_HID_0485,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 8UL,
@@ -7486,7 +8094,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC }
 	},
 	[340] = {
-	.class_hid = BNXT_ULP_CLASS_HID_15c3,
+	.class_hid = BNXT_ULP_CLASS_HID_1225,
 	.class_tid = 1,
 	.hdr_sig_id = 10,
 	.flow_sig_id = 72UL,
@@ -7504,7 +8112,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID }
 	},
 	[341] = {
-	.class_hid = BNXT_ULP_CLASS_HID_29ef,
+	.class_hid = BNXT_ULP_CLASS_HID_0489,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 8UL,
@@ -7521,7 +8129,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC }
 	},
 	[342] = {
-	.class_hid = BNXT_ULP_CLASS_HID_15db,
+	.class_hid = BNXT_ULP_CLASS_HID_1229,
 	.class_tid = 1,
 	.hdr_sig_id = 11,
 	.flow_sig_id = 72UL,
@@ -7539,7 +8147,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID }
 	},
 	[343] = {
-	.class_hid = BNXT_ULP_CLASS_HID_1151,
+	.class_hid = BNXT_ULP_CLASS_HID_0226,
 	.class_tid = 1,
 	.hdr_sig_id = 12,
 	.flow_sig_id = 16384UL,
@@ -7556,7 +8164,7 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_DST_ADDR }
 	},
 	[344] = {
-	.class_hid = BNXT_ULP_CLASS_HID_315d,
+	.class_hid = BNXT_ULP_CLASS_HID_4045a,
 	.class_tid = 1,
 	.hdr_sig_id = 12,
 	.flow_sig_id = 81920UL,
@@ -7574,776 +8182,776 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT }
 	},
 	[345] = {
-	.class_hid = BNXT_ULP_CLASS_HID_3612,
+	.class_hid = BNXT_ULP_CLASS_HID_0daa,
 	.class_tid = 2,
 	.hdr_sig_id = 0,
-	.flow_sig_id = 81920UL,
+	.flow_sig_id = 20480UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
 	},
 	[346] = {
-	.class_hid = BNXT_ULP_CLASS_HID_66da,
+	.class_hid = BNXT_ULP_CLASS_HID_11b0,
 	.class_tid = 2,
 	.hdr_sig_id = 0,
-	.flow_sig_id = 81928UL,
+	.flow_sig_id = 20488UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
 	},
 	[347] = {
-	.class_hid = BNXT_ULP_CLASS_HID_243ca,
+	.class_hid = BNXT_ULP_CLASS_HID_403f8,
 	.class_tid = 2,
 	.hdr_sig_id = 1,
-	.flow_sig_id = 265216UL,
-	.flow_pattern_id = 1,
+	.flow_sig_id = 81920UL,
+	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
+		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
-		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI }
+		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT }
 	},
 	[348] = {
-	.class_hid = BNXT_ULP_CLASS_HID_20d8e,
+	.class_hid = BNXT_ULP_CLASS_HID_4161e,
 	.class_tid = 2,
 	.hdr_sig_id = 1,
-	.flow_sig_id = 273408UL,
-	.flow_pattern_id = 1,
+	.flow_sig_id = 81928UL,
+	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
+		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
-		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI }
+		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT }
 	},
 	[349] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2e082,
+	.class_hid = BNXT_ULP_CLASS_HID_40439,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1313792UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 66304UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
 	},
 	[350] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2ab46,
+	.class_hid = BNXT_ULP_CLASS_HID_41405,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1321984UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 68352UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
 	},
 	[351] = {
-	.class_hid = BNXT_ULP_CLASS_HID_25226,
+	.class_hid = BNXT_ULP_CLASS_HID_51449,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 2362368UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 328448UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
 	},
 	[352] = {
-	.class_hid = BNXT_ULP_CLASS_HID_25cea,
+	.class_hid = BNXT_ULP_CLASS_HID_50b33,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 2370560UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 330496UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
 	},
 	[353] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2c82a,
+	.class_hid = BNXT_ULP_CLASS_HID_48c01,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 3410944UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 590592UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
 	},
 	[354] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2f9a2,
+	.class_hid = BNXT_ULP_CLASS_HID_483eb,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 3419136UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 592640UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
 	},
 	[355] = {
-	.class_hid = BNXT_ULP_CLASS_HID_23b56,
+	.class_hid = BNXT_ULP_CLASS_HID_5833f,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 537136128UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 852736UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
 	},
 	[356] = {
-	.class_hid = BNXT_ULP_CLASS_HID_205da,
+	.class_hid = BNXT_ULP_CLASS_HID_5937b,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 537144320UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 854784UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
 	},
 	[357] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2d8ce,
+	.class_hid = BNXT_ULP_CLASS_HID_41875,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 538184704UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 134284032UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[358] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2a2d2,
+	.class_hid = BNXT_ULP_CLASS_HID_40f5f,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 538192896UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 134286080UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[359] = {
-	.class_hid = BNXT_ULP_CLASS_HID_24a72,
+	.class_hid = BNXT_ULP_CLASS_HID_50f23,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 539233280UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 134546176UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[360] = {
-	.class_hid = BNXT_ULP_CLASS_HID_25476,
+	.class_hid = BNXT_ULP_CLASS_HID_51f6f,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 539241472UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 134548224UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[361] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2c076,
+	.class_hid = BNXT_ULP_CLASS_HID_4875b,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 540281856UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 134808320UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[362] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2f1ee,
+	.class_hid = BNXT_ULP_CLASS_HID_49727,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 540290048UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 134810368UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[363] = {
-	.class_hid = BNXT_ULP_CLASS_HID_20bb6,
+	.class_hid = BNXT_ULP_CLASS_HID_5976b,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1074007040UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 135070464UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[364] = {
-	.class_hid = BNXT_ULP_CLASS_HID_23d2e,
+	.class_hid = BNXT_ULP_CLASS_HID_58655,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1074015232UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 135072512UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[365] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2a96e,
+	.class_hid = BNXT_ULP_CLASS_HID_4125f,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1075055616UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 268501760UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[366] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2dae6,
+	.class_hid = BNXT_ULP_CLASS_HID_401f9,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1075063808UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 268503808UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[367] = {
-	.class_hid = BNXT_ULP_CLASS_HID_25af2,
+	.class_hid = BNXT_ULP_CLASS_HID_501cd,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1076104192UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 268763904UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[368] = {
-	.class_hid = BNXT_ULP_CLASS_HID_24c6a,
+	.class_hid = BNXT_ULP_CLASS_HID_51149,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1076112384UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 268765952UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[369] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2c7aa,
+	.class_hid = BNXT_ULP_CLASS_HID_49a67,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1077152768UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 269026048UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[370] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2c26e,
+	.class_hid = BNXT_ULP_CLASS_HID_489c1,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1077160960UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 269028096UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[371] = {
-	.class_hid = BNXT_ULP_CLASS_HID_203e2,
+	.class_hid = BNXT_ULP_CLASS_HID_58955,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1610877952UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 269288192UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[372] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2357a,
+	.class_hid = BNXT_ULP_CLASS_HID_59951,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1610886144UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 269290240UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[373] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2a0fa,
+	.class_hid = BNXT_ULP_CLASS_HID_40569,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1611926528UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 402719488UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[374] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2d272,
+	.class_hid = BNXT_ULP_CLASS_HID_41575,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1611934720UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 402721536UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[375] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2527e,
+	.class_hid = BNXT_ULP_CLASS_HID_51579,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1612975104UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 402981632UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[376] = {
-	.class_hid = BNXT_ULP_CLASS_HID_243f6,
+	.class_hid = BNXT_ULP_CLASS_HID_50463,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1612983296UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 402983680UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[377] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2fff6,
+	.class_hid = BNXT_ULP_CLASS_HID_48d71,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1614023680UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 403243776UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[378] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2e16e,
+	.class_hid = BNXT_ULP_CLASS_HID_49d7d,
 	.class_tid = 2,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1614031872UL,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 403245824UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
-		BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[379] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2422d,
+	.class_hid = BNXT_ULP_CLASS_HID_59d41,
 	.class_tid = 2,
 	.hdr_sig_id = 2,
-	.flow_sig_id = 265216UL,
+	.flow_sig_id = 403505920UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[380] = {
-	.class_hid = BNXT_ULP_CLASS_HID_20c69,
+	.class_hid = BNXT_ULP_CLASS_HID_58c6b,
 	.class_tid = 2,
 	.hdr_sig_id = 2,
-	.flow_sig_id = 273408UL,
+	.flow_sig_id = 403507968UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
+		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[381] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2e165,
+	.class_hid = BNXT_ULP_CLASS_HID_10255,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 1313792UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 265216UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8351,19 +8959,18 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
 	},
 	[382] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2aaa1,
+	.class_hid = BNXT_ULP_CLASS_HID_11675,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 1321984UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 273408UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8371,20 +8978,19 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
 	},
 	[383] = {
-	.class_hid = BNXT_ULP_CLASS_HID_253c1,
+	.class_hid = BNXT_ULP_CLASS_HID_14649,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 2362368UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1313792UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8392,19 +8998,19 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
 	},
 	[384] = {
-	.class_hid = BNXT_ULP_CLASS_HID_25d0d,
+	.class_hid = BNXT_ULP_CLASS_HID_15a69,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 2370560UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1321984UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8412,20 +9018,20 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
 	},
 	[385] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2c9cd,
+	.class_hid = BNXT_ULP_CLASS_HID_1205b,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 3410944UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 2362368UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8433,20 +9039,19 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
 	},
 	[386] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2f845,
+	.class_hid = BNXT_ULP_CLASS_HID_1347b,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 3419136UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 2370560UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8454,21 +9059,20 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
 	},
 	[387] = {
-	.class_hid = BNXT_ULP_CLASS_HID_25afd,
+	.class_hid = BNXT_ULP_CLASS_HID_16bbf,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 2147748864UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 3410944UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8476,19 +9080,20 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
 	},
 	[388] = {
-	.class_hid = BNXT_ULP_CLASS_HID_22439,
+	.class_hid = BNXT_ULP_CLASS_HID_1785f,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 2147757056UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 3419136UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8496,20 +9101,21 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
 	},
 	[389] = {
-	.class_hid = BNXT_ULP_CLASS_HID_290f9,
+	.class_hid = BNXT_ULP_CLASS_HID_11551,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 2148797440UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 537136128UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8517,20 +9123,19 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[390] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2c371,
+	.class_hid = BNXT_ULP_CLASS_HID_10897,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 2148805632UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 537144320UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8538,21 +9143,20 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[391] = {
-	.class_hid = BNXT_ULP_CLASS_HID_24355,
+	.class_hid = BNXT_ULP_CLASS_HID_15955,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 2149846016UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 538184704UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8560,20 +9164,20 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[392] = {
-	.class_hid = BNXT_ULP_CLASS_HID_275dd,
+	.class_hid = BNXT_ULP_CLASS_HID_14c8b,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 2149854208UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 538192896UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8581,21 +9185,21 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[393] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2e19d,
+	.class_hid = BNXT_ULP_CLASS_HID_13b47,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 2150894592UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 539233280UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8603,21 +9207,20 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[394] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2d015,
+	.class_hid = BNXT_ULP_CLASS_HID_12e85,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 2150902784UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 539241472UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8625,22 +9228,21 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[395] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2560d,
+	.class_hid = BNXT_ULP_CLASS_HID_17f5b,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 4295232512UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 540281856UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8648,19 +9250,21 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[396] = {
-	.class_hid = BNXT_ULP_CLASS_HID_21049,
+	.class_hid = BNXT_ULP_CLASS_HID_17299,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 4295240704UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 540290048UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8668,20 +9272,22 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
 	},
 	[397] = {
-	.class_hid = BNXT_ULP_CLASS_HID_28c09,
+	.class_hid = BNXT_ULP_CLASS_HID_10fe7,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 4296281088UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1074007040UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8689,20 +9295,19 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[398] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2be89,
+	.class_hid = BNXT_ULP_CLASS_HID_10325,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 4296289280UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1074015232UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8710,21 +9315,20 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[399] = {
-	.class_hid = BNXT_ULP_CLASS_HID_267a9,
+	.class_hid = BNXT_ULP_CLASS_HID_153cb,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 4297329664UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1075055616UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8732,20 +9336,20 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[400] = {
-	.class_hid = BNXT_ULP_CLASS_HID_261ed,
+	.class_hid = BNXT_ULP_CLASS_HID_14709,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 4297337856UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1075063808UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8753,21 +9357,21 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[401] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2ddad,
+	.class_hid = BNXT_ULP_CLASS_HID_12dc5,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 4298378240UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1076104192UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8775,21 +9379,20 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[402] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2cc2d,
+	.class_hid = BNXT_ULP_CLASS_HID_1212b,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 4298386432UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1076112384UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8797,22 +9400,21 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[403] = {
-	.class_hid = BNXT_ULP_CLASS_HID_26edd,
+	.class_hid = BNXT_ULP_CLASS_HID_171c9,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 6442716160UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1077152768UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8820,20 +9422,21 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[404] = {
-	.class_hid = BNXT_ULP_CLASS_HID_22819,
+	.class_hid = BNXT_ULP_CLASS_HID_1650f,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 6442724352UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1077160960UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8841,21 +9444,22 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[405] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2a4d9,
+	.class_hid = BNXT_ULP_CLASS_HID_10201,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 6443764736UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1610877952UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8863,21 +9467,20 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[406] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2d759,
+	.class_hid = BNXT_ULP_CLASS_HID_116c1,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 6443772928UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1610886144UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8885,22 +9488,21 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[407] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2573d,
+	.class_hid = BNXT_ULP_CLASS_HID_14605,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 6444813312UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1611926528UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8908,21 +9510,21 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[408] = {
-	.class_hid = BNXT_ULP_CLASS_HID_279bd,
+	.class_hid = BNXT_ULP_CLASS_HID_15a05,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 6444821504UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1611934720UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8930,22 +9532,22 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[409] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2f27d,
+	.class_hid = BNXT_ULP_CLASS_HID_12007,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 6445861888UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1612975104UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8953,22 +9555,21 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[410] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2e4fd,
+	.class_hid = BNXT_ULP_CLASS_HID_13407,
 	.class_tid = 2,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 6445870080UL,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 1612983296UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -8976,23 +9577,22 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[411] = {
-	.class_hid = BNXT_ULP_CLASS_HID_24fbe,
+	.class_hid = BNXT_ULP_CLASS_HID_1640b,
 	.class_tid = 2,
 	.hdr_sig_id = 3,
-	.flow_sig_id = 265216UL,
+	.flow_sig_id = 1614023680UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -9001,18 +9601,21 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
-		BNXT_ULP_HDR_BIT_I_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[412] = {
-	.class_hid = BNXT_ULP_CLASS_HID_201fa,
+	.class_hid = BNXT_ULP_CLASS_HID_1780b,
 	.class_tid = 2,
 	.hdr_sig_id = 3,
-	.flow_sig_id = 273408UL,
+	.flow_sig_id = 1614031872UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
@@ -9021,2202 +9624,16438 @@  struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
 		BNXT_ULP_HDR_BIT_I_IPV6 |
-		BNXT_ULP_HDR_BIT_I_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
+		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
 	},
 	[413] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2ecf6,
+	.class_hid = BNXT_ULP_CLASS_HID_404b0,
 	.class_tid = 2,
-	.hdr_sig_id = 3,
-	.flow_sig_id = 1313792UL,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 66304UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV6 |
-		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI }
 	},
 	[414] = {
-	.class_hid = BNXT_ULP_CLASS_HID_2a732,
+	.class_hid = BNXT_ULP_CLASS_HID_4148c,
 	.class_tid = 2,
-	.hdr_sig_id = 3,
-	.flow_sig_id = 1321984UL,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 68352UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV6 |
-		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI }
 	},
 	[415] = {
-	.class_hid = BNXT_ULP_CLASS_HID_25e52,
+	.class_hid = BNXT_ULP_CLASS_HID_514c0,
 	.class_tid = 2,
-	.hdr_sig_id = 3,
-	.flow_sig_id = 2362368UL,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 328448UL,
 	.flow_pattern_id = 1,
 	.app_sig = 0,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV6 |
-		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+	},
+	[416] = {
+	.class_hid = BNXT_ULP_CLASS_HID_50bba,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 330496UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+	},
+	[417] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48c88,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 590592UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+	},
+	[418] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48362,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 592640UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+	},
+	[419] = {
+	.class_hid = BNXT_ULP_CLASS_HID_583b6,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 852736UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+	},
+	[420] = {
+	.class_hid = BNXT_ULP_CLASS_HID_593f2,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 854784UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+	},
+	[421] = {
+	.class_hid = BNXT_ULP_CLASS_HID_41f54,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 536937216UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[422] = {
+	.class_hid = BNXT_ULP_CLASS_HID_40fce,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 536939264UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[423] = {
+	.class_hid = BNXT_ULP_CLASS_HID_50e02,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 537199360UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[424] = {
+	.class_hid = BNXT_ULP_CLASS_HID_51e5e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 537201408UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[425] = {
+	.class_hid = BNXT_ULP_CLASS_HID_487ca,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 537461504UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[426] = {
+	.class_hid = BNXT_ULP_CLASS_HID_49606,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 537463552UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[427] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5965a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 537723648UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[428] = {
+	.class_hid = BNXT_ULP_CLASS_HID_58514,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 537725696UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[429] = {
+	.class_hid = BNXT_ULP_CLASS_HID_412c2,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1073808128UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[430] = {
+	.class_hid = BNXT_ULP_CLASS_HID_401ac,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1073810176UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[431] = {
+	.class_hid = BNXT_ULP_CLASS_HID_501e0,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1074070272UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[432] = {
+	.class_hid = BNXT_ULP_CLASS_HID_511cc,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1074072320UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[433] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4990a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1074332416UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[434] = {
+	.class_hid = BNXT_ULP_CLASS_HID_489e4,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1074334464UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[435] = {
+	.class_hid = BNXT_ULP_CLASS_HID_589c8,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1074594560UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[436] = {
+	.class_hid = BNXT_ULP_CLASS_HID_59804,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1074596608UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[437] = {
+	.class_hid = BNXT_ULP_CLASS_HID_40404,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1610679040UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[438] = {
+	.class_hid = BNXT_ULP_CLASS_HID_41440,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1610681088UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[439] = {
+	.class_hid = BNXT_ULP_CLASS_HID_51484,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1610941184UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[440] = {
+	.class_hid = BNXT_ULP_CLASS_HID_50b0e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1610943232UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[441] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48c4c,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1611203328UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[442] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48306,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1611205376UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[443] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5830a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1611465472UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[444] = {
+	.class_hid = BNXT_ULP_CLASS_HID_59346,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 1611467520UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[445] = {
+	.class_hid = BNXT_ULP_CLASS_HID_102cc,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 265216UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI }
+	},
+	[446] = {
+	.class_hid = BNXT_ULP_CLASS_HID_116ec,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 273408UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI }
+	},
+	[447] = {
+	.class_hid = BNXT_ULP_CLASS_HID_146d0,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 1313792UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+	},
+	[448] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15af0,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 1321984UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+	},
+	[449] = {
+	.class_hid = BNXT_ULP_CLASS_HID_120c2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 2362368UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+	},
+	[450] = {
+	.class_hid = BNXT_ULP_CLASS_HID_134e2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 2370560UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+	},
+	[451] = {
+	.class_hid = BNXT_ULP_CLASS_HID_16b26,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 3410944UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+	},
+	[452] = {
+	.class_hid = BNXT_ULP_CLASS_HID_178c6,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 3419136UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+	},
+	[453] = {
+	.class_hid = BNXT_ULP_CLASS_HID_115c6,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 2147748864UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[454] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10804,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 2147757056UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[455] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15822,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 2148797440UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[456] = {
+	.class_hid = BNXT_ULP_CLASS_HID_14c60,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 2148805632UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[457] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13bd4,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 2149846016UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[458] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12e12,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 2149854208UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[459] = {
+	.class_hid = BNXT_ULP_CLASS_HID_17e30,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 2150894592UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[460] = {
+	.class_hid = BNXT_ULP_CLASS_HID_17276,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 2150902784UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+	},
+	[461] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11f1a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 4295232512UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[462] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11358,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 4295240704UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[463] = {
+	.class_hid = BNXT_ULP_CLASS_HID_14398,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 4296281088UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[464] = {
+	.class_hid = BNXT_ULP_CLASS_HID_157b8,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 4296289280UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[465] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13d68,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 4297329664UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[466] = {
+	.class_hid = BNXT_ULP_CLASS_HID_131aa,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 4297337856UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[467] = {
+	.class_hid = BNXT_ULP_CLASS_HID_16192,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 4298378240UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[468] = {
+	.class_hid = BNXT_ULP_CLASS_HID_175b2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 4298386432UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[469] = {
+	.class_hid = BNXT_ULP_CLASS_HID_112b2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 6442716160UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[470] = {
+	.class_hid = BNXT_ULP_CLASS_HID_106f0,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 6442724352UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[471] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15692,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 6443764736UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[472] = {
+	.class_hid = BNXT_ULP_CLASS_HID_14ad0,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 6443772928UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[473] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13080,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 6444813312UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[474] = {
+	.class_hid = BNXT_ULP_CLASS_HID_124c2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 6444821504UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[475] = {
+	.class_hid = BNXT_ULP_CLASS_HID_174e0,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 6445861888UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[476] = {
+	.class_hid = BNXT_ULP_CLASS_HID_16f22,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 6445870080UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+	},
+	[477] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4025b,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 66304UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI }
+	},
+	[478] = {
+	.class_hid = BNXT_ULP_CLASS_HID_41267,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 68352UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI }
+	},
+	[479] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5122b,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 328448UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
+	},
+	[480] = {
+	.class_hid = BNXT_ULP_CLASS_HID_50d51,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 330496UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
+	},
+	[481] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48a63,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 590592UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+	},
+	[482] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48589,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 592640UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+	},
+	[483] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5855d,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 852736UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+	},
+	[484] = {
+	.class_hid = BNXT_ULP_CLASS_HID_59519,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 854784UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+	},
+	[485] = {
+	.class_hid = BNXT_ULP_CLASS_HID_41e17,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 134284032UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+	},
+	[486] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4093d,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 134286080UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+	},
+	[487] = {
+	.class_hid = BNXT_ULP_CLASS_HID_50941,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 134546176UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+	},
+	[488] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5190d,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 134548224UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+	},
+	[489] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48139,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 134808320UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+	},
+	[490] = {
+	.class_hid = BNXT_ULP_CLASS_HID_49145,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 134810368UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+	},
+	[491] = {
+	.class_hid = BNXT_ULP_CLASS_HID_59109,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 135070464UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+	},
+	[492] = {
+	.class_hid = BNXT_ULP_CLASS_HID_58037,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 135072512UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+	},
+	[493] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4143d,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 268501760UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[494] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4079b,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 268503808UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[495] = {
+	.class_hid = BNXT_ULP_CLASS_HID_507af,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 268763904UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[496] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5172b,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 268765952UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[497] = {
+	.class_hid = BNXT_ULP_CLASS_HID_49c05,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 269026048UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[498] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48fa3,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 269028096UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[499] = {
+	.class_hid = BNXT_ULP_CLASS_HID_58f37,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 269288192UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[500] = {
+	.class_hid = BNXT_ULP_CLASS_HID_59f33,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 269290240UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[501] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4030b,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 402719488UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[502] = {
+	.class_hid = BNXT_ULP_CLASS_HID_41317,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 402721536UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[503] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5131b,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 402981632UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[504] = {
+	.class_hid = BNXT_ULP_CLASS_HID_50201,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 402983680UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[505] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48b13,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 403243776UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[506] = {
+	.class_hid = BNXT_ULP_CLASS_HID_49b1f,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 403245824UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[507] = {
+	.class_hid = BNXT_ULP_CLASS_HID_59b23,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 403505920UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[508] = {
+	.class_hid = BNXT_ULP_CLASS_HID_58a09,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 403507968UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+	},
+	[509] = {
+	.class_hid = BNXT_ULP_CLASS_HID_419bf,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 536937216UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+	},
+	[510] = {
+	.class_hid = BNXT_ULP_CLASS_HID_40925,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 536939264UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+	},
+	[511] = {
+	.class_hid = BNXT_ULP_CLASS_HID_508e9,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 537199360UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+	},
+	[512] = {
+	.class_hid = BNXT_ULP_CLASS_HID_518b5,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 537201408UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+	},
+	[513] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48121,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 537461504UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+	},
+	[514] = {
+	.class_hid = BNXT_ULP_CLASS_HID_490ed,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 537463552UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+	},
+	[515] = {
+	.class_hid = BNXT_ULP_CLASS_HID_590b1,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 537723648UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+	},
+	[516] = {
+	.class_hid = BNXT_ULP_CLASS_HID_583ff,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 537725696UL,
+	.flow_pattern_id = 1,
+	.app_sig = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV6 |
+		BNXT_ULP_HDR_BIT_I_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }